Ex Parte Barnes et al

Board of Patent Appeals and Interferences

Feb 28, 2011

10010161 (B.P.A.I. Feb. 28, 2011)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/010,161 11/13/2001 Brian C. Barnes 2000.056700 7264
92585 7590 02/28/2011
Advanced Micro Devices, Inc.
c/o Williams, Morgan & Amerson, P.C.
10333 Richmond, Suite 1100
Houston, TX 77042
EXAMINER
ABYANEH, ALI S
ART UNIT PAPER NUMBER
2437
MAIL DATE DELIVERY MODE
02/28/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte BRIAN C. BARNES, GEOFFREY S. STRONGIN, and
RODNEY W. SCHMIDT
____________________

Appeal 2009-008001
Application 10/010,161
Technology Center 2400
____________________

Before JOSEPH F. RUGGIERO, CARLA M. KRIVAK, and
CARL W. WHITEHEAD, JR., Administrative Patent Judges.

KRIVAK, Administrative Patent Judge.

DECISION ON APPEAL1
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-37. We have jurisdiction under 35 U.S.C. § 6(b).
We reverse and enter a new ground of rejection under 37 C.F.R.
§ 41.50(b).

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, or for filing a request for rehearing,
as recited in 37 C.F.R. § 41.52, begins to run from the “MAIL DATE”
(paper delivery mode) or the “NOTIFICATION DATE” (electronic delivery
mode) shown on the PTOL-90A cover letter attached to this decision.
Appeal 2009-008001
Application 10/010,161

2
STATEMENT OF THE CASE
Appellants’ claimed invention relates to protecting data stored in a
memory from unauthorized access (Spec. 10:7-9).
Independent claim 1, reproduced below, is representative of the
subject matter on appeal:
1. A memory management unit for managing a memory storing
data arranged within a plurality of memory pages, the memory
management unit comprising:

a security check unit coupled to receive a linear address
generated during execution of a current instruction, wherein the
linear address has a corresponding physical address residing
within a selected memory page, and wherein the security check
unit is configured to use the linear address to access at least one
security attribute data structure located in the memory to obtain
a security attribute of the selected memory page, to compare a
numerical value conveyed by a security attribute of the current
instruction to a numerical value conveyed by the security
attribute of the selected memory page, and to produce an output
signal dependent upon a result of the comparison; and

wherein the memory management unit is configured to access
the selected memory page dependent upon the output signal.

REJECTIONS
The Examiner rejected claims 1-9, 11-19, 21, 23-25, 27-34, 36, and 37
under 35 U.S.C. § 102(b) as anticipated by Maruyama (US 6,052,763).
The Examiner rejected claims 10, 20, 22, 26, and 35 under 35 U.S.C.
§ 103(a) based upon the teachings of Maruyama and Appellants’ admitted
prior art (APA).

Appeal 2009-008001
Application 10/010,161

3
ANALYSIS
The Examiner finds Maruyama teaches a Master ID Table (24),
meeting the limitation of “at least one security attribute data structure” (Ans.
9-10). The Examiner further finds Maruyama teaches the Master ID Table
and a DRAM (19) are located within a memory unit (10), thus providing a
memory that includes both the security attribute data structure and a selected
memory page, as claimed (Ans. 10).
Appellants contend Maruyama’s Master ID Table is stored in an
EEPROM or battery back-up RAM separate from the DRAM that includes
the accessed memory pages (App. Br. 9-10; Reply Br. 5). Thus, Appellants
argue, Maruyama does not suggest a memory that includes the security
attribute data structure and the selected memory page (App. Br. 10; Reply
Br. 5). We agree.
Maruyama’s Master ID Table and DRAM are not part of the same
memory because Maruyama’s memory unit is not itself a “memory” as
claimed. Rather, Maruyama’s memory unit comprises a number of
components, one being the DRAM, i.e., a memory, and another separate
component being the Master ID Table (Maruyama Fig. 4). Therefore,
Maruyama does not anticipate claims 1, 11, 12, 13, 23, and 32, in addition to
claims 2-9, 14-19, 21, 24, 25, 27-31, 33, 34, 36, and 37, which are not
argued separately.2

2 Appellants do not include claims 14-19, 21, 24, 25, 27-31, 33, and 34 in
the “Grounds of Rejection to be Reviewed on Appeal” or in any claim
grouping in the “Argument” (App. Br. 7-14). However, Appellants request
reversal of the Examiner’s rejection of all pending claims (App. Br. 15).
Thus, we apply Appellants’ arguments regarding the independent claims to
Appeal 2009-008001
Application 10/010,161

4
The obviousness rejection of claims 10, 20, 22, 26, and 35, which
depend from claims 1, 13, and 23, is reversed for the same reasons described
above.

NEW GROUND OF REJECTION
Pursuant to 37 C.F.R. § 41.50(b), we enter a new ground of rejection.
Claims 1, 11, and 12 are rejected under 35 U.S.C. § 102(a) as anticipated by
Appellants’ admitted prior art (Spec. 3:11-6:3).
Appellants’ Specification provides a “popular 80x86 (x86) processor
architecture includes specialized hardware elements to support a protected
virtual address mode (i.e., a protected mode)” (Spec. 3:11-12). Figs 1-3,
which are each labeled “Prior Art,” illustrate “how an x86 processor
implements both virtual memory and memory protection features” (Spec.
3:12-14). Fig. 1 shows a “well-known linear-to-physical address translation
mechanism 100 of the x86 processor” (Spec. 3:14-15), wherein a memory
location 116 within a page frame 108 has a physical address resulting from
the linear-to-physical address translation (Spec. 5:1-3). To provide
protection to the memory page being accessed, the x86 processor
architecture implements a user/supervisor (U/S) bit in each of a page
directory entry format 200 and a page table entry format 300 (Spec. 5:4-6;
Figs. 2 and 3). A page directory 104, which includes the page directory
entry format, “is always located within the memory (e.g., the main memory
unit)” (Spec. 3:21). A page table 106, which includes the page table entry
format, and page frame 108, are also “assumed to reside in the memory”

dependent claims 14-19, 21, 24, 25, 27-31, 33, and 34, and find these claims
also not anticipated.
Appeal 2009-008001
Application 10/010,161

5
(Spec. 3:22-23). The U/S bits in the page directory entry and the page table
entry are logically ANDed to determine whether access to the page frame is
authorized (Spec. 5:19-22). Thus, the U/S bit in each of the page directory
entry and page table entry meets the claimed limitation of “at least one
security attribute data structure located in the memory to obtain a security
attribute of the selected memory page.”
Further, authorization depends on comparing the U/S bits derived
from the linear address to the privilege level of the program being executed
by the x86 processor. A memory page protected by U/S=0, i.e., a supervisor
level memory page, can only be accessed by a program with a corresponding
current privilege level 0 (CPL0), i.e., a supervisor level of the current
executing program (Spec. 5:7-10). A memory page with U/S=1, i.e., a user
level memory page, can be accessed by a program with a corresponding
current privilege level of CPL1, CPL2, or CPL3, i.e., user levels of the
current executing program (Spec. 5:11-13). Thus, Appellants’ admitted
prior art also meets the claimed limitations “to compare a numerical value
conveyed by a security attribute of the current instruction to a numerical
value conveyed by the security attribute of the selected memory page, and to
produce an output signal dependent upon a result of the comparison” and
“wherein the memory management unit is configured to access the selected
memory page dependent upon the output signal.”
Therefore, the admitted prior art in the Specification, as described
above, meets all of the limitations of claims 1, 11, and 12.

DECISION
The Examiner’s decision rejecting claims 1-37 is reversed.
Appeal 2009-008001
Application 10/010,161

6
A new ground of rejection for claims 1, 11, and 12 under 35 U.S.C.
§ 102(a) is entered.

TIME PERIOD
This decision contains a new ground of rejection pursuant to 37
C.F.R. § 41.50(b). 37 C.F.R. § 41.50(b) also provides that the Appellants,
WITHIN TWO MONTHS FROM THE DATE OF THE DECISION, must
exercise one of the following two options with respect to the new ground of
rejection to avoid termination of the appeal as to the rejected claims:
(1) Submit an appropriate amendment of the claims so rejected
or new evidence relating to the claims so rejected, or both, and
have the matter reconsidered by the examiner, in which event
the proceeding will be remanded to the examiner. . . .

(2) Request that the proceeding be reheard under § 41.52 by the
Board upon the same record. . . .

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv)(2010).

REVERSED
37 C.F.R. § 41.50(b)

kis
Advanced Micro Devices, Inc.
c/o Williams, Morgan & Amerson, P.C.
10333 Richmond, Suite 1100
Houston TX 77042