Ex Parte Bakke

Board of Patent Appeals and Interferences

Sep 23, 2008

10228036 (B.P.A.I. Sep. 23, 2008)

UNITED STATES PATENT AND TRADEMARK OFFICE 1
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BEFORE THE BOARD OF PATENT APPEALS 4
AND INTERFERENCES 5
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Ex parte BRIAN E. BAKKE 8
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Appeal 2007-3989 11
Application 10/228,0361 12
Technology Center 2100 13
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Decided: September 23, 2008 16
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Before HOWARD B. BLANKENSHIP, ALLEN R. MACDONALD, and 20
CAROLYN D. THOMAS, Administrative Patent Judges. 21
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THOMAS, C., Administrative Patent Judge. 23
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DECISION ON APPEAL 25
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1 Application filed August 26, 2002. The real party in interest is
International Business Machines Corporation.
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Application 10/228,036

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I. STATEMENT OF THE CASE 1
Appellant appeals under 35 U.S.C. § 134 from a final rejection 2
of claims 1-7, 10-18, 21, and 23-28 mailed February 17, 2006. We have 3
jurisdiction under 35 U.S.C. § 6(b). 4
We reverse. 5
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A. INVENTION 7
Appellant invented a system and method for reading the internal 8
address space of an adapter in a system during a dump. The adapter includes 9
a control port and a data port used as channels for exchanging control 10
messages and dump data between the adapter and the system. The system 11
starts the dump by sending to the data port a specification of a block of the 12
adapter’s internal address space. In response, the adapter sends dump data 13
portions to a system buffer via the data port. (Spec., Abstract.) 14
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B. ILLUSTRATIVE CLAIM 16
The appeal contains claims 1-7, 10-18, 21, and 23-28. Claims 8, 9, 17
19, 20, and 22 are canceled. Claims 1, 12, 23, and 26 are independent 18
claims. Claim 1 is illustrative: 19
1. A method of reading internal addresses space of an 20
adapter having a data port at an address, comprising: 21
enabling the data port, in response to detecting a system 22
address of the data port on an address bus, by the adapter; 23
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sending to the data port a first address token specifying a 1
first block of the internal address space of the adapter to be read, 2
wherein the first block comprises a plurality of data portions; 3
sending to a control port of the adapter, a message 4
indicating the presence of the first address token in the data port; 5
responsive to receipt of the first address token and the 6
message by the adapter: putting, by the adapter, a first data portion of 7
the first block in the data port; 8
putting, by the adapter, a data validation message in a 9
control port, the data validation message indicating the presence of the 10
first data portion of the first block in the data port; 11
detecting, by a processor monitoring the control port, the 12
data validation message in the control port; and 13
responsive to detecting the data validation message by 14
the processor: reading, by the processor, the first data portion from the 15
data port. 16
17
C. REFERENCES 18
The references relied upon by the Examiner in rejecting the claims on 19
appeal are as follows: 20
Cramer US 4,065,810 Dec. 27, 1977 21
Andrews US 5,634,099 May 27, 1997 22
23
Applicant Admitted Prior Art (AAPA), see Specification, paragraphs 24
[0001]–[0005]. 25
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D. REJECTIONS 27
The Examiner entered the following rejections which are before us for 28
review: 29
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Claims 1-7, 10-18, 21, and 23-25 are rejected under 35 U.S.C. 1
§ 103(a) as being unpatentable over Cramer in view of Andrews. 2
Claims 26-28 are rejected under 35 U.S.C. § 103(a) as being 3
unpatentable over Cramer in view of Andrews and further in view of AAPA. 4
5
II. PROSECUTION HISTORY 6
Appellant appealed from the Final Rejection and filed an Appeal Brief 7
(App. Br.) on September 5, 2006. The Examiner mailed an Examiner’s 8
Answer (Ans.) on October 26, 2006. Appellant filed a Reply Brief (Reply 9
Br.) on December 21, 2006. 10
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III. ISSUE 12
Whether Appellants have shown that the Examiner erred in rejecting 13
the claims as being obvious over the combination of cited references. 14
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IV. FINDINGS OF FACT 16
The following findings of fact (FF) are supported by a preponderance 17
of the evidence. 18
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Cramer 20
1. Cramer discloses a data transfer system for “transferring data from 21
an external device such as a modem to a memory associated with the 22
processor via an I/O bus . . .” (Col. 1, ll. 8-13). 23
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2. Cramer discloses that “[f]or transferring data from the external 1
device to the memory, three addresses are stored in the registers of the 2
external device. Each address defines an address in memory which contains 3
a pointer address.” (Col. 1, ll. 58-62.) 4
3. Cramer discloses that “[a] control program . . . monitors the status 5
table and either transfers the data stored in a filled block and resets the 6
second pointer or . . .” (Col. 2, ll. 13-15.) 7
8
Andrews 9
4. Andrews discloses “a data processing system that includes multiple 10
processors that utilize direct memory access to transfer data between 11
individual memories that are associated with the processors.” (Col. 1, ll. 8-12
11.) 13
5. Andrews discloses “means for performing direct memory access 14
operations between said first and second memories along said bus on behalf 15
of said second processor . . .” (Col. 2, ll. 2-4.) 16
17
V. PRINCIPLES OF LAW 18
The question of obviousness is "based on underlying factual 19
determinations including . . . what th[e] prior art teaches explicitly and 20
inherently . . . ." In re Zurko, 258 F.3d 1379, 1383 (Fed. Cir. 2001) (citing 21
Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966); In re Dembiczak, 175 22
F.3d 994, 998 (Fed. Cir. 1999); In re Napier, 55 F.3d 610, 613 (Fed. Cir. 23
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1995)). "In rejecting claims under 35 U.S.C. § 103, the examiner bears the 1
initial burden of presenting a prima facie case of obviousness." In re 2
Rijckaert, 9 F.3d 1531, 1532 (Fed. Cir. 1993) (citing In re Oetiker, 977 F.2d 3
1443, 1445 (Fed. Cir. 1992)). "'A prima facie case of obviousness is 4
established when the teachings from the prior art itself would appear to have 5
suggested the claimed subject matter to a person of ordinary skill in the art.'" 6
In re Bell, 991 F.2d 781, 783 (Fed. Cir. 1993) (quoting In re Rinehart, 531 7
F.2d 1048, 1051 (CCPA 1976)). 8
Appellants have the burden on appeal to the Board to demonstrate 9
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86 10
(Fed. Cir. 2006) (“On appeal to the Board, an applicant can overcome a 11
rejection [under § 103] by showing insufficient evidence of prima facie 12
obviousness or by rebutting the prima facie case with evidence of secondary 13
indicia of nonobviousness.”) (quoting In re Rouffet, 149 F.3d 1350, 1355 14
(Fed. Cir. 1998)). 15
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VI. ANALYSIS 17
Common Feature In All Claims 18
Our representative claim, claim 1, recites, inter alia, “. . . a first 19
address token specifying a first block of the internal address space of the 20
adapter,” “. . . a control port of the adapter” and “. . . monitoring the 21
control port.” Independent claims 12, 23, and 26 recite similar limitations. 22
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Thus, the scope of each of the independent claims includes at least the above 1
noted limitations. 2
3
The Obviousness Rejection 4
We now consider the Examiner’s rejection of representative claim 1 5
under 35 U.S.C. § 103(a) as being obvious over the combination of Cramer 6
and Andrews. 7
Appellant contends: 8
Thus, rather than the processor monitoring the control port of 9
the adapter (which necessarily requires some affirmative 10
outbound signaling from the processor), Cramer teaches that 11
the adapter must notify the processor when the adapter wishes 12
to transfer signals to the processor. 13
(App. Br. 13; see also Reply Br. 3.) 14
Appellant further contends that Andrews’ “technology is not related to 15
transferring memory from an adapter.” (App. Br. 14.) 16
The Examiner found that “Cramer et al. do teach that the disclosed 17
method and apparatus are applicable to a full-duplex operation where data 18
from the internal address space of the adapter is transported to the memory 19
unit connected to the memory bus . . .” (Ans. 6). We disagree. 20
The Examiner seems to suggest that the limitation of “specifying . . . 21
internal address space of the adapter” is taught by Cramer’s disclosure of 22
the full-duplex operation. However, we find that Cramer’s full-duplex 23
operation is merely illustrated to show the “register requirement” for the 24
memory. (Cramer, Col. 5, ll. 51-63.) We do not readily find nor has the 25
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Examiner shown how such a full-duplex operation specifies a block of 1
internal address space of the adapter. Instead, Cramer discloses transferring 2
data by utilizing addresses stored in registers of the external device (FF 1-2). 3
The Examiner further found that Andrews illustrates specifying 4
internal address space by illustrating “an adapter referred to as the ‘Direct 5
Access Memory Unit (DAU)’ to perform data transfer between the memory 6
of a host processor and the memory of a remote processor.” (Ans. 6.) We 7
disagree. 8
While Andrews discloses utilizing direct memory access to transfer 9
data between memories (FF 4-5), we do not readily find and the Examiner 10
has not shown how Andrews sends to a data port an address token specifying 11
the internal address space of the DMA unit itself, as required by claim 1. 12
Regarding “monitoring the control port” limitation, we find that 13
Cramer merely discloses that a control program monitors a status table 14
located in the memory itself (FF 3). Thus, we find that Cramer’s monitoring 15
of a table in the processor’s memory is distinguishable from the claimed 16
monitoring of the control port in the adapter. 17
As such, we can only rule on the basis of the evidence that is provided 18
in support of the rejection, and we find it deficient here. The allocation of 19
burdens requires that the USPTO produce the factual basis for its rejection 20
of an application under 35 U.S.C. §§ 102 and 103. In re Piasecki, 745 F.2d 21
1468, 1472 (Fed. Cir. 1984) (citing In re Warner, 379 F.2d 1011, 1016 22
(CCPA 1967)). The one who bears the initial burden of presenting a prima 23
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facie case of unpatentability is the Examiner. In re Oetiker, 977 F.2d 1443, 1
1445 (Fed. Cir. 1992). 2
The absence of the above-noted limitations negates obviousness. 3
Therefore, we reverse the obviousness rejection of claim 1 and of 4
claims 2-7, 10-18, 21, and 23-28, which stand therewith. 5
6
VII. CONCLUSIONS 7
We conclude that Appellant has shown that the Examiner erred in 8
rejecting claims 1-7, 10-18, 21, and 23-28. 9
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VIII. DECISION 11
In view of the foregoing discussion, we reverse the Examiner’s 12
rejection of claims 1-7, 10-18, 21, and 23-28. 13
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REVERSED 15
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rwk 21
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IBM CORPORATION, INTELLECTUAL PROPERTY LAW 23
DEPT 917, BLDG. 006-1 24
3605 HIGHWAY 52 NORTH 25
ROCHESTER MN 55901-7829 26
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