Ex Parte BAEK et al

Patent Trial and Appeal Board

Mar 14, 2016

12614549 (P.T.A.B. Mar. 14, 2016)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
12/614,549 11109/2009
20987 7590 03/16/2016
VOLENTINE & WHITT PLLC
ONE FREEDOM SQUARE
11951 FREEDOM DRIVE, SUITE 1300
RESTON, VA 20190
FIRST NAMED INVENTOR
Dong-hoon BAEK
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
SEC.2491 8804
EXAMINER
ZHENG, CHARLES H
ART UNIT PAPER NUMBER
2622
NOTIFICATION DATE DELIVERY MODE
03/16/2016 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address( es):
cjohnson@volentine.com
aloomis@volentine.com
iplaw@volentine.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte DONG-HOON BAEK, JI-HOON KIM,
JUNG-PIL LIM, and JAE-YOUL LEE
Appeal2014-003107
Application 12/614,549
Technology Center 2600
Before ST. JOHN COURTENAY III, THU A. DANG, and
LARRY J. HUME, Administrative Patent Judges.
DANG, Administrative Patent Judge.
DECISION ON APPEAL
Appeal2014-003107
Application 12/614,549
I.STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 4, and 6-17. Appellants have previously canceled claims 1-3 and 5.
We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM
A. INVENTION
According to Appellants, the claimed invention relates to "an interface
method for data transmission (TX) and receive (RX) system. More
particularly, the inventive concept relates to an interface method for a data
TX/RX system communicating a data stream using a point to point
transmission approach. Spec. i-f 2.
B. ILLUSTRATIVE CLAIM
Claim 4 is exemplary:
4. An interface method for a data transmitting and rece1vmg
system comprising a timing controller and a source driver driving
display data to a panel display, the method comprising:
operating in a reset mode during which a value stored in a register
of the source driver is initialized in response to (a) an indication
that the timing controller is communicating a current data stream,
and (b) a power-up detection for the source driver or the timing
controller;
operating in a receive ready mode during which the source driver
prepares to receive payload data contained in the current data
stream; and
operating in a setup mode during which control data contained in
the current data stream updates data stored in a register of the
source driver
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C. REJECTIONS
The prior art relied upon by the Examiner as evidence in rejecting the
claims on appeal is:
Yi US 2006/0244708 Al Nov. 2, 2006
RapidIO Interconnet Specification Part VI: Physical Layer lx/4x LP-
Serial Specification, RapidIO Trade Association, Rev 1.2 (06/2002).
(hereinafter "RapidIO").
MPC8548E PowerQUICC Ill Integrated Processor Hardware
Specifications, Freescale Semiconductor, Inc. (2009).
(hereinafter "Freescale").
Claims 4, 6-10, and 12-17 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over the combination of Yi and RapidIO.
Claim 11 stands rejected under 35 U.S.C. § 103(a) as being
unpatentable over the combination of Yi, RapidIO, and Freescale.
II. ISSUE
The principal issue before us is whether the Examiner erred in finding
the combination of Yi and RapidIO teaches or would have suggested
"operating in a setup mode during which control data contained in the
current data stream updates data stored in a register of the source driver."
(claim 4, emphasis added).
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Application 12/614,549
Ill. FINDINGS OF FACT
The following findings of Fact (FF) are shown by a preponderance of
the evidence.
Yi
1. Yi discloses a control board 504and a source driver 510 driving
data on an LCD flat screen display. (Fig. 5a, i-f7).
Rapid!O
2. RapidIO discloses a "DISCOVERY state" during which the
"output drivers" are enabled, and "bit synchronization" and "alignment" are
accomplished. (VI-63).
3. RapidIO also discloses "the lx/4x LP-Serial Command and Status
Register (CSR) set. All registers in the set are 32-bits long and aligned to a
32-bit boundary. These registers allow an external processing element to
determine the capabilities, configuration, and status of a processing element
using this lx/4x LP-Serial physical layer. The registers can be accessed
using the maintenance operations defined in Part I: Input/Output Logical
Specification." (VI-89).
4. "[L]ane_sync ... indicates the bit and code-group boundary
alignment synchronization state of a lane receiver" and "it is also used to
indicate the presence of a link partner. A link partner is declared to be
present when either lane_sync[O] or lane_sync[2] is asserted which causes
the state machine to enter the DISCOVERY state." (Vl-62).
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IV. ANALYSIS
Appellants contend that, although the Examiner concluded that the
"DISCOVERY state" of Rapid!O may be interpreted as the setup mode of
claim 4,
[t]he first paragraph on page VI-63 of Rapid!O as specifically
relied upon by the Examiner does not describe or mention a
register. More particularly, the first paragraph on page VI-63 of
Rapid!O does not describe or mention control data contained in
a current data stream updating data stored in a register of a
source driver, wherein the current data stream includes both
payload (display) data and control data.
(App. Br. 6-7).
Instead, Appellants contend "Rapid!O merely discloses at page VI-63
initialization for each mode through a reset operation." (App. Br. 7).
Appellants further contend although "the Examiner has also relied
upon Chapter 6, page VI-89 (paragraphs 1 and 3 in particular) of Rapid!O,"
VI-89 of RapidIO "does not disclose or even remotely suggest updating
registers during the DISCOVERY state (interpreted by the Examiner as
the setup mode), as would be necessary to meet the features of claim 4."
According to Appellants, page VI-89 of RapidIO merely describes the
registers can be accessed "during maintenance operations." (App. Br. 7).
We consider all of Appellants' arguments and evidence presented, and
disagree with Appellants' contentions regarding the Examiner's rejections of
the claims. We incorporate herein and adopt as our own: (1) the findings
and reasons set forth by the Examiner in the action from which this appeal is
taken, and (2) the reasons set forth in the Examiner's Answer in response to
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Appellants' arguments. We highlight and address specific findings and
arguments below.
We agree with the Examiner's finding Yi's control board and source
driver teach or suggest limitations "timing controller" and "source driver,"
respectively, as recited in independent claim 4. (Final Act. 4--5, FF 1 ).
Further, we find no error with the Examiner's reliance on RapidIO for
disclosing or suggesting a setup mode and control data which updates data
stored in a register. (FF 2, 3). As the Examiner finds, the RapidIO industrial
standard has been available "at least since 2002" (Ans. 12) and the
implementation of this standard applies to the claimed "registers."
(Ans. 13). Specifically, the Examiner finds RapidIO's "fields" can "be
considered as some sort of control data." (Ans. 13)(emphasis added).
Furthermore, the Examiner finds "while receiving the data, register will be
updated, and it meets the claim limitation of 'operating in a setup mode
during which control data contained in the current data stream updates data
stored in a register' where RapidIO's 'DISCOVERY state' is mapped to
'setup mode'." (Ans. 14). Thus, we find no error with the Examiner's
reliance on RapidIO for the teaching and suggestion of "operating in a setup
mode during which control data contained in the current data stream updates
data stored in a register of the source driver." (claim 4).
Thus, even assuming, arguendo, the reviewing court were to find
RapidIO's updating is not performed in a "setup" mode (App. Br. 7), we
find it would have been well within the level of skill of one skilled in that
art, upon reading RapidIO's teaching of LP-Serial Registers and the
Discovery state (FF 2, 3), to update data stored in a register during a setup
mode.
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We note Appellants have presented no evidence that updating data
stored in registers during a setup mode of operation was "uniquely
challenging or difficult for one of ordinary skill in the art." Leapfrog Enters.,
Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir. 2007), nor have
Appellants presented evidence of secondary considerations of non-
obviousness, or that the Examiner's suggested combination yielded more
than expected results. Instead, we find the skilled artisan would have
concluded it obvious to update data stored in a register of the source driver
during a setup mode, since the skilled artisan is "a person of ordinary
creativity, not an automaton." KSR Int'! Co. v. Teleflex Inc., 550 U.S. 398,
420 (2007). The skilled artisan would "be able to fit the teachings of
multiple patents together like pieces of a puzzle." Id. at 421.
We note, Appellants merely attribute names for these modes as
"reset" mode, "ready" mode, "setup" mode, without providing any explicit
definitions of what each of these claimed modes precisely means. In fact,
we note, claim 4, when considered as a whole, merely transmits data, but
such data is not actually used to perform any positively recited function. 1
1 To the extent Appellants contend RapidIO's updating data is not
performed during a "setup" mode, wherein RapidIO's mode is different from
Appellants' mode (App. Br. 7), we note the such contention urging
patentability is predicated on the label attributed to the modes. However,
such labeling of the mode during which the updating step of method claim 4
is not being used to change or affect the manner in which updating to be
performed nor is there a particular output claimed. That is, such "setup"
mode is merely defined as the mode during which the updating occurs.
Thus, a question arises as to whether this labeling of this mode is merely
non-functional descriptive material. The PT AB has provided guidance in
decisions on the appropriate handling of claims that differ from the prior art
only based on "nonfunctional descriptive material." See Ex parte Nehls, 88
USPQ2d 1883, 1889 (BPAI 2008) (precedential) ("[T]he nature of the
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Thus, we find the preponderance of evidence supports the Examiner's
finding that the combination of RapidIO and Yi discloses the contested
limitations. (Ans. 12-14).
For these reasons, we agree with the Examiner's finding that the
combination of Yi and RapidIO would have at taught or at least suggested
the contested limitations of claim 4. Accordingly, on this record, we find no
error in the Examiner's rejection of independent claim 4 and independent
claim 14, which is commensurate in scope. We also sustain the rejection of
claims 6, 9-11, 13, 16, and 17 depending from claims 4 and 14, and falling
therewith.
Regarding dependent claim 7, Appellants contend "there appears to be
no disclosure that lane_sync of Rapid!O (interpreted by the Examiner as the
packet identity data of claim 7) is included in the packet format of LP-serial
packets shown in Fig. 2-1. The packet field definitions in Table 2-1 do not
define or include lane-sync." (App. Br. 10). However, the Examiner finds
RapidIO's lane_sync teaches or suggests the disputed limitation "entered
from the reset mode or the receive ready mode," as recited in claim 7. (Final
Act. 10, citing RapidIO, p. VI-62). We find Lane_Synchronization is taught
in the RapidIO reference (RapidIO, p.VI-52, 54-62) as a secondary state
information being manipulated does not lend patentability to an otherwise
unpatentable computer-implemented product or process."); Ex parte
Mathias, 84 USPQ2d 1276, 1279 (BPAI 2005) (informative).
("[N]onfunctional descriptive material cannot lend patentability to an
invention that would have otherwise been anticipated by the prior art."),
affd, 191 Fed. Appx. 959 (Fed. Cir. 2006) (Rule 36); Ex parte Curry, 84
USPQ2d 1272, 1274 (BPAI 2005) (informative) ("Nonfunctional descriptive
material cannot render nonobvious an invention that would have otherwise
been obvious."), affd, No. 06-1003 (Fed. Cir. June 12, 2006) (Rule 36).
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after initialization and the skilled artisan would have concluded it obvious to
utilize a reset mode. Thus, we find no error with the Examiner's finding that
the combination of Yi and RapidIO teaches or suggests claim 7.
Regarding dependent claim 8, Appellants argue Examiner's findings
on RapidIO's Discovery state is erroneous. (App. Br. 10). We find no error
with the Examiner's finding that the scope of claim term "setup mode"
covers RapidIO's Discovery State, for the same reasons explained above
regarding claim 4. (Final Act. 8).
Regarding dependent claim 12, Appellants contend "Since there is no
disclosure or suggestion of operating in the DISCOVERY state between
successive ones of a plurality of frame periods in Rapid!O, the rejection of
claim 12 appears to be based merely on impermissible hindsight
reconstruction." (App. Br. 11, 12). However, the Examiner finds certain
error patterns between link peers as a result of spurious channel condition
could cause the Discovery state to commence periodically. (Ans. 14--15).
Examiner further finds, RapidIO is a flexible tool where the payload size of
a packet is variable and choosing a size corresponding to the data of a frame
suitable for display application is within the capability of the protocol. (Id.).
We find a skilled artisan would have concluded it obvious to utilize a
plurality of frame periods within the context of claims 4 and 12. Thus, we
agree with the Examiner's findings and find no error with the Examiner's
conclusion of obviousness regarding claim 12.
Regarding dependent claim 15, Appellants contend
Rapid!O fails to show transitions of a data signal, transitions of
a data signal from low to high, a data input/output control signal,
transitions of a data signal from low to high during a time period
in which a data input/output control signal is high, and/or
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detection of configuration data during a time period in which the
data signal is low while the data input/output control signal is
high. Since Fig. 3-7 of Rapid/O does not specifically show these
signals and data with corresponding transitions and high/low
states, Rapid/O clearly fails to disclose or even remotely suggest
a data stream transfer start indication having the extent as
specifically recited in claim 15.
(App. Br. 14).
However, the Examiner's finds RapidIO's receiver and transmitter
teaches or at least suggests the claimed data transfer. (Final Act. 12, citing
RapidIO Fig. 3-7, where the configuration data such as stypeO and
parameterO and 1 all has to be received first before payload transmission
commences). Furthermore, claim 15 recites merely data transfers which we
note is non-functional descriptive material, and as such we do not accord it
patentable weight. We find a skilled artisan would have concluded it
obvious to determine a data stream start indication in response to a data
input/output control signal and other data within the context of claim 15.
Moreover, Appellants have provided no evidence that combining such
teachings of Yi and RapidIO was uniquely challenging, difficult for one of
ordinary skill in the art, or yielded more than expected results (Leapfrog
Enters., Inc., 485 F.3d at 1162. Thus, we agree with the Examiner's
findings and find no error with the Examiner's conclusion of obviousness
regarding claim 15.
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Y. CONCLUSION AND DECISION
We affirm the Examiner's decision rejecting claims 4, and 6-17 under
35 U.S.C. § 103(a).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(l )(iv).
AFFIRMED
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