Ex Parte Aziz et al

Patent Trial and Appeal Board

Mar 12, 2014

11399647 (P.T.A.B. Mar. 12, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/399,647 04/06/2006 Pervez M. Aziz Aziz 23-16 1127
47386 7590 03/13/2014
RYAN, MASON & LEWIS, LLP
1175 POST ROAD EAST
2ND FLOOR
WESTPORT, CT 06880
EXAMINER
MCKIE, GINA M
ART UNIT PAPER NUMBER
2631
MAIL DATE DELIVERY MODE
03/13/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte PERVEZ M. AZIZ and GREGORY W. SHEETS
____________________

Appeal 2011-010139
Application 11/399,647
Technology Center 2600
____________

Before ST. JOHN COURTENAY III, THU A. DANG, and
LARRY J. HUME, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

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Application 11/399,647

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I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a final rejection of
claims 1-20. However, Appellants state that “[c]laims 1-3, 8-10 and 15-17
are being appealed” (App. Br. 2). In particular, Appellants do not appeal
claims 4-7, 11-14, and 18-20, but note that they are pending and rejected
(id.). The Board has no jurisdiction as to non-appealed claims, and we
consider claims 4-7, 11-14, and 18-20 not before us for review. The
Examiner has the authority to cancel the non-appealed claims. See Ex parte
Ghuman, 88 USPQ2d 1478, 1480 (BPAI 2008) (precedential).
We have jurisdiction as to claims 1-3, 8-10, and 15-17 under
35 U.S.C. § 6(b). We affirm.

A. INVENTION
According to Appellants, the invention relates, generally, to
recovering a clock from a received data stream, and more particularly, to
obtaining an initial phase estimate using a zero phase start algorithm (Spec.
1, ll. 5-7).

B. ILLUSTRATIVE CLAIM
Claim 1 is exemplary:
1. A method for obtaining a phase offset estimate from a
data stream, comprising:
obtaining a binary sampled version of said data stream
based on a clock, wherein
said binary sampled version consists of single-bit two-
level binary sliced data;
accumulating a first dot product of said binary sampled
version of said data stream and an ideal sequence;
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accumulating a second dot product of said binary
sampled version of said data
stream and a delayed ideal sequence; and
adjusting a phase offset of said clock until said
accumulated first and second dot
product satisfy one or more predefined conditions.

C. REJECTION
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Bishop US 6,307,696 B1 Oct. 23, 2001

All of the claims on appeal, claims 1-3, 8-10, and 15-17, stand
rejected under 35 U.S.C. § 103(a) as unpatentable over Bishop.

II. ISSUE
The dispositive issue before us is whether the Examiner has erred in
finding Boyer teaches or would have suggested “obtaining a binary sampled
version” that “consists of single-bit two-level binary sliced data” as recited
in claim 1 (emphasis added)?

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Bishop
1. Bishop discloses an analog-to-digital (A/D) converter that
samples analog input signals responsive to a sampling clock signal input,
wherein every other sample value is stored in a memory so as to provide
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even A/D samples on one path and odd A/D samples on another path (col. 6,
ll. 57-64; Fig. 6).
2. The conversion process includes quantization according to the
number of bits resolved by the A/D (col. 3, l. 66 to col. 4, l. 1).

IV. ANALYSIS
Appellants contend that “there is no disclosure or suggestion in
Bishop of a low resolution (single-bit) A/D Converter” (App. Br. 4).
According to Appellants, “[t]he ADC output ADC0(n) and ADC1(n) . . . can
be described in terms of a sine wave because it is a multi-bit output of the
ADC” (id.). Thus, Appellants assert that “Bishop expressly teaches away
from such a modification by teaching the use of the multi-bit output of the
ADC” (App. Br. 5).
However, the Examiner finds that, in Bishop, “‘[t]he conversion
process includes quantization according to the number of bits resolved by
the A/D’” and concludes that “one of ordinary skill in the art would know
the ‘number of bits’ disclosed by Bishop includes the number 1, i.e.[,]
single-bit resolution” (Ans. 17). In particular, the Examiner concludes that it
would have been obvious “to use an A/D converter that resolves a single bit,
thus allowing simpler implementation” since the ordinary artisan “would
know that it is simpler (and faster) for an A/D to resolve 1 bit than to resolve
multiple bits” (id.). That is, the Examiner concludes “the binary sample
version consisting of ‘single-bit binary sliced data’ was within the level of
ordinary skill at the time the claimed invention was made” (Ans. 20).
Although the Examiner admits that “Bishop does not specify the number of
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bits,” the Examiner finds that “Bishop does not exclude single-bit
resolution” (Ans. 21).
We agree with the Examiner’s underlying factual findings and
ultimate legal conclusion of obviousness.
We give the claim its broadest reasonable interpretation consistent
with the Specification. See In re Morris, 127 F.3d 1048, 1054 (Fed. Cir.
1997). Claim 1 does not provide any definition for “single-bit two-level
binary sliced data” and we note that the Specification is silent as to any such
definition. In fact, we could not find any support in the originally filed
Specification for such “single-bit” data.1 Although Appellants argue that
Bishop does not disclose a single-bit output of the ADC because “[t]he ADC
output ADC0(n) and ADC1(n) . . . can be described in terms of a sine wave”
(App. Br. 4), nothing in the claim or the Specification precludes a sine-wave
output.
Nevertheless, the test for obviousness is not what Bishop shows but
what Bishop would have suggested to one of ordinary skill in the art. See In
re Merck & Co., Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986).
Bishop discloses an A/D converter that provides even A/D samples
on one path and odd A/D samples on another path (FF1), wherein the
number of bits resolved by the A/D is variable (FF 2). We find no error with
the Examiner’s conclusion that “one of ordinary skill in the art would know
the ‘number of bits’ disclosed by Bishop includes the number 1, i.e.[,]

1 In the event of further prosecution, we leave it to the Examiner to consider
whether claim 1, and the other claims, should also be rejected under
35 U.S.C. § 112, 1st paragraph, as failing to comply with the written
description requirement.
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single-bit resolution” (Ans. 17) and that it would have been obvious “to use
an A/D converter that resolves a single bit, thus allowing simpler
implementation” since the ordinary artisan “would know that it is simpler
(and faster) for an A/D to resolve 1 bit than to resolve multiple bits” (id.).
The Supreme Court has determined that the conclusion of obviousness
can be based on the background knowledge possessed by a person having
ordinary skill in the art. KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416
(2007). The skilled artisan is “a person of ordinary creativity, not an
automaton.” Id. at 420-21. We are not persuaded, and Appellants have
presented no persuasive evidence that obtaining such “single-bit” data was
“uniquely challenging or difficult for one of ordinary skill in the art.”
Leapfrog Enters., Inc. v. Fisher-Price, Inc., 485 F.3d 1157, 1162 (Fed. Cir.
2007) (citing KSR, 550 U.S. at 418). We agree with the Examiner’s
conclusion that “the binary sample version consisting of ‘single-bit binary
sliced data’ was within the level of ordinary skill at the time the claimed
invention was made” (Ans. 20).
Though Appellants also contend that the Bishop “teaches away” from
“single-bit” data (App. Br. 5), our reviewing court has held that “‘[a]
reference may be said to teach away when a person of ordinary skill, upon
[examining] the reference, would be discouraged from following the path set
out in the reference, or would be led in a direction divergent from the path
that was taken by the applicant.’” Para-Ordnance Mfg., Inc. v. SGS
Importers Int’l, Inc., 73 F.3d 1085, 1090 (Fed. Cir. 1995) (quoting In re
Gurley, 27 F.3d 551, 553 (Fed. Cir. 1994)). Appellants show no teaching in
Bishop that would discourage the obtaining of single-bit data. We agree
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with the Examiner’s finding that “Bishop does not exclude single-bit
resolution” (Ans. 21).
Accordingly, we find Appellants have not shown that the Examiner
erred in rejecting representative claim 1, and independent claims 8 and 15,
falling therewith (App. Br. 5), over Bishop.
As for dependent claims 2, 9, and 16, Appellants merely argue that, in
Bishop, “[t]here is no disclosure or suggestion of a transition of at least one
of said accumulated first and second dot product” (App. Br. 5-6). Similarly,
as for dependent claims 3, 10, and 17, Appellants merely contend that, in
Bishop, “[t]here is no disclosure or suggestion of a transition to a final
value” (id.).
However, we find no error with the Examiner’s interpretation that
“[t]he word transition simply means a ‘process of change’” and thus find no
error with the Examiner’s finding that Bishop at the least suggests “one of
the accumulated first and second dot products undergoes a change” (Ans.
23). In particular, we find no error with the Examiner’s finding that “the
phase adjustment stops when at least one of said accumulated first and
second dot products is divided by N, this constitutes a change or ‘transition’”
(id.) to a final value (Ans. 24).
Therefore, we find the Examiner also did not err in rejecting claims 2,
3, 9, 10, 16, and 17.

V. CONCLUSION AND DECISION
We affirm the Examiner’s rejection of claims 1-3, 8-10, and 15-17
under 35 U.S.C. § 103(a).
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No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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