Ex Parte Aton et al

Patent Trials and Appeals Board

May 18, 2018

13454801 - (D) (P.T.A.B. May. 18, 2018)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
13/454,801 04/24/2012
23494 7590 05/22/2018
TEXAS INSTRUMENTS IN CORPORA TED
PO BOX 655474, MIS 3999
DALLAS, TX 75265
FIRST NAMED INVENTOR
Thomas J. Aton
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-69518 9199
EXAMINER
MUSE, ISMAIL A
ART UNIT PAPER NUMBER
2819
NOTIFICATION DATE DELIVERY MODE
05/22/2018 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte THOMAS J. ATON,
ROGER MARK TERRY, and ROBERT L. PITTS
Appeal2017-006150
Application 13/454,801
Technology Center 2800
Before GEORGE C. BEST, JEFFREY R. SNAY, and
MERRELL C. CASHION, JR., Administrative Patent Judges.
BEST, Administrative Patent Judge.
DECISION ON APPEAL
The Examiner finally rejected claims 1, 2, and 17 of Application
13/454,801 under 35 U.S.C. § 102(b) as anticipated and also rejected claims
3 and 10 under 35 U.S.C. § 103(a) as obvious. Final Act. (December 31,
2015). Appellants 1 seek reversal of these rejections pursuant to 35
U.S.C. § 134(a). We have jurisdiction under 35 U.S.C. § 6.
For the reasons set forth below, we affirm.
1 Texas Instruments, Inc. is identified as the real party in interest. Appeal
Br. 2.
Appeal2017-006150
Application 13/454,801
BACKGROUND
The '801 Application describes integrated circuit structures and
methods for making them. Spec. ,r 5. Processes for making integrated
circuits can be identified by the width of the conducting lines that
interconnect the semiconductor devices that comprise the integrated circuit.
Id. ,r 6. According to the Specification, "[p ]rocess generations having
different size[d] line widths from each other are called process nodes." Id.
Integrated circuits are typically designed using a type of computer
software, called a layout tool, place-and-route tool, or, simply, a tool.
Id. ,r 8. A layout tool
Id.
situates and defines the geometric arrangement of the
transistors, conducting lines, contacts, vias and their
interconnections with the semiconductor devices. Tools have
constraints, called design rules, that are consistent with the
process capabilities and also provide some simplification or
order for mathematical algorithms or procedures adopted in a
tool to lay out a given complicated integrated circuit and avoid
what would otherwise [be] a stupefying and unnecessarily
complicated array of geometric possibilities in three dimensions
of height, width and depth for the conducting lines that the tool
is to define.
"Newer technologies at advanced semiconductor wafer fabrication
process nodes have strong 'context effects' where the performance of a
transistor depends significantly on what other base layer objects occur near
the transistors." Id. ,r 9. The Specification further states:
[001 OJ Context effects have previously generally been
"margined for" by accepting an overall degradation in the
performance of all of the standard cells [ circuit layout objects
used in circuit design software]. Or they have simply been
ignored, detrimentally.
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Appeal2017-006150
Application 13/454,801
[0011] Accordingly, significant departures and
alternatives in [the] structures, circuits, processes of
manufacture, and [the] processes of design, for addressing the
above considerations and problems would be most desirable.
Id. ,I,I 10-11.
One embodiment of Appellants' invention solves the problems
described above in the following way:
Cells are divided into classes. Those cells that can be placed
near other cells without disrupting their neighbor's behavior are
called "good neighbors" and can be utilized near other cells in
the conventional manner. Cells that disrupt their neighbor's
timing beyond certain criteria are declared "bad neighbors" and
are segregated or allocated into separate place and route regions
and "buffered" from the other standard cells in the sense of
context effects reduction. This buffering is accomplished by a
third class of cells that cause little, if any, timing disruption and
also themselves are insensitive to timing disruption (some types
of capacitor cells for example).
Id. ,I 26.
Claim 1 is representative of the '801 Application's claims and is
reproduced below from the Claims Appendix of the Appeal Brief.
1. An integrated circuit comprising:
a substrate having a semiconducting surface; and
a structure formed in and on the semiconducting surface, the
structure including a first block of standard cells, and at least a
second block,
the first and second blocks arranged in a horizontal row,
and at least partially aligned in height, such that at least a
portion of a first vertical block boundary of the first
block is adjacent to and aligned with at least a portion of
a second vertical block boundary of the second block,
thereby defining a region of alignment between the first
and second blocks,
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Appeal2017-006150
Application 13/454,801
the first block including a first base level extending
beyond the first vertical block boundary to form a
first vertical base-level boundary at least partially
within the region of alignment,
the second block including a second base level
extending beyond the second vertical block
boundary to form a second vertical base-level
boundary at least partially within the region of
alignment;
the first and second blocks placed on the semiconducting
surface such that the blocks are separated by a protective
separation strip between the blocks;
the first block including a first DWDI dimension
between its first vertical block boundary, and the
second vertical base-level boundary of the second
base level,
the second block including a second DWDI
dimension between its second vertical block
boundary, and the first vertical base-level
boundary of the first base level,
the DWDI dimension defined such that a
minimum separation exists between the first and
second vertical base-level boundaries
corresponding to the protective separation strip.
Appeal Br. 12-13 (Claims App.).
REJECTIONS
On appeal, the Examiner maintains the following rejections:
1. Claims 1, 2, and 17 are rejected under 35 U.S.C. § I02(b) as
anticipated by Kim. 2 Final Act. 3.
2 US 2009/0175081 Al, published July 9, 2009.
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Appeal2017-006150
Application 13/454,801
2. Claim 3 is rejected under 35 U.S.C. § I03(a) as unpatentable
over Kim. Final Act. 5.
3. Claim 10 is rejected under 35 U.S.C. § I03(a) as unpatentable
over the combination of Kim and Pitts. 3 Final Act. 6.
DISCUSSION
Appellants only present substantive arguments for reversal of the
rejection of claim 1, which is the sole independent claim on appeal. Appeal
Br. 5-10. Appellants do not present any separate arguments for dependent
claims 2, 3, 10, and 17. Id. at 2. We, therefore, limit our discussion to claim
1, which we select as representative of the claims on appeal. 37 C.F.R.
§ 4I.37(c)(l)(iv) (2015). Claims 2, 3, 10, and 17 will stand or fall with
claim 1.
At bottom, this appeal is an illustration of an old maxim: "'That which
infringes, if later, would anticipate, if earlier."' Peters v. Active Mfg. Co.,
129 U.S. 530, 537 (1889) (quoting Peters v. Active Mfg. Co., 21 F. 319, 320
(CCSD Ohio 1884)). As explained in the Examiner's Answer, the Examiner
found that claim 1 reads on Kim's structure. See Answer 4---6. 4
Appellants "contest[] the annotation First DWD 1, as merely applying
Appellant's claimed 'DWDI dimension' to Kim's Fig[ure] 8B, ignoring
Kim's teaching of the use of a 'minimum distance D ... for adjacent n-type
3 US 2009/0033368 Al, published February 5, 2009.
4 We agree with Appellants that "[ the Examiner] intended to draw the
Second DWDI annotation the same as the 'First DWDI' annotation as
extending from what the Examiner contends is a 'block boundary' as in
Annotated Fig[ure] 8B-3 to the adjacent 'base-level boundary' as in
Annotated Fig[ure] 8B-5." Reply Br. 7.
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Appeal2017-006150
Application 13/454,801
isolation wells' for structural separation, and failing to teach defining the
structural separation 'DWDl dimension' relative to a 'vertical block
boundary."' Reply Br. 7.
For the following reasons, we are not persuaded by Appellants'
argument.
Claim 1 is an apparatus claim. As such, it must be distinguished from
the prior art in terms of structure. See In re Schreiber, 128 F.3d 1473, 1478
(Fed. Cir. 1997) and cases cited therein; see also In re Danly, 263 F.2d 844,
848 (CCPA 1959) ("Claims drawn to an apparatus must distinguish from the
prior art in terms of structure rather than function"); In re Gardiner, 171
F .2d 313, 315-16 ( CCP A 1948) ("It is trite to state that the patentability of
apparatus claims must be shown in the structure claimed and not merely
upon a use, function, or result thereof.").
Appellants attempt to demonstrate a structural difference between
Kim's device and the subject matter of claim. See Appeal Br. 9-10; Reply
Br. 7. In particular, Appellants argue:
In the Examiner's Annotated Fig[ure] 8B-6, and the related
arguments in the Examiner's Answer, the Examiner merely
annotates Kim Fig[ ure] 8B according to the claimed "DWD 1
dimension", without addressing the fact that Kim fails to
provide any disclosure regarding structural separation based on
the claimed "DWD 1 dimension" defined relative to the claimed
"vertical block boundary", and without addressing the fact that
Kim expressly teaches a structural separation based on a
"minimum distance D ... for adjacent n-type isolation wells",
which is defined relative to, arguendo, the "base-level
boundary" of then-wells 222/228, and not the claimed "vertical
block boundary".
Reply Br. 7.
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Application 13/454,801
In this case, however, Appellants' argument is not persuasive.
Although Kim uses different language to describe the structure of its
apparatus, we discern no error in the Examiner's finding that claim 1 reads
upon Kim's structure.
We, therefore, affirm the rejection of claim 1. Thus, we also affirm
the rejections of claims 2, 3, 10, and 17.
CONCLUSION
For the reasons set forth above, we affirm the rejections of claims 1-3,
10, and 17 of the '801 Application.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
AFFIRMED
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