Ex Parte Arndt et al

Board of Patent Appeals and Interferences

Jan 18, 2012

10927949 (B.P.A.I. Jan. 18, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
10/927,949 08/27/2004 Christian Arndt 1890-0122 2341
7590 01/18/2012
Maginot, Moore & Beck LLP
Chase Tower
Suite 3250
111 Monument Circle
Indianapolis, IN 46204-5109
EXAMINER
WELLS, KENNETH B
ART UNIT PAPER NUMBER
2816
MAIL DATE DELIVERY MODE
01/18/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte CHRISTIAN ARNDT, VELI KARTAL, and RAINALD SANDER
____________________

Appeal 2010-001195
Application 10/927,949
Technology Center 2800
____________________

Before JOSEPH L. DIXON, THU A. DANG,
and JAMES R. HUGHES, Administrative Patent Judges.

DANG, Administrative Patent Judge.

DECISION ON APPEAL

I. STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134(a) from a Final Rejection of
claims 17-26 and 32-43 (App. Br. 2). Appellants are not appealing the
Examiner’s rejections of claims 28-31, but note that these claims are
pending (App. Br. 2). Appellants’ withdrawal of claims 28-31 from the
appeal acts as a waiver with respect to these claims. Accordingly, we
summarily sustain the Examiner’s rejection of claims 28-31. See 37 C.F.R.
Appeal 2010-001195
Application 10/927,949

2
§ 41.37(c)(1)(vii); cf. Ex parte Ghuman, 88 USPQ2d 1478, 1480 (BPAI
2008) (precedential). Claims 1-16 and 27 have been canceled (App. Br. 2).
We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.

A. INVENTION
Appellants’ invention is directed to a method for driving a load
transistor and circuit arrangement including a voltage limiting circuit;
wherein, current and temperature instabilities of the load transistor are
prevented by a deactivation circuit that deactivates the voltage limiting
circuit in a manner dependent on the load current through the load transistor
(Abstract; Spec. 12:10-13:20).

B. ILLUSTRATIVE CLAIM
Claim 17 is exemplary:
17. A circuit arrangement comprising:

a load transistor having a control connection and a first and second
load connection;
a drive connection coupled at an input to a source of a drive signal and
at an output to the control connection of the load transistor, the drive
connection being configured to have the drive signal present at the output;

a voltage limiting circuit connected between one of the load
connections and the control connection of the load transistor, the voltage
limiting circuit configured to limit a load path voltage of the load transistor
to a predetermined clamping voltage; and

a deactivation circuit connected to the voltage limiting circuit, the
deactivation circuit being configured to deactivate the voltage limiting
circuit in response to a deactivation signal responsive to a load current
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Application 10/927,949

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measurement value of the load transistor, wherein the deactivation circuit is
designed to deactivate the voltage limiting circuit if the load current of the
load transistor falls below a predetermined value; and

wherein the load transistor undergoes transition to a avalanche mode
when the voltage limiting circuit is deactivated and an overvoltage of the
load transistor reaches an avalanche voltage.

C. REJECTIONS
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Yokosawa US 6,294,941 B1 Sept. 25, 2001
Claims 17, 19-24, and 28-42 stands rejected under 35 U.S.C. § 102(b)
as being anticipated by Yokosawa.
Claims 18, 25, 26, and 43 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over Yokosawa.

II. ISSUES
The dispositive issues before us are whether the Examiner has erred in
determining that Yokosawa discloses:
1. “a deactivation circuit connected to the voltage limiting circuit, the
deactivation circuit being configured to deactivate the voltage limiting
circuit in response to a deactivation signal responsive to a load current
measurement value of the load transistor, wherein the deactivation circuit is
designed to deactivate the voltage limiting circuit if the load current of the
load transistor falls below a predetermined value” (claim 17, emphasis
added); and
Appeal 2010-001195
Application 10/927,949

4
2. “a current measuring arrangement configured to determine a load
current through the load transistor and to provide a current measurement
signal and a deactivation signal generating circuit configured to compare
the current measurement signal with a reference value to generate the
deactivation signal” (claim 21, emphasis added).

III. FINDINGS OF FACT
The following Findings of Fact (FF) are shown by a preponderance of
the evidence.
Yokosawa
1. Yokosawa is directed to a stabilized power supply circuit
constituted by a voltage follower circuit which receives a power supply
voltage VBATT as a power supply input and uses a voltage VREF supplied
from an external source as a reference voltage to a differential amplifier
1(Fig. 1 and 3; col. 4, ll. 45-53 and col. 7, ll. 63-67); wherein, each
embodiment includes a clamp circuit (28, 29) that limits the gate-source
voltage of the source follower transistor 8 so as to prevent the source
follower transistor 8 from exceeding a predetermined voltage level (Fig. 1
and 3; col. 5, ll. 20-26; col. 6, ll. 24-40 and col. 7, l. 63-col.8, l. 15).
2. During normal operation, the clamping circuit 29 is off and the
stabilized power supply circuit is controlled as a voltage follower; wherein,
the usual feedback function is performed (Fig. 3; col. 7, ll. 20-25).

Appeal 2010-001195
Application 10/927,949

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3. Within the clamping circuit 29, nMOS transistor 2 and diodes
(13, 14) do not become conductive at the same time as pMOS transistor 7
and diodes (15, 16); wherein either one transistor and the corresponding
diodes of one channel type become conductive or the transistors of both
channel types are non-conductive (Fig. 3; col. 6, ll. 59-64).
4. When a voltage is forcibly applied to the output terminal 53,
one of transistors (2, 7) of the clamping circuit turns on corresponding the
voltage Va at node A (Fig. 2 and 3; col. 7, ll. 25-41). For VOUT=0V to
approximately 5 V, the pMOS transistor 7 is on and the nMOS transistor 2 is
off (Fig. 2). From VOUT=5V to16V, the nMOS transistor 2 is on and pMOS
transistor 7 is off (id.).

IV. ANALYSIS
Claims 17, 19-20, and 32-42
Appellants provide similar arguments with respect to independent
claims 17 and 32 (App. Br. 6-13 and 15). Appellants do not provide
arguments with respect to dependent claims 19, 20, and 33-42. Accordingly,
we select claim 17 as being representative of the claims. See 37 C.F.R.
§ 41.37(c)(1)(vii).
Appellants contend that “while Yokosawa does disclose a circuit that
can disable or enable a voltage limiting circuit, Yokosawa does not teach
that such activation or deactivation is dependent upon the load current
through a load transistor, and certainly does not teach anything ‘designed to
deactivate the voltage limiting circuit if the load current of the load transistor
falls below a predetermined value’” (App. Br. 7). Specifically, Appellants
argue that “the ‘deactivation circuit’ [FET 2] of Yokosawa is dependent on
Appeal 2010-001195
Application 10/927,949

6
the source voltage Vout of the load transistor 8, which is not a measurement
of the ‘load current’ through the load transistor” (App. Br. 8). Appellants
contend that “a current measurement circuit or device typically requires a
current sensor or a differential voltage measurement;” wherein, Yokosawa
provides “[a] single node voltage [which] is typically insufficient to provide
a load current measurement” (id.).
Appellants assert that in the special case where “the output node 53 of
Yokosawa is not connected to any device,” “FET 2 is never turned” and
therefore “FET 2 is never deactivated based on when the ‘load current’ as
represented by Vout falls below a predetermined threshold” (App. Br. 9).
Appellants further contend that “the Examiner has described a ‘state
transition’ of Yokosawa that is physically impossible” since “the transistor 8
can never be on while the FET 2 is conducting” (App. Br. 12).
However, the Examiner finds that “the deactivation circuit is FET 2
and this transistor will turn off when the current flowing through transistor 8
falls below a predetermined value” (Ans. 7). The Examiner notes “that the
current flowing through transistor 8 and resistors 9, 10 can be read on the
claimed ‘load current’ because it flows through the load transistor 8” (id.).
To determine whether the Yokosawa teaches “a deactivation circuit
connected to the voltage limiting circuit, the deactivation circuit being
configured to deactivate the voltage limiting circuit in response to a
deactivation signal responsive to a load current measurement value of the
load transistor, wherein the deactivation circuit is designed to deactivate the
voltage limiting circuit if the load current of the load transistor falls below a

Appeal 2010-001195
Application 10/927,949

7
predetermined value” as recited in claim 17, we give the claim its broadest
reasonable interpretation consistent with the Specification. See In re Morris,
127 F.3d 1048, 1054 (Fed. Cir. 1997). However, we will not read
limitations from the Specification into the claims. In re Van Geuns, 988
F.2d 1181, 1184 (Fed. Cir. 1993).
Claim 17 does not place any limitation on what “a deactivation
signal” and “a load current measurement value of the load transistor” mean,
include, or represent. Thus, we give “deactivation signal” its broadest
reasonable interpretation as a signal that deactivates the voltage limiting
circuit, as consistent with the Specification and as specifically defined in
claim 17. We also give “load current measurement value” its broadest
reasonable interpretation as the value of current through the load transistor,
as consistent with the Specification and as specifically defined in claim 17.
Yokosawa discloses a stabilized power supply circuit constituted by a
voltage follower circuit; wherein, the stabilized power supply circuit
includes a clamp circuit that limits the gate-source voltage of the source
follower transistor so as to prevent the source follower transistor from
exceeding a predetermined voltage level (FF 1). During normal operation,
the clamping circuit is off and the stabilized power supply circuit is
controlled as a voltage follower; wherein, the usual feedback function is
performed (FF 2). The clamp circuit comprises a first and second portion
having respective transistors and diode; wherein, the first and second
portions do not become conductive at the same time (FF 3).

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01195
/927,949
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Appeal 2010-001195
Application 10/927,949

10
As shown in Figs. 2 and 3 above, when a voltage is forcibly applied to
the output terminal 53, one of transistors (2, 7) of the clamping circuit turns
on. In particular, when the voltage at VOUT is within the range of 0V to
approximately 5 V, pMOS transistor 7 is on (corresponding to potential
differential 12) and nMOS transistor 2 is off. Alternatively, when VOUT is
within the range of approximately 5V to 16V, nMOS transistor 2 is on
(corresponding to potential differential 11) and pMOS transistor 7 is off.
Therefore, when the voltage falls below a predetermined value of
approximately 5V (or its corresponding load current), transistor 2 turns off
and deactivates the first portion of clamping circuit 29 (diodes 13 and 14).
We find that this transistor 2 serves as a deactivation circuit for the voltage
limiting circuit (diodes 13 and 14) when the load current falls below a
predetermined value. That is, we find that “wherein the deactivation circuit
is designed to deactivate the voltage limiting circuit if the load current of the
load transistor falls below a predetermined value” reads upon Yokosawa’s
transistor 2.
In view of our claim construction above, we find that Yokosawa
discloses “a deactivation circuit connected to the voltage limiting circuit, the
deactivation circuit being configured to deactivate the voltage limiting
circuit in response to a deactivation signal responsive to a load current
measurement value of the load transistor, wherein the deactivation circuit is
designed to deactivate the voltage limiting circuit if the load current of the
load transistor falls below a predetermined value,” as specifically required
by claim 17.

Appeal 2010-001195
Application 10/927,949

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Accordingly, we find that Appellants have not shown that the
Examiner erred in rejecting claim 17 under 35 U.S.C. § 102(b) over
Yokosawa; and independent claim 32 and claims 19, 20, and 33-42
depending from claims 17 and 32 which have been grouped therewith.
Claims 21-24
Appellants provide an argument with respect to claim 21 (App. Br.
13-14). Appellants do not provide arguments with respect to dependent
claims 22-24. Accordingly, we select claim 21 as being representative of the
claims.
Appellants contend that “Yokosawa does not disclose such a current
measuring arrangement, nor a deactivation circuit configured to compare the
current measurement signal with a reference value” (App. Br. 14).
However, the Examiner finds that “Yokosawa does in fact clearly
disclose a current measurement circuit (it is the voltage divider formed by
the combination of resistors 9 and 10)” (Ans. 17). The Examiner finds
further that “comparator 1 which compares the voltage between resistors 9
and 10 to VREF and outputs a signal which causes generation of the
deactivation signal at the gate of FET2” discloses “the recited deactivation
signal generating circuit of claim 21” (Ans. 5).
Claim 21 does not place any limitation on what “current measuring
arrangement” and “deactivation signal generating circuit” mean, include, or
represent. Thus, we give “a current measuring arrangement configured to
determine the load current through the load transistor and to provide a
current measurement signal” its broadest reasonable interpretation as a
circuit that measures the load current, as consistent with the Specification
and as specifically defined in claim 21. Additionally, we give “a
Appeal 2010-001195
Application 10/927,949

12
deactivation signal generating circuit configured to compare the current
measurement signal with a reference value to generate the deactivation
signal” its broadest reasonable interpretation as a circuit that generates a
signal for the deactivation circuit, as consistent with the Specification and as
specifically defined in claim 21.
As shown in Figure 3 supra, Yokosawa discloses a voltage divider
network formed by the combination of resistors 9 and 10 that provides the
inverting input for differential amplifier 1 which compares the inverting
input with the reference voltage VREF (FF 1). We adopt the Examiner’s
position that the voltage divider network is a current measurement circuit;
wherein, the voltage is measured across resistor 10 and, thereby, the
respective current or load current from the load transistor 8 is measured
since the value of the resistance is known (Ans. 17). That is, we find that “a
current measuring arrangement configured to determine the load current
through the load transistor and to provide a current measurement signal”
reads on Yokosawa’s circuit arrangement including differential amplifier 1
and the voltage divider network (formed by resistors 9 and 10).
As shown in Figure 3 and noted supra, Yokosawa discloses nMOS
transistor 2 that activates and deactivates the voltage limiting circuit portion
(diodes 13 and 14) of clamping circuit 29 (FF 3). The gate of transistor 2 is
coupled to the source of load transistor 8; such that when the source voltage
reaches a predetermined voltage level, transistor 2 turns on and off (FF 3).
We find that the circuit arrangement including transistor 8 and differential
amplifier 1 represents the deactivation signal generating circuit which
compares the current measurement signal (voltage across resistor 10) with a
reference value (VREF) to generate the deactivation signal (voltage VOUT).
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Application 10/927,949

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That is, we find that “a deactivation signal generating circuit
configured to compare the current measurement signal with a reference
value to generate the deactivation signal” reads on Yokosawa’s circuit
arrangement including differential amplifier 1 and load transistor 8.
In view of our claim construction above, we find that Yokosawa
provides “a current measuring arrangement configured to determine the load
current through the load transistor and to provide a current measurement
signal and a deactivation signal generating circuit configured to compare the
current measurement signal with a reference value to generate the
deactivation signal,” as specifically required by claim 21.
Accordingly, we find that Appellants have not shown that the
Examiner erred in rejecting claim 21 under 35 U.S.C. § 102(b) over
Yokosawa; and claims 22-24 depending from claim 17 which have been
grouped therewith.
Claims 18, 25, 26, and 43
Appellants argue that claims 18, 25, 26, and 43 are patentable over the
cited prior art for the same reasons asserted with respect to claim 17 (App.
Br. 15).
As noted supra, however, we find that Yokosawa discloses all the
features of claim 17. We therefore sustain the Examiner’s rejection of
claims 18, 25, 26, and 43 under 35 U.S.C. § 103 for the same reasons
expressed with respect to parent claim 17, supra.

Appeal 2010-001195
Application 10/927,949

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V. CONCLUSION AND DECISION
The Examiner’s rejection of claims 17, 19-24, and 28-42 under 35
U.S.C. § 102(b) and claims 18, 25, 26, and 43 under 35 U.S.C. § 103(a) is
affirmed.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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