Ex Parte Aripin

Patent Trial and Appeal Board

Feb 23, 2017

13408058 (P.T.A.B. Feb. 23, 2017)

United States Patent and Trademark Office
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O.Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/408,058 02/29/2012 Azhar Aripin ONS01460 3877
132239 7590 02/27/2017
SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC (KJ)
5005 E. MCDOWELL ROAD, Maildrop A700
Phoenix, AZ 85008
EXAMINER
NGO, HUNG V
ART UNIT PAPER NUMBER
2847
NOTIFICATION DATE DELIVERY MODE
02/27/2017 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
patents @ onsemi. com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte AZHAR ARIPIN
Appeal 2015-005385
Application 13/408,058
Technology Center 2800
Before ADRIENE LEPIANE HANLON, ROMULO H. DELMENDO, and
BRIAN D. RANGE, Administrative Patent Judges.
HANLON, Administrative Patent Judge.
DECISION ON APPEAL
A. STATEMENT OF THE CASE
The Appellant filed an appeal under 35 U.S.C. § 134 from an Examiner’s
decision finally rejecting claims 1—14 and 21—26 under 35 U.S.C. § 103(a) as
unpatentable over Abe1 in view of Shirasaka et al.2 We have jurisdiction under
35 U.S.C. § 6(b).
We AFFIRM-IN-PART.
1 US 2001/0013639 Al, published August 16, 2001 (“Abe”).
2 US 7,554,182 B2, issued June 30, 2009 (“Shirasaka”).
Appeal 2015-005385
Application 13/408,058
Representative claim 1 is reproduced below.3 The limitations at issue are
italicized.
1. An electronic device structure comprising:
a leadframe having a pair of adjacent inner rows of I/O pads
and at least one outer row of I/O pads, wherein the pair of adjacent
inner rows of I/O pads are physically isolated from each other and
each have an interior facing sidewall surface opposing each other,
an electronic device having first and second opposing major
surfaces, wherein the second major surface is attached to at least two
opposing I/O pads in the pair of adjacent inner rows of I/O pads;
connective structures coupling the first major surface to at least
a portion of I/O pads in the pair of adjacent inner rows of I/O pads and
the at least one outer row of I/O pads; and
an encapsulating layer covering at least portions of the
leadframe, the electronic device and the connective structures,
wherein the encapsulating layer is absent from a portion of the
interior facing sidewall surface of each of the adjacent inner rows of
I/O pads.
B. DISCUSSION
Abe Figure 2, reproduced below, illustrates an electronic device structure.
3 Claim 1 is reproduced from the revised Claims Appendix in the Response to
Notification of Non-Compliant Appeal Brief dated November 21, 2014
(hereinafter “Rev. Claims App.”).
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Application 13/408,058
FIG. 2
t
Abe Fig. 2 is a cross-sectional view showing the
structure of a semiconductor device according to
one embodiment of the invention.
1. Claim 1
The Examiner finds Abe discloses a pair of adjacent inner rows of I/O pads
10a4 and connective structures 16 coupling the first major surface of electronic
device 14 to the I/O pads. Final 2;5 Ans. 3.6 The Examiner finds Shirasaka
discloses an outer row of I/O pads and connective structures coupling the first
major surface of an electronic device to the outer row of I/O pads. Final 5; Ans. 3—
4 (relying on Shirasaka Fig. 4).7 The Examiner concludes that “[i]t would have
4 According to the Appellant, Abe “shows a single pair of I/O pads 10a (which
would be equivalent to, for example, Appellant’s pair of adjacent inner rows of I/O
pads 17 shown in FIG. 1)” (emphasis omitted). Appeal Brief dated October 31,
2014 (“App. Br.”), at 6.
5 Final Office Action dated June 5, 2014.
6 Examiner’s Answer dated February 27, 2015.
7 The Appellant argues that the Examiner’s reliance on Shirasaka Figure 4 in the
Examiner’s Answer is a new ground of rejection. Therefore, the Appellant
“requests that the prosecution in the case be reopened.” Reply Brief dated April
14, 2015 (“Reply Br.”), at 3. Such a request is properly made in a petition under
37C.F.R. § 1.181, not a Reply Brief. See 37 C.F.R. 41.40 (2015).
3
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Application 13/408,058
been obvious to one of ordinary skill in the art at the time the invention was made
to include the outer row of I/O pads [disclosed in Shirasaka] with the device of
Abe for providing additional I/O pads.”8 Final 5.
The Appellant argues:
[T]here is no motivation for Abe to add more I/O pads. Furthermore,
there is no teaching in Shirasaka to go from one row of I/O pads to
more than one row. Shirasaka discusses only shrinking or making
more reliable, a package having a second row of I/O pads already, not
adding a second row.
Reply Br. 5 (emphasis added).
The Appellant’s argument is not persuasive of reversible error. To the
extent the Appellant is arguing that Abe alone does not provide motivation to add
an outer row of I/O pads, the Appellant’s argument fails to consider the prior art as
a whole. See In re Keller, 642 F.2d 413, 425 (CCPA 1981) (test for obviousness is
what the combined teachings of the references would have suggested to those of
ordinary skill in the art). Shirasaka discloses an electronic device structure
comprising an inner row of I/O pads and an outer row of I/O pads. In the rejection
on appeal, the Examiner relies on Shirasaka to show that, at the time of the
Appellant’s invention, it was known to include inner and outer rows of I/O pads in
an electronic device structure to provide additional pads. Ans. 4 (citing Shirasaka
col. 3,11. 50—53). The Examiner concludes that it would have been obvious to one
of ordinary skill in the art to add an outer row of I/O pads to Abe’s structure for the
same reason (i.e., to provide additional pads). Final 5. The Appellant does not
direct us to any credible evidence to the contrary.
8 We understand the Examiner’s proposed modification of Abe to include the
connective structures of Shirasaka which couple the electronic device to the outer
row of I/O pads.
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Application 13/408,058
In the Reply Brief, the Appellant also argues:
The slot DG of Shirasaka Fig 4 is not formed underneath the
electronic device .... It is submitted that the slot DG as shown in
Shirasaka would not work in Abe because it would not be physically
possible to attach the second major surface [of the electronic device
(i.e., lower surface)] to the opposing I/O pads as Abe shows, as the
groove extends beyond the planar surface of the lower surface of the
electronic device.
Reply Br. 4.
The Appellant’s argument is not persuasive of reversible error. In the
§ 103(a) rejection on appeal, the Examiner finds Abe discloses that the second
major surface (i.e., lower surface) of electronic device 14 is attached to opposing
I/O pads 10a in a pair of adjacent inner rows of I/O pads. The Examiner finds I/O
pads 10a have interior facing sidewall surfaces that oppose each other. Final 2
(citing Abe Fig. 2). As shown in Abe Figure 2, encapsulating material 18 is
disposed between the interior facing sidewall surfaces. In the modification
proposed by the Examiner, the Examiner does not physically substitute Shirasaka’s
slot DG into the structure of Abe. Rather, the Examiner relies on Shirasaka to
show that removing encapsulating material 18 from the interior facing sidewall
surfaces of I/O pads 10a in Abe would provide access to the pads.9 See Final 5.
The Appellant argues that:
Shirasaka has the same shortcomings of the prior art which Abe was
seeking to improve. In Abe, paragraph [005]-[006], Abe states that,
“this presents a problem that it is difficult to clean flux residues
remaining between a package and a substrate after the package has
been mounted onto the substrate. This happens because the edges of
the projected portions 110a, or external terminals, and part of the sides
9 “The test for obviousness is not whether the features of a secondary reference
may be bodily incorporated into the structure of the primary reference.” Keller,
642 F.2d at 425.
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Application 13/408,058
of the resin 118 are coplanar.” Shirasaka in Fig 4 shows terminals and
sides of the resin that are coplanar such that it is believed that flux
residues will be difficult to clean. Thus it is submitted that there is a
teaching away to combine Abe with Shirasaka, as Shirasaka presents
the same problems that Abe was trying to solve.
Reply Br. 4.
In the rejection on appeal, the Examiner is proposing to remove resin 18
from the vertical sidewall surfaces of the inner rows of I/O pads 10a in Abe. The
Appellant has not directed us to any credible evidence showing that the problem
described in Abe would exist after resin perpendicular to the surface of the
substrate is removed. Thus, the Appellant’s argument is not persuasive of
reversible error.
The Appellant does not present arguments in support of the separate
patentability of any of dependent claims 2—6 and 8. See App. Br. 8. Therefore, the
§ 103(a) rejection of claims 1—6 and 8 is sustained.
2. Claim 7
Claim 7 depends from claim 1 and recites:
wherein one I/O pad within the pair of adjacent inner rows of I/O pads
is attached to the second major surface with a conductive material,
and wherein a second I/O pad within the pair of adjacent inner rows of
I/O pads is attached to the second major surface with a non-
conductive material.
Rev. Claims App. (emphasis added).
The Examiner finds Abe discloses that one I/O pad is attached to the second
major surface with conductive material 16 (i.e., a bonding wire) and a second I/O
pad is attached to the second major surface with a non-conductive material 12 (i.e.,
adhesive tape). Final 3.
The Appellant argues that “Abe shows a connective structure 16 attached to
the first major surface, not the second major surface, as appellant’s claim.” App.
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Application 13/408,058
Br. 8. The Appellant’s argument is supported by the record. See, e.g., Abe Fig. 2
(showing connective structure 16 and material 12 attached to different major
surfaces of electronic device 14). Therefore, the § 103(a) rejection of claim 7 is
not sustained.
3. Claim 21
The Examiner relies on Abe to show:
the leadframe having at least two adjacent inner rows of I/O pads
(10a), and having a gap between the at least two adjacent inner rows
of I/O pads (Fig 2) wherein the at least two adjacent inner rows of I/O
pads are isolated, and wherein the plurality of I/O pads in adjacent
rows each has an interior facing sidewall surface opposing eah [sic,
each] other [as recited in claim 21.]
Final 4 (emphasis added).
The Examiner finds Abe does not disclose that encapsulating material “is
absent from a portion of the interior facing sidewall surface of each of the adjacent
inner rows of I/O pads” as recited in claim 21 and relies on Shirasaka to show that
limitation. Final 5.
Referring to Shirasaka Figure 14, the Appellant argues that “in any of the
embodiments of Shirasaka that have connective structures coupled to the second
major surface [(i.e., upper surface)], the slot or gap DG does not underlie the
electronic device as appellant claims.” App. Br. 9.
The Appellant’s argument is not persuasive of reversible error. In contrast
to claim 1, claim 21 does not recite an outer row of I/O pads and corresponding
connective structures on the upper surface of the electronic device coupling the
device to the outer row of I/O pads.10 Thus, in the § 103(a) rejection of claim 21,
10 Moreover, in contrast to claim 1, “first surface” and “second major surface” of
the electronic device recited in claim 21 refer to lower and upper surfaces,
respectively, of the electronic device.
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Application 13/408,058
the Examiner merely relies on Shirasaka to show that removing encapsulating
material from a portion of the interior facing sidewall surfaces of the EO pads in
Abe would enable access to the pads. Final 5. The Examiner relies on Abe, not
Shirasaka, to show an electronic device overlying the gap between adjacent inner
rows of I/O pads. Final 4.
The Appellant also argues that Abe and Shirasaka both show a flag portion.
App. Br. 9. The Appellant’s argument, however, does not address the Examiner’s
finding that Shirasaka Figure 14 shows “the lead frame is absent a flag portion
adjacent a central portion of the electronic device.” Final 5. Moreover, claim 9
does not expressly exclude a flag portion, and the Appellant does not explain, in
any detail, why the language of claim 9 inherently excludes a flag portion. For
those reasons, the Appellant’s argument is not persuasive of reversible error.
The Appellant does not present arguments in support of the separate
patentability of any of dependent claims 22—26. See App. Br. 10. Thus, for the
reasons set forth above, the § 103(a) rejection of claims 21—26 is sustained.
4. Claim 9
The Appellant argues “[tjhere is no reason or motivation for Abe to include
a slot between the I/O pads for accessing the I/O pads.” App. Br. 8. Claim 9 does
not expressly recite a slot. To the extent that the Appellant is referring to the
absence of an encapsulating layer “from a portion of the interior facing sidewall
surface of the multiple rows of I/O pads” recited in claim 9, the Appellant’s
argument is not persuasive of reversible error for the reasons discussed above in
sustaining the § 103(a) rejections of claims 1 and 21.
The Appellant does not present arguments in support of the separate
patentability of any of dependent claims 10-14. See App. Br. 9. Thus, for the
reasons set forth above, the § 103(a) rejection of claims 9—14 is sustained.
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C. DECISION
The Examiner’s decision rejecting claims 1—6, 8—14 and 21—26 under 35
U.S.C. § 103(a) as unpatentable over Abe in view of Shirasaka is affirmed.
The Examiner’s decision rejecting claim 7 under 35 U.S.C. § 103(a) as
unpatentable over Abe in view of Shirasaka is reversed.
No time period for taking any subsequent action in connection with this
appeal may be extended under 37 C.F.R. § 1.136(a)(1).
AFFIRMED-IN-PART
9