Ex parte Amerasekera

Board of Patent Appeals and Interferences

Dec 15, 1999

08515752 (B.P.A.I. Dec. 15, 1999)

Application for patent filed August 16, 1995. According to the appellants,1
the application is a continuation of Application 08/242,925, filed May 16, 1994, now
abandoned.
1
THIS OPINION WAS NOT WRITTEN FOR PUBLICATION
The opinion in support of the decision being entered today (1) was not written for
publication in a law journal and (2) is not binding precedent of the Board.
Paper No. 25
UNITED STATES PATENT AND TRADEMARK OFFICE
__________
BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
__________
Ex parte EKANAYAKE A. AMERASEKERA
and CHARVAKA DUVVURY
__________
Appeal No. 1997-1688
Application 08/515,7521
___________
ON BRIEF
___________
Before URYNOWICZ, JERRY SMITH, and LALL, Administrative Patent
Judges.
URYNOWICZ, Administrative Patent Judge.

Decision on Appeal
This appeal is from the final rejection of claims 28-33, all
the claims pending in the application.
The invention pertains to an ESD protection circuit. Claim
28 is illustrative and reads as follows:
Appeal No. 1997-1688
Application 08/515,752
2
An ESD protection circuit for protecting a device which has a
power supply which is at a first voltage of approximately 3.3
volts and which interfaces with devices that have a supply voltage
which
is at a second voltage of approximately 5 volts, said ESD
protection circuit comprising:

a bond pad, said bond pad subjected to said first voltage or
said second voltage;
a switching element connected to said bond pad, said
switching element becomes conductive upon the occurrence of an ESD
event; and
a primary protection device connected between said switching
element and ground for dissipating an ESD signal, said primary
protection device is isolated from said bond pad except during
said ESD events.
The references relied upon by the examiner as evidence of
obviousness are:
Murayama JP-58-162065 Sep. 26, 1983
Misu et al. (Misu) JP-61-30075 Feb. 12, 1986
Taira EP-0257774 Mar. 02, 1988
Tailliet EP-0568421 Nov. 03, 1993
Isono et al. (Isono) JP-5-335495 Dec. 17, 1993
Claims 28-33 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Isono, Tailliet, Misu, Murayama or Taira.
The respective positions of the examiner and the appellants
with regard to the propriety of these rejections are set forth in
Appeal No. 1997-1688
Application 08/515,752
3
the final rejection (Paper No. 16) and the examiner’s answer
(Paper No. 22) and the appellants’ brief (Paper No. 21) and reply
brief (Paper No. 23).
Appellants’ Invention

ESD protection circuits are illustrated in Figures 2 and 5.
A protection circuit includes a bond pad 14 which is subjected to
a first voltage of approximately 3.3 volts or a second voltage of
approximately 5 volts; a switching element connected to the bond
pad, the element becoming conductive upon the occurrence of an ESD
event; and a primary protection device connected between the
switching element and ground for dissipating an ESD signal. In
accordance with the above operation, an ESD signal is prevented
from damaging input/output circuitry 18.
Opinion
We will not sustain any of the five prior art rejections of
claim 28.
In the answer, the examiner in effect acknowledges that the
prior art does not teach a power supply which is at a first
Appeal No. 1997-1688
Application 08/515,752
4
voltage of approximately 3.3 volts, and devices that have a supply
voltage which is at a second voltage of approximately 5 volts, as
recited in the preamble of sole independent claim 28. Such being
the case, the examiner takes the position that the preamble is
merely a statement of intended use for the ESD protection circuit
which is entitled to no patentable weight in a claim such as claim
28 drawn to structure. In the reply brief, appellants take issue
with this position.
We are not persuaded by the examiner’s position. The first
recitation in the body of the claim refers to “said first voltage”
and “said second voltage”. Thus, the words in the preamble
provide antecedent basis for terms used in the body of claim 28
and are necessary to give meaning to the claim. Gerber Garment
Tech., Inc. v. Lectra Sys., Inc., 916 F.2d 683, 689, 16 USPQ2d
1436, 1441 (Fed. Cir. 1990).
The examiner’s position to the effect that it would have been
obvious that the protection circuits of the prior art could have
been used for dual supplies of approximately 3.3 and 5 volts and
that appellants have failed to prove otherwise is also not
persuasive. The burden is initially on the examiner to establish
a prima facie case of obviousness. Here, the examiner has not
Appeal No. 1997-1688
Application 08/515,752
5
shown through evidence that any of the circuits in the prior art
cited against the claims would operate at approximately 3.3 and 5
volts. For example, in discussing the operation of his device at
page 5, Isono refers to relatively high breakdown voltages of 250
and 350 volts and this suggests that Isono would not be operable
at the low voltages intended by appellants. Furthermore, the mere
fact that the prior art may be modified in the manner suggested by
the examiner does not make the modification obvious unless the
prior art suggested the desirability of the modifications. In re
Fritch, 972 F.2d 1260, 1266, 23 USPQ2d 1780, 1783, 1784 (Fed. Cir.
1992). The examiner has not established that any one of the
references applied against claim 28 suggests any motivation for,
or desirability of, the change espoused.
Although we will not sustain any of the rejections of claim
28, we agree with the examiner that each of Isono, Misu and
Murayama discloses the switching element and primary protection
device limitations defined in claim 28.
Whereas we will not sustain any of the rejections of claim
28, we will not sustain any of the rejections of dependent claims
29-33 over the same prior art.
REVERSED
Appeal No. 1997-1688
Application 08/515,752
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STANLEY M. URYNOWICZ, JR. )
Administrative Patent Judge )
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)
)
) BOARD OF PATENT
)
JERRY SMITH ) APPEALS AND
Administrative Patent Judge )
) INTERFERENCES
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PARSHOTAM S. LALL )
Administrative Patent Judge )
SMU/kis
Mark A. Valetti
Patent Department
Texas Instruments Incorporated
Post Office Box 655474 MS 219
Dallas, TX 75265