Ex Parte Altman et al

Board of Patent Appeals and Interferences

May 29, 2009

10244559 (B.P.A.I. May. 29, 2009)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte ERIK RICHTER ALTMAN, RAVI NAIR, JOHN KEVIN
O’BRIEN, KATHRYN MARY O’BRIEN, PETER HOWLAND ODEN,
DANIEL ARTHUR PRENER, and SUMEDH WASUDEO SATHAYE
____________________

Appeal 2008-2386
Application 10/244,559
Technology Center 2100
____________________

Decided:1 May 29, 2009
____________________

Before ALLEN R. MACDONALD, ST. JOHN COURTENAY III, and
DEBRA K. STEPHENS, Administrative Patent Judges.

STEPHENS, Administrative Patent Judge.

DECISION ON APPEAL

1 The two-month time period for filing an appeal or commencing a civil
action, as recited in 37 C.F.R. § 1.304, begins to run from the decided date
shown on this page of the decision. The time period does not run from the
Mail Date (paper delivery) or Notification Date (electronic delivery).
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STATEMENT OF THE CASE
Appellants appeal under 35 U.S.C. § 134 from a final rejection of
claims 1-40. We have jurisdiction under 35 U.S.C. § 6(b).

We AFFIRM-IN-PART.

We also enter new grounds of rejection against claims 1, 16, 32, 35,
38, and 39 under the provisions of 37 C.F.R. § 41.50(b).

Introduction
According to Appellants, the invention is a method for emulating the
instruction set of one processor using the instruction set of another processor
(Spec. 2, ll. 11-13). A virtual-to-real memory mapping mechanism of a host
multiprocessor system’s operating system is used (Abstract). The mapping
mechanism includes inputting a target virtual memory address into a
simulated page table to obtain a host virtual memory address (Abstract).

Exemplary Claim(s)
Claims 1, 16, 21, and 22 are exemplary claims and are reproduced
below:
1. A method of emulating a target system's memory addressing
using a virtual-to-real memory mapping mechanism of a host multiprocessor
system's operating system, comprising:

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inputting a target virtual memory address into a page table to obtain a
host virtual memory address,
wherein said target system is oblivious to software it is running on.

16. A method of mapping a memory addressing of a multiprocessing
system when it is emulated using a virtual memory addressing of another
multiprocessing system, comprising:

accessing a local lookaside table (LLT) on a target processor with a
target virtual memory address;

determining whether there is a "'miss" in the LLT; and

with said miss determined in said LLT, obtaining a lock for a global
page table.

21. In a host multiprocessor system for emulating the operation of a
target n-processor system (n≥1) by execution of one or more threads
representing the operation of the target system, a method for emulating the
target system's memory addressing using a virtual-to-real memory mapping
mechanism of the host multiprocessor system's operating system, said
method comprising:

(a) reading a target system virtual memory address (ATV);

(b) mapping said ATV to a target real address (ATR);

(c) mapping said ATR to a host virtual memory address (AHV); and

(d) mapping said AHV to a host real memory address, wherein the
emulation of the target system's memory addressing is treated as an
application running on the host multiprocessor system.

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22. A system for emulating a target system's memory addressing,
comprising:

a page table for mapping a target virtual memory address from a target
system to a host virtual memory address and page access rights for said
target virtual memory address,

wherein said target system is oblivious to the software it is running
on.

Prior Art
The prior art relied upon by the Examiner in rejecting the claims on
appeal is:
Richter US 5,440,710 Aug. 8, 1995
Onodera US 5,574,878 Nov. 12, 1996
Bodin US 5,675,762 Oct. 07, 1997
Bugnion US 6,075,938 Jun. 13, 2000
Noel US 6,381,682 B2 Apr. 30, 2002

Egolf US 6,480,845 B1 Nov. 12, 2002
(filed Jun. 14, 2000)

IBM, Low-Synchronization Translation Lookaside Buffer Consistency
Algorithm, IBM Technical Disclosure Bulletin, US, vol. 33, No. 6B, 428-
433 (1990).

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Rejections
The Examiner rejected claims 21-37 under 35 U.S.C. § 101(a) as
being directed to non-statutory matter.2
The Examiner rejected claims 1-4, 6-8, and 15 under
35 U.S.C. § 102(b) as being anticipated by Noel.
The Examiner rejected claims 16, 17, 20, 32-36, 38, and 39 under
35 U.S.C. § 102(b) as being anticipated by Richter.
The Examiner rejected claims 22, 24, and 25 under 35 U.S.C. § 102(e)
as being anticipated by Egolf.
The Examiner rejected claim 5 under 35 U.S.C. § 103(a) as being
unpatentable over Noel and IBM.
The Examiner rejected claims 9-13 under 35 U.S.C. § 103(a) as being
unpatentable over Noel and Onodera.
The Examiner rejected claims 14 and 21 under 35 U.S.C. § 103(a) as
being unpatentable over Noel, Onodera, and Richter.
The Examiner rejected claims 18, 19, 37, and 40 under
35 U.S.C. § 103(a) as being unpatentable over Richter and Bodin.
The Examiner rejected claims 23 and 26-31 under 35 U.S.C. § 103(a)
as being unpatentable over Egolf and Bugnion.

2 The Examiner rejected claims 23 and 28 under 35 U.S.C. § 112,
second paragraph, for being indefinite for failing to provide a structure in the
disclosure that actually performs the functions recited in the claims. This
rejection was withdrawn in the Examiner’s Answer (Ans. 15, ¶ 10.2).

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GROUPING OF CLAIMS
Appellants have grouped claims together to address the grounds of
rejection (App. Br. 8, §VI. GROUNDS OF REJECTION and App. Br, 9-14,
§VII. ARGUMENTS). We consider Appellants groupings; however, we
have grouped the claims together as follows:
(1) Claims 22-31 and 32-35 as separate groups in response to the
rejection under 35 U.S.C. § 101. We consider the § 101 rejection of claims
21, 36, and 37 separately.
(2) Claims 1-4, 6-8 and 15 as a group in response to the rejection
under 35 U.S.C. § 102. We will, therefore, treat dependent claims 2-4, 6-8,
and 15 as standing or falling with independent claim 1.
(3) Claims 5 and claims 9-14 as a group in response to the rejection
under 35 U.S.C. § 103.
(4) Claim 21 in response to the rejection under 35 U.S.C. § 103.
(5) Claims 16-17 and 20 as a group in response to the rejection
under 35 U.S.C. § 102. We will, therefore, treat claims 17 and 20 as
standing or falling with independent claim 16.
(6) Claims 18-19 as a group in response to the rejection under
35 U.S.C. § 103.
(7) Claims 32-35 as a group in response to the rejection under 35
U.S.C. § 102. We will, therefore treat dependent claims 33-34 as standing
or falling with independent claim 32.
(8) Claim 36 in response to the rejection under 35 U.S.C. § 102.
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(9) Claim 39 in response to the rejection under 35 U.S.C. § 102.
(10) Claim 38 in response to the rejection under 35 U.S.C. § 102.
(11) Claims 37 and 40 in response to the rejection under 35 U.S.C.
§ 103.
(12) Claims 22, 24 and 25 in response to the rejection under
35 U.S.C. § 102. We will, therefore, treat dependent claims 24-25 as
standing or falling with independent claim 22.
(13) Claims 23 and 26-31 in response to the rejection under 35
U.S.C. § 103.
See 37 C.F.R. § 41.37(c)(1)(vii) (“Notwithstanding any other
provision of this paragraph, the failure of appellant to separately argue
claims which appellant has grouped together shall constitute a waiver of any
argument that the Board must consider the patentability of any grouped
claim separately.”).

ISSUE
35 U.S.C. § 101: claims 21-37
Appellants argue independent claims 22, 32, 36, and 37 and their
dependent claims clearly refer to either software modules or physical
structures that clearly perform various processing acts; therefore, these
claims recite statutory material (App. Br. 9). Appellants admit claim 21
could more clearly define whether a system or method is being claimed;
however, Appellants argue the claim clearly recites acts being executed by a
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computer (id.). Thus, Appellants contend claim 21 also recites statutory
subject matter (id.).
The Examiner asserts neither a transformation of an article nor a
tangible final result is produced (Ans. 15, ¶ 10.1.2). The Examiner further
determines the claims are drawn to the manipulation of abstract ideas and
software, per se (id.). Therefore, the Examiner concludes the claims are not
directed to statutory subject matter (id.).
Issue 1: Have Appellants met the burden of showing the Examiner
erred in concluding claims 21-37 are directed toward non-statutory subject
matter since they are drawn to software per se?

FINDINGS OF FACT (FF)
Appellants’ Invention
(1) The present invention emulates programs written for a system
(e.g., a “target computing system”), to perform with the same results on
another system (e.g., a “host computing system”) (Spec. 2, ll. 11-13). A
computing system includes processors, the memory, and the input/output
devices (Spec. 2, ll. 8-10).
(2) To reduce overhead in the present invention, a local cache of
entries in a page table is provided – one per simulated processor (Spec. 20,
ll. 11-15). The cache is shown as a Local Lookaside Table (Spec. 20, ll. 13-
15). ”Local” means on the target processor (Spec. 21, ll. 1-3).
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(3) The method of the present invention may be implemented by
operating a computer to execute a sequence of machine-readable instructions
that may reside in various types of signal-bearing media including a RAM or
a magnetic data storage diskette (Spec. 25, ll. 7-11). The instructions may
also be stored on a variety of machine-readable data storage media, such as
DASD storage (e.g., a conventional "hard drive" or a RAID array), magnetic
tape, electronic read-only memory (e.g., ROM, EPROM, or EEPROM), an
optical storage device (e.g. CD-ROM, WORM, DVD, digital optical tape,
etc.), paper "punch" cards, or other suitable signal-bearing media including
transmission media such as digital and analog and communication links and
wireless (Spec. 25, ll. 12-19).
(4) The invention provides a solution to the memory mapping
problem in a multiprocessing environment where there is a many-to-many
mapping, and where there is not actual, strict control over the software
running on the target (Spec. 26, ll. 3-6). A key advantage is using the virtual
memory addressing of another system for emulation as this allows for a
much larger space when mapping occurs (Spec. 26, ll. 15-18). Thus, a 64-
bit virtual memory of the target (guest) can be targeted (mapped) to a 64-bit
virtual memory of the host, whereas if the same memory was to be mapped
to a real memory, then only 32-bit may be possible (Spec. 26, ll. 18-20).

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PRINCIPLES OF LAW
§ 101
"Whoever invents or discovers any new and useful process, machine,
manufacture, or composition of matter, or any new and useful improvement
thereof, may obtain a patent therefor, subject to the conditions and
requirements of this title." 35 U.S.C. § 101. "[N]o patent is available for a
discovery, however useful, novel, and nonobvious, unless it falls within one
of the express categories of patentable subject matter of 35 U.S.C. § 101."
Kewanee Oil Co. v. Bicron Corp., 416 U.S. 470, 483 (1974).
The Court of Appeals for the Federal Circuit recently clarified the
bounds of patent-eligible subject matter for process claims. See In re Bilski,
545 F.3d 943 (Fed. Cir. 2008) (en banc). The Bilski court found the
machine-or-transformation test the applicable test for determining patent
eligibility of a process under § 101. See Bilski at 956.
The Bilski court, in following the Supreme Court, enunciated the
machine-or-transformation test as follows: “A claimed process is surely
patent-eligible under § 101 if: (1) it is tied to a particular machine or
apparatus, or (2) it transforms a particular article into a different state or
thing.” Id. at 954 (citing Benson, 409 U.S. at 70 (1972)).

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Claim Construction
"The Patent and Trademark Office (PTO) must consider all claim
limitations when determining patentability of an invention over the prior
art." In re Lowry, 32 F.3d 1579, 1582 (Fed. Cir. 1994) (citing In re Gulack,
703 F.2d 1381, 1385 (Fed. Cir. 1983)). "Claims must be read in view of the
specification, of which they are a part." Markman v. Westview Instruments,
Inc., 52 F.3d 967, 979 (Fed. Cir. 1995) (en banc).

ANALYSIS
35 U.S.C. § 101: claims 21-37
We interpret claim 21 as a method implemented in a host
multiprocessor system (i.e., a machine) that emulates the operation of a
target n-processor system using a virtual-to-real memory mapping
mechanism of the host multiprocessor’s operating system.
Claim 21 recites a method performed in a host multiprocessor system
that emulates a target n-processor system; therefore the process claim
includes use of a specific machine. We further find use of the specific
machine imposes meaningful limits on the scope of the claims – the host
processor emulates a target system’s memory addressing causing it to
behave like the target processor. Therefore, we find the method of claim 21
is tied to a particular machine or apparatus under the first prong of the
machine-or-transformation test reaffirmed by the Federal Circuit in Bilski,
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545 F.3d at 956. Accordingly, we conclude that claim 21 is directed to
statutory subject matter under 35 U.S.C. § 101.

Claim 22 recites a system for emulating that includes a page table for
mapping a target virtual memory address from a target system. Appellants
define a “system” as hardware, a software module, or computer program that
“clearly perform the various processing acts within the host computer” (App.
Br. 9 and Reply 5). From the above discussion, we conclude that the scope
of the claimed “system” broadly encompasses both statutory (hardware
based) and non statutory (disembodied software or computer program
per se) embodiments. Our reviewing court has stated that “[t]he four
categories [of § 101] together describe the exclusive reach of patentable
subject matter. If a claim covers material not found in any of the four
statutory categories, that claim falls outside the plainly expressed scope of
§ 101 even if the subject matter is otherwise new and useful.” In re Nuijten,
500 F.3d 1346, 1354 (Fed. Cir. 2007) reh’g en banc denied, 515 F.3d 1361
(Fed. Cir. 2008), cert. denied, __ U.S.__, 127 S.Ct. 70 (2008).
Moreover, we find claim 22 does not recite “specific electronic
structural elements which impart a physical organization on the information
stored in memory” In re Lowry, 32 F.3d at 1583 (emphasis added). Instead,
the scope of the claimed “system” broadly encompasses an abstract
disembodied data structure (page table) that does not define any structural or
functional interrelationships between the data structure and a tangible
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memory which permits the data structure’s functionality to be realized (In re
Warmerdam, 33 F3d. at 1361). Accordingly, Appellants have not shown
the Examiner erred in concluding that claim 22 is directed to non-statutory
subject matter.

Appellants have not separately argued the statutory matter rejection of
dependent claims 23-31. Therefore, Appellants have not shown the
Examiner erred in concluding that claims 23-31 are directed to non-statutory
subject matter.

Claim 32 recites a system for emulating a target system’s memory
addressing using a virtual-to-real memory mapping mechanism of a host
multiprocessor system’s operating system. While the preamble of claim 32
could be construed as a statement of intended use, we note that the body of
claim 32 includes a local lookaside table that receives a target virtual
memory address and outputs a host virtual memory address and page access
rights (claim 32). Thus, when the language of the claim is considered as a
whole, we conclude that execution by a machine is required. The local
lookaside table is a cache or memory (FF 2). Thus, it is our view that the
language of claim 32 as a whole requires “specific electronic structural
elements which impart a physical organization on the information stored in
memory.” See In re Lowry, 32 F.3d at 1583. Appellants also indicate
several advantages to the present invention including the ability to more
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efficiently and optimally map the memory address of one system using the
virtual addressing of another system (FF 4).
Accordingly, we conclude the invention as recited in claim 32 is
directed to statutory subject matter. Additionally, since claims 33-35 depend
directly or indirectly from claim 32, we conclude that claims 33-35 are
directed to statutory subject matter.

Claim 36 specifically recites a system for mapping addressing of a
multiprocessor system when it is emulated using a virtual memory
addressing of another multiprocessor system and a local lookaside table on a
target processor. Since specific electronic structural elements are claimed
(i.e., “another multiprocessor system” and “a target processor” as machines),
we conclude that claim 36 is directed to statutory subject matter.

Claim 37 recites a system for multiprocessor emulation of a target n-
processor system by executing one or more threads representing the
operation of the target system. Claim 37 further recites the use of a virtual-
to-real memory mapping mechanism. We note that “execute” is defined as
“to perform an instruction” or “in programming, execution implies loading
the machine code of the program into memory and then performing the
instruction” (See Microsoft Computer Dictionary 200 (5th ed. 2002). Thus,
we find structure (i.e., a multiprocessor machine) is implied through the term
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“executing.” Accordingly, we conclude that claim 37 is directed to statutory
subject matter.

Based on the above, Appellants have not shown the Examiner erred in
concluding that claims 22-31 are directed to non-statutory subject matter.
Accordingly, we sustain the Examiner’s rejection of claims 22-31 under
35 U.S.C. § 101. Because Appellants have shown the Examiner erred in
concluding that claims 21 and 32-37 are directed to non-statutory subject
matter, we reverse the Examiner’s rejection of claims 21 and 32-37 under
35 U.S.C. § 101.

ISSUES
35 U.S.C. § 102(b) – claims 1-4, 6-8, and 15 and
35 U.S.C. § 103(a): claims 5, 9-14, and 21
Appellants contend Noel does not address emulation of a target
system as recited in the preamble and “wherein” clause of independent claim
1 and thus, Noel does not teach a target and host system (App. Br. 10-12).
Nor, according to Appellants, does Noel teach mapping virtual memory
addresses (App. Br. 12). Appellants conclude with an argument that Noel
and the various secondary references cited by the Examiner are non-
analogous art since Noel does not address emulation of a target system on a
host system (id.).
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The Examiner counters by concluding the preamble does not have
patentable weight since none of the claim elements refer to a host or target
system except the “wherein” clause which does not further limit the claim
(Ans. 16). The Examiner further finds emulation is performed by the Noel
reference and also that Noel is analogous art (Ans. 16-17, ¶ 10.3.2.3).

Issue 2: Have Appellants met the burden of showing the Examiner
erred in finding Noel is analogous art?
Issue 3: Have Appellants met the burden of showing the Examiner
erred in finding Noel discloses inputting a target virtual memory address
from which a host virtual memory address is obtained?

Appellants argue Richter is not emulating one multiprocessor system
on another multiprocessor system (App. Br. 12). Appellants further argue
the translation-lookaside buffer of Richter is not “local” and no mention is
made of a “global” mechanism (App. Br. 13). Appellants continue that
Richter does not disclose a local lookaside table and a global page table (id.).
Nor does Richter describe that when a miss is determined in the LLT, a lock
is obtained for a global page table (App. Br. 14).
The Examiner finds claim 16 does not recite multiprocessor systems
in the claim limitations or refer to them in the preamble (Ans. 18, ¶ 10.4.2.1
and 10.4.2.2). The Examiner further finds the terms “global” and “local” do
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not necessitate or imply a multiprocessing system exists (Ans. 18, ¶
10.4.2.1).

35 U.S.C. § 102(b) – claims 16-17, 20, 32- 36, and 39 and
35 U.S.C. § 103(a): claims 18-19
Issue 4: Have Appellants met the burden of showing the Examiner
erred in finding the translation-lookaside buffer of Richter is a local look-
aside buffer and Richter discloses determining if a virtual memory address is
a miss for those stored in the local lookaside table and if so, locking a global
page table?

35 U.S.C. § 102(b) – claims 37 and 38 and
35 U.S.C. § 103(a): claim 40
Issue 5: Have Appellants met the burden of showing the Examiner
erred in finding Richter discloses a virtual memory address as input and a
host virtual memory address as output?

35 U.S.C. § 35 U.S.C. § 102(e) – claims 22, 24, and 25 and
35 U.S.C. § 103(a): claims 23 and 26-31
Appellants argue Egolf teaches against use of a page table for
mapping between target and host virtual memories (App. Br. 14). Egolf
instead, according to Appellants, describes a method of mapping that is a
simple translation described by an arithmetic formula (id.). Appellants also
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contend the secondary reference Bugnion is not properly combinable with
Egolf since Egolf has no page tables (App. Br. 14-15).
The Examiner finds Egolf discloses use of page tables, from simple to
complex and specifically describes computing a virtual address and then a
real address by reference to various emulated page tables and page table
pointers (Ans. 18-19, ¶ 10.5.2.1).
Issue 6: Have Appellants met the burden of showing the Examiner
erred in finding Egolf discloses a page table that shows mapping between a
target system virtual memory address to a host virtual memory address?

FINDINGS OF FACT (FF)
Noel’s Invention
(5) Noel describes a method and apparatus for multiple instances of
operating systems executing cooperatively in a single multiprocessor
computer (Abstract).
(6) A virtual machine uses a single physical machine, with one or
more physical processors, in combination with software which simulates
multiple virtual machines (col. 2, ll. 32-36).
(7) Memory management software maintains tables of mapping
information (page tables) that keep track of where each virtual page is
located in physical memory (col. 31, ll. 41-44). A process, through a
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memory management unit, utilizes this mapping information when it
translates virtual addresses to physical addresses (id.).
(8) The Hive Project uses a cell architecture such that when the
system boots, each cell manages processors, memory, and I/O devices as if it
were an independent operating system (col. 3, ll. 33-38). The cells
cooperate to present the illusion of a single system to user-level processes
(col. 3, ll. 38-40).
Richter’s Invention
(9) Richter describes a method and system for memory
management using segmentation and paging (col. 1, ll. 8-10).
(10) In memory management systems using segments or pages, a
user is prevented from harming data stored in another user’s segments or
pages since the CPU checks that memory references are to a segment or
page belonging to that user (col. 1, ll. 21-24). A page table provides
mapping or translation between a program or virtual address generated by
the user’s program and a physical address of a location in memory (col. 1, ll.
37-40).
(11) A page table called a translation-lookaside buffer (TLB)
translates a virtual page number (upper bits of the virtual address) to the
physical page number (col. 1, ll. 52- 55).
(12) In the TLB, a table of entries is stored in a RAM array (col. 3,
ll. 52-54 and Figure 2, element 63). An entry has a virtual page number
field and a physical page number field (col. 3, ll. 54-56). An input virtual
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page number is compared to the entries of virtual page numbers in the table
and if a match is found, the physical address is output (col. 3, l. 56 – col. 4, l.
2).
(13) A “page fault” is signaled if a miss occurs (the translation is not
present in the TLB) (col. 4, ll. 10-13). The page fault causes the user’s
program to suspend while a supervisory program loads, corrects or modifies
the TLB or page tables (col. 4, ll. 13-17).
Egolf’s Invention
(14) Egolf discloses a method and system for emulating virtual
memory paging during emulation of a target multiprocessor system for
either a single processor or multiprocessor system (col. 1, ll. 19-21 and col.
2, ll. 17-20).
(15) A first computer architecture is emulated on a second computer
architecture (col. 1, ll. 24-26). The computer with the second computer
architecture is the “Host” computer system and the virtual computer system
having the first “emulated” computer architecture is the “Target” system
(col. 1, ll. 33-37).
(16) For virtual memory architectures, a critical element is mapping
addresses between the Target and Host systems and more specifically,
translation of target virtual addresses into host virtual addresses (col. 1, ll.
56-60). Host virtual memory addresses are mapped and used as Target
virtual memory addresses (col. 8, ll. 44-46).
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(17) An attractive approach for some factors is to relieve the
Emulator of virtual to real translation by mapping target virtual addresses
directly to host applications (col. 11, ll. 36-39). Building page tables and
managing real memory are eliminated and instead, the virtual memory for
each Working Space could be requested directly from the host O/S (col. 11,
ll. 43-49).

PRINCIPLES OF LAW
Analogous Art
Two separate tests define the scope of analogous prior art: (1) whether
the art is from the same field of endeavor, regardless of the problem
addressed and, (2) if the reference is not within the field of the inventor's
endeavor, whether the reference still is reasonably pertinent to the particular
problem with which the inventor is involved. In re Deminski, 796 F.2d 436,
442 (Fed. Cir. 1986); see also In re Wood, 599 F.2d 1032, 1036 (CCPA
1979) and In re Bigio, 381 F.3d 1320, 1325 (Fed. Cir. 2004).

Anticipation
Anticipation is established only when a single prior art reference
discloses, expressly or under the principles of inherency, each and every
element of a claimed invention as well as disclosing structure which is
capable of performing the recited functional limitations. RCA Corp. v. App.
Dig. Data Sys., Inc., 730 F.2d 1440, 1444 (Fed. Cir. 1984); W.L. Gore and
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Assoc., Inc. v. Garlock, Inc., 721 F.2d 1540, 1554 (Fed. Cir. 1983).

Obviousness
Appellants have the burden on appeal to the Board to demonstrate
error in the Examiner’s position. See In re Kahn, 441 F.3d 977, 985-86
(Fed. Cir. 2006).
KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007) (citing
Graham v. John Deere Co., 383 U.S. 1, 12 (1966)), reaffirmed principles
based on its precedent that “[t]he combination of familiar elements
according to known methods is likely to be obvious when it does no more
than yield predictable results.” Id. The Court explained:
When a work is available in one field of endeavor, design
incentives and other market forces can prompt variations of it,
either in the same field or a different one. If a person of
ordinary skill can implement a predictable variation, § 103
likely bars its patentability. For the same reason, if a technique
has been used to improve one device, and a person of ordinary
skill in the art would recognize that it would improve similar
devices in the same way, using the technique is obvious unless
its actual application is beyond his or her skill.

Id. at 417. The operative question in this “functional approach” is thus
“whether the improvement is more than the predictable use of prior art
elements according to their established functions.” Id.

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Preamble
“The preamble of a claim does not limit the scope of the claim when it
merely states a purpose or intended use of the invention.” In re Paulsen, 30
F.3d 1475, 1479 (Fed. Cir. 1994). “[W]here a patentee defines a structurally
complete invention in the claim body and uses the preamble only to state a
purpose or intended use for the invention, the preamble is not a claim
limitation.” Rowe v. Dror, 112 F.3d 473, 478 (Fed. Cir. 1997) (citations
omitted).

ANALYSIS
Issue 2
35 U.S.C. § 102(b) – claims 1-4, 6-8, and 15 and
35 U.S.C. § 103(a): claims 5, 9-14, and 21
Noel is directed to sharing memory between processors in a
multiprocessor system (FF 7). The system includes memory management
software that maintains tables for mapping information regarding where
each virtual page is located in physical memory (FF 8). Appellants’
invention is also directed to a system that maps memory (see claims 1 and
21). Accordingly, we find that both Noel and Appellants’ invention are
from the same field of endeavor, i.e., systems using virtual computer
information and mapping memory and addresses. Therefore, we find Noel
and Appellants’ inventions are analogous art.

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Issue 3
35 U.S.C. § 102(b) – claims 1-4, 6-8, and 15
Noel describes a method and apparatus that includes tables of
mapping information for translating virtual addresses to physical addresses
(FF 7). Noel does not disclose inputting one virtual memory address to a
page table to obtain a second virtual memory address. Therefore, we find
Noel does not disclose each and every element as recited in claim 1. Claims
2-4, 6-8 and 15 depend from independent claim 1 and thus stand with claim
1. Accordingly, we find Appellants have shown the Examiner erred in
finding Noel discloses inputting a target virtual memory address from which
a host virtual memory address is obtained. Therefore, we reverse the
Examiner’s rejection of claims 1-4, 6-8, and 15.

35 U.S.C. § 103(a): claims 5 and 9-14
Appellants did not separately argue any elements of claims 5 and 9-
14. Since claims 5 and 9-14 depend directly or indirectly from claim 1
which we have found is not fully taught or suggested by Noel, we conclude
claim 5 is not obvious over Noel and IBM; claims 9-13 are not obvious over
Noel and Onodera; and claim 14 is not obvious over Noel, Onodera, and
Richter. Accordingly, we find Appellants have shown the Examiner erred in
rejecting claims 5 and 9-14.

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35 U.S.C. § 103(a): claim 21
Noel does not teach or suggest the invention as recited in claim 21.
The Examiner cites Onodera and Richter references in rejecting claim 21 for
obviousness over the combination of the Noel, Onodera, and Richter
technology; however, the Examiner does not point to any aspects of either
the Onodera or Richter references to support those features the Examiner
admits are not disclosed in Noel (Ans. 10). Instead, the Examiner states it
would have been obvious to map a virtual memory address to a real memory
address “to achieve the numerous advantages of virtual memory, many of
which are known in the art” (Ans. 10-11).
We agree. Additionally, we find Richter teaches translating a virtual
page number to a physical page number. However, each reference describes
mapping a virtual memory address to a real memory address. The Examiner
has not set forth evidence to show one skilled in the art would reverse the
page table functionality in Noel and combine aspects of the Noel page table
and the reversed page table to render the present invention as recited
obvious. Indeed, the Examiner has not set forth a reason for combining
these two features.
We accordingly find the gap in the combined references to be
uncomfortably wide and such gap cannot be bridged with theories or
speculation. After considering the totality of the record before us, it is our
view the weight of the evidence supports Appellants’ contention that the
Examiner has not supported the assertion that reversing the page table
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functionality is sufficient to establish a prima facie case of obviousness.
Accordingly, we conclude Appellants have met the burden of showing the
Examiner erred in concluding claim 21 is not obvious over Noel, Onodera,
and Richter. Therefore, we reverse the Examiner’s rejection of claim 21.
Issue 4
35 U.S.C. § 102(b): claims 16-17, and 20
Richter describes use of a page table or translation-lookaside buffer
for a central processing unit shared by several different users (FF 11). Claim
16 recites a local lookaside table (LLT) and a global page table. Although
we agree with the Examiner that claim 16 does not recite more than one
processor, we find Richter does not disclose locking a second table when a
“miss” occurs in a first table. Instead, Richter discloses when a miss occurs,
the user’s program is suspended while a supervisory program loads and
corrects or modifies the TLB (FF 13). Thus, we find Richter does not
disclose locking another table, but instead discloses locking the table in
which the miss occurred.
Accordingly, we find Richter does not disclose determining if a target
virtual memory address is a “miss” in a local lookaside table and if so,
obtaining a lock for a global page table. Therefore, we find Appellants have
met the burden of showing the Examiner erred in rejecting claim 16.
Claims 17 and 20 depend directly or indirectly from independent claim 16
and thus, stand with claim 16. Accordingly, we reverse the Examiner’s
rejection of claims 16-17 and 20.
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35 U.S.C. § 103(a): claims 18-19
Appellants did not separately argue claims 18-19 but instead indicated
that since independent claim 16 from which they depend was not anticipated
by Richter, claims 18-19 were not obvious over Richter and Bodin based on
the same arguments. Since we found Richter does not teach determining if a
target virtual memory address is a “miss” in a local lookaside table and if so,
obtaining a lock for a global page table, we conclude Appellants have met
the burden of showing the Examiner erred in rejecting claims 18-19.
Accordingly, we reverse the Examiner’s rejection of claims 18-19 for
obviousness over Richter and Bodin.

35 U.S.C. § 102(b): claim 32-35
Claim 32 recites a local lookaside table as does Richter (FF 11). The
system in Richter receives a virtual page number and translates it to a
physical page number (FF 11 and FF 12). We find the data in the chart does
not distinguish the structure over the prior art. Both tables accept a page
number and translate it to another page number. Moreover, claim 32 does
not recited obtaining a lock for a global page table as argued by Appellants.
Accordingly, we find Richter discloses a local lookaside table that
receives an address and outputs an address. Additionally, we find
Appellants argued features not recited in the claim. Therefore, we find
Appellants have not met the burden of showing the Examiner erred in
rejecting claim 32. Since claims 33-35 depend directly or indirectly from
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independent claim 32 and were not separately argued, claims 33-35 fall with
claim 32. As a result, we affirm the Examiner’s rejection of claims 32-35
for anticipation by Richter.

35 U.S.C. § 102(b): claim 36
Claim 36 recites a local lookaside table as does Richter; however,
claim 36 also recites means for accessing, determining, and obtaining (FF
11). The system in Richter receives a virtual page number and translates it
to a physical page number (FF 11 and FF 12). Additionally, we find Richter
does not disclose obtaining a lock for a different page table – the lock in
Richter is obtained for the same table in which the miss occurs (FF 13).
Accordingly, we find Richter does not disclose a local lookaside table that
receives a target virtual memory address and outputs a host virtual memory
address and means, based on an input from said determining means, for
obtaining a lock for a global page table. Therefore, we find Appellants have
met the burden of showing the Examiner erred in rejecting claim 36. As a
result, we reverse the Examiner’s rejection of claim 36 for anticipation by
Richter.
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35 U.S.C. § 102(b): claim 39
Claim 39 recites a local lookaside table and “the page table.” We are
unable to determine to what “the page table” refers and thus, we are unclear
as to what is locked. Accordingly, we find Appellants have not met the
burden of showing the Examiner erred in rejecting claim 39.

Issue 5
35 U.S.C. § 102(b): claim 38
Appellants have the burden of showing the Examiner erred.
Appellants have not presented any arguments to show the Examiner erred.
Appellants grouped claim 38 with claims reciting a lookaside table and
argued the cited art did not disclose this feature. However, claim 38 does
not recite a lookaside table. Thus, Appellants are arguing an element which
is not claimed. Appellants have not proffered evidence as to why Richter
does not disclose the invention as recited in claim 38. Accordingly, we find
Appellants have not met their burden of showing the Examiner erred in
rejecting claim 38 and thus, affirm the Examiner’s rejection of claim 38 for
anticipation by Richter.

35 U.S.C. § 103(a): claims 37 and 40
As with claim 38, Appellants argued an element which is not recited
in claims 37 and 40. Therefore, Appellants have not proffered evidence as
to why Richter and Bodin do not teach or suggest Appellants’ invention as
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recited in claims 37 and 40. Accordingly, we conclude Appellants have not
met the burden of showing the Examiner erred in rejecting claims 37 and 40.
Therefore, we affirm the Examiner’s rejection of claims 37 and 40 for
obviousness over Richter and Bodin.

Issue 6
35 U.S.C. § 35 U.S.C. § 102(e) – claims 22, 24, and 25
Egolf describes that mapping a target virtual address into host virtual
addresses is a critical element for virtual memory architectures (FF 14).
Egolf describes a method for mapping addresses between the Target and
Host systems without use of page tables (FF 17 and FF 18). We find Egolf
does not “teach against” using page tables, but instead, describes an
“attractive approach” that eliminates the use of page tables. By discussing
why their invention is an improvement and “an attractive approach” (and
why they are using a linear translation instead), Egolf describes an existing
technique that uses page tables for mapping target virtual addresses into host
virtual addresses.
Therefore, we find Egolf discloses a page table that shows mapping
between a target system virtual memory address and a host virtual memory
address. Additionally, we find the “wherein” clause that recites “wherein
said target system is oblivious to the software it is running on” does not
recite structure. Since Appellants have not defined “oblivious” in their
Specification, we look to the dictionary where “oblivious” is defined as
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“lacking remembrance, memory, or mindful attention” or “lacking active
conscious knowledge of awareness” (Merriam-Webster’s Collegiate
Dictionary 800 (10th ed. 2000). We are not clear how the claimed “system”
can possess a trait or feature associated with conscious beings. However,
even if we were to try to interpret “oblivious” as applied to the claimed
“system,” the “wherein” clause merely states the result of emulating and
does not add structure. (Emulate is defined as “[f]or a hardware or software
system to behave in the same manner as another hardware or software
system.” Microsoft Computer Dictionary 191 (5th ed. 2002)). Therefore,
we find this element is described by Egolf which describes a method and
system for emulating (FF 14).
Thus, we conclude Appellants have not met the burden of showing the
Examiner erred in rejecting claim 22. Since claims 24-25 depend directly
from claim 22 and were not separately argued, claims 24-25 fall with claim
22. Accordingly, we affirm the Examiner’s rejection of claims 22, 24 and
25 for anticipation by Egolf.

35 U.S.C. § 103(a): claims 23 and 26-31
Appellants did not separately argue dependent claims 23 and 26-31
but instead argued these claims are not obvious based on Egolf not
anticipating claim 22 from which claims 23 and 26-31 depend. Therefore,
we conclude Appellants have not met the burden of proving the Examiner
erred in concluding claims 23 and 26-31 are obvious over Egolf and
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Bugnion. Accordingly, we affirm the Examiner’s rejection of claims 23 and
26-31 for obviousness over Egolf and Bugnion.

CONCLUSION
Appellants have not established the Examiner erred in concluding that
claims 22-31 are directed to non-statutory subject matter.
Appellants have established the Examiner erred in concluding that
claims 21 and 32-37 are directed to non-statutory subject matter.
We further conclude Appellants have not met the burden of showing
the Examiner erred in finding Noel is analogous art. However, we conclude
that Appellants have met the burden of showing the Examiner erred in
finding Noel discloses inputting a target virtual memory address from which
a host virtual memory address is obtained. Therefore, we conclude the
Examiner erred in rejecting claims 1-4, 6-8, and 15 for anticipation by Noel,
claim 5 for obviousness over Noel and IBM; claims 9-13 for obviousness
over Noel and Onodera; and claims 14 and 21 for obviousness over Noel,
Onodera, and Richter.
Additionally, we conclude Appellants have met the burden of showing
the Examiner erred in finding Richter discloses determining if a virtual
memory address is a miss for those stored in the local lookaside table and if
so, locking a global page table. Therefore, we conclude the Examiner erred
in rejecting claims 16, 17, and 20 for anticipation by Richter and claims 18
and 19 for obviousness over Richter and Bodin.
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We conclude Appellants have not met the burden of showing the
Examiner erred in finding Richter discloses a local lookaside table that
receives a target virtual memory address and outputs a host virtual memory
address. Therefore, we conclude Appellants not met the burden of showing
the Examiner erred in rejecting claims 32-35 for anticipation by Richter.
We conclude Appellants have met the burden of showing the
Examiner erred in finding Richter discloses a local lookaside table that
receives a target virtual memory address and outputs a host virtual memory
address or obtaining a lock for a global page table. Therefore, we conclude
Appellants met the burden of showing the Examiner erred in rejecting claim
36 for anticipation by Richter.
However, we conclude Appellants have not met the burden of
showing the Examiner erred in rejecting claim 39 for anticipation by
Richter.
We further conclude Appellants have not met the burden of showing
the Examiner erred in finding Richter discloses a virtual memory address is
input and a host virtual memory address is output. Therefore, we conclude
Appellants have not met the burden of showing the Examiner erred in
rejecting claim 38 for anticipation by Richter and claims 37 and 40 for
obviousness over Richter and Bodin.
We conclude Appellants have not met the burden of showing the
Examiner erred in finding Egolf discloses a page table that shows mapping
between a target system virtual memory address to a host virtual memory
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address. Therefore, we conclude Appellants have not met the burden of
showing the Examiner erred in rejecting claims 22, 24 and 25 for
anticipation by Egolf and claims 23 and 26-31 for obviousness over Egolf
and Bugnion.

NEW GROUND OF REJECTION
35 U.S.C. § 103
Using our authority under 37 C.F.R. § 41.50(b), we reject claims 1
and 21 under 35 U.S.C. § 103(a) as being unpatentable over Noel and Egolf
and claims 16, 32, 36, and 39 under 35 U.S.C. § 103(a) as being
unpatentable over Richter and Egolf.
Noel, Egolf, and Richter are within the field of emulation and virtual
machines (FF 5, FF 6, and FF 14).

Claims 1 and 21
Noel describes a process that translates virtual addresses to physical
addresses using page tables (FF 7). Egolf describes mapping a target virtual
address to a host virtual address (FF 16). Egolf further describes an
improvement on using page tables to perform the mapping (FF 18). We find
Noel and Egolf are both directed to the field of emulation, virtual machines
and addressing. We conclude a person of ordinary skill in the art would
have been motivated to incorporate the page table of Noel that maps virtual
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to physical addresses into the system described in Egolf that maps a target
virtual address to a host virtual address.
We find the “wherein” clauses merely state an intended result of
emulation of one processor on another. Specifically, the wherein clauses
recite that a target processor is oblivious (claim 1) and the emulation of the
target system’s memory addressing is treated as an application running on
the host multiprocessor system (claim 21). Accordingly, we conclude the
wherein clauses do not add any structure but rather simply express the
intended result of emulation.
Therefore, we reject claims 1 and 21 under 35 U.S.C. § 103(a) as
being unpatentable over Noel and Egolf. As Appellants have not argued the
elements recited in dependent claims 2-15 are not taught or suggested by the
cited references including IBM, Onodera and Richter, we additionally reject
claims 2-4, 6-8, and 15 under 35 U.S.C. § 103(a) as being obvious over Noel
and Egolf; claim 5 under 35 U.S.C. § 103(a) as being obvious over Noel,
IBM, and Egolf; claims 9-13 under 35 U.S.C. § 103(a) as being obvious over
Noel, Onodera, and Egolf; and claim 14 under 35 U.S.C. § 103(a) as being
obvious over Noel, Onodera, Richter, and Egolf.

Claim 39
Claim 39 is rejected under 35 U.S.C. § 112, second paragraph, as
being indefinite. Claim 39 reads “with said miss determined in said LLT,
obtaining a lock for the page table.” Page table has no antecedent basis and
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thus, it is unclear what structure Appellants are actually claiming. For this
reason, we reject claim 39 under 35 U.S.C. § 112 using our authority under
37 C.F.R. § 41.50(b). Consideration of a prior art rejection of claim 39
cannot be made because the subject matter encompassed by the claims on
appeal must be reasonably understood without resort to speculation.
Presently, speculation and conjecture must be utilized by us and by the
artisan inasmuch as the claims on appeal do not adequately reflect what the
disclosed invention is. Note In re Steele, 305 F.2d 859, 862 (CCPA 1962)
(A prior art rejection cannot be sustained if the hypothetical person of
ordinary skill in the art would have to make speculative assumptions
concerning the meaning of claim language.); Note also In re Wilson, 424
F.2d 1382, 1385 (CCPA 1970).

DECISION
The Examiner’s rejection of claims 21 and 32-37 under
35 U.S.C. § 101(a) as being directed to non-statutory subject matter is
reversed.
The Examiner’s rejection of claims 22-31 under 35 U.S.C. § 101(a) as
being directed to non-statutory subject matter is affirmed.
The Examiner’s rejection of claims 1-4, 6-8, and 15 under
35 U.S.C. § 102(b) as being anticipated by Noel is reversed.
The Examiner’s rejection of claims 16, 17, and 20 under
35 U.S.C. § 102(b) as being anticipated by Richter is reversed.
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The Examiner’s rejection of claims 32-35 under 35 U.S.C. § 102(b) as
being anticipated by Richter is affirmed.
The Examiner’s rejection of claim 36 under 35 U.S.C. § 102(b) as
being anticipated by Richter is reversed.
The Examiner’s rejection of claim 38 under 35 U.S.C. § 102(b) as
being anticipated by Richter is affirmed.
The Examiner’s rejection of claim 39 under 35 U.S.C. § 102(b) as
being anticipated by Richter is affirmed.
The Examiner’s rejection of claims 22, 24, and 25 under
35 U.S.C. § 102(e) as being anticipated by Egolf is affirmed.
The Examiner’s rejection of claim 5 under 35 U.S.C. § 103(a) as
being unpatentable over Noel and IBM is reversed.
The Examiner’s rejection of claims 9-13 under 35 U.S.C. § 103(a) as
being unpatentable over Noel and Onodera is reversed.
The Examiner’s rejection of claims 14 and 21 under
35 U.S.C. § 103(a) as being unpatentable over Noel, Onodera, and Richter is
reversed.
The Examiner’s rejection of claims 18 and 19 under
35 U.S.C. § 103(a) as being unpatentable over Richter and Bodin is
reversed.
The Examiner’s rejection of claims 37 and 40 under
35 U.S.C. § 103(a) as being unpatentable over Richter and Bodin is
affirmed.
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The Examiner’s rejection of claims 23 and 26-31 under
35 U.S.C. § 103(a) as being unpatentable over Egolf and Bugnion is
affirmed.
In addition to affirming the Examiner's rejections of one or more
claims, this decision contains new grounds of rejection pursuant to 37 C.F.R.
§ 41.50(b) (2007). 37 C.F.R. § 41.50(b) provides “[a] new ground of
rejection pursuant to this paragraph shall not be considered final for judicial
review.”
37 C.F.R. § 41.50(b) also provides that Appellant, WITHIN TWO
MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new grounds of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. Submit an appropriate amendment of the claims
so rejected or new evidence relating to the claims so rejected, or both,
and have the matter reconsidered by the Examiner, in which event the
proceeding will be remanded to the Examiner.…

(2) Request rehearing. Request that the proceeding be reheard under
§ 41.52 by the Board upon the same record.…

Should Appellants elect to prosecute further before the Examiner
pursuant to 37 C.F.R. § 41.50(b)(1), in order to preserve the right to seek
review under 35 U.S.C. §§ 141 or 145 with respect to the affirmed rejection,
the effective date of the affirmance is deferred until conclusion of the
prosecution before the Examiner unless, as a mere incident to the limited
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prosecution, the affirmed rejection is overcome.
If Appellants elect prosecution before the Examiner and this does not
result in allowance of the application, abandonment or a second appeal, this
case should be returned to the Board of Patent Appeals and Interferences for
final action on the affirmed rejection, including any timely request for
rehearing thereof.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2007).

AFFIRMED-IN-PART
37 C.F.R. § 41.50(b)

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