Ex Parte Al-Dahle et alDownload PDFPatent Trial and Appeal BoardDec 22, 201612792291 (P.T.A.B. Dec. 22, 2016) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/792,291 06/02/2010 Ahmad Al-Dahle P9178US1 / APPL:0202 4440 73576 7590 APPLE INC. - Fletcher c/o Fletcher Yoder, PC P.O. Box 692289 Houston, TX 77269-2289 12/27/2016 EXAMINER MISERY, RAM A ART UNIT PAPER NUMBER 2691 NOTIFICATION DATE DELIVERY MODE 12/27/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docket@fyiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte AHMAD AL-DAHLE and WEI H. YAO Appeal 2016-001835 Application 12/792,2911 Technology Center 2600 Before JOHNNY A. KUMAR, JOHN P. PINKERTON, and MATTHEW J. McNEILL, Administrative Patent Judges. McNEILL, Administrative Patent Judge. DECISION ON APPEAL Appellants appeal under 35 U.S.C. § 134(a) from the Examiner’s rejection of claims 1—4 and 6-19. Claims 5 and 20 have been canceled. We have jurisdiction under 35 U.S.C. § 6(b). We affirm. 1 According to Appellants, the real party in interest is Apple Inc. App. Br. 2. Appeal 2016-001835 Application 12/792,291 STATEMENT OF THE CASE Introduction Appellants’ application relates to techniques for reducing parasitic capacitance in electronic displays. Spec. ^ 1. Claim 1 is illustrative of the claimed subject matter on appeal and reads as follows: 1. A display panel comprising: a pixel that includes: a pixel electrode; a common electrode; a transistor having a drain coupled to the pixel electrode, a source coupled to a data line, and a gate coupled to a gate line, wherein the transistor is configured to pass a data signal from the data line to the pixel electrode upon receipt of an activation signal from the gate line; a common voltage line configured to supply a common voltage to the common electrode; and a shielding conductor interposed between the pixel electrode and the gate line, wherein the shielding conductor is configured to shield the pixel electrode from a parasitic capacitance with the gate line by causing a parasitic capacitance between the gate line and the shielding conductor instead of between the gate line and the pixel electrode, wherein the shielding conductor is supplied a shielding voltage higher than that of the activation signal supplied by the gate line. The Examiner’s Rejections Claims 3 and 4 stand rejected under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter regarded as the invention. Final Act. 2. 2 Appeal 2016-001835 Application 12/792,291 Claims 1 and 2 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Shin (US 2006/0215071 Al; Sep. 28, 2006) and Sasaki (US 2003/0146890 Al; Aug. 7, 2003). Final Act. 3—4. The Examiner adds Lee (US 5,949,396; Sept. 7, 1999) (“Lee ’396”) to reject claims 6 and 7 (Final Act. 5-6); Hayashi (US 6,927,752 B2; Aug. 9, 2005) to reject claims 11-13 (Final Act. 10-12); Hayashi and Jang (US 2005/0140617 Al; June 30, 2005) to reject claim 14 (Final Act. 12-13); Hayashi and Lee ’396 to reject claim 15 (Final Act. 13-14); and Hayashi and Lee et al. (US 2007/0035499 Al; Feb. 15, 2007) (“Lee ’499”) to reject claim 19 (Final Act. 14-15). Claims 8-10 and 16-18 stand rejected under 35 U.S.C. § 103(a) as unpatentable over Shin, Hayashi, and Lee ’499. Final Act. 6-10. ANALYSIS Claim 1 Appellants argue the Examiner erred in rejecting claim 1 because the combination of Shin and Sasaki does not teach or suggest a “shielding voltage higher than that of an activation signal supplied by a gate line.” App. Br. 10-12, Reply Br. 2-3. In particular, Appellants argue the Examiner admits Shin does not teach or suggest this limitation. App. Br. 10 (citing Final Act. 4). Appellants argue Shin does not teach a shielding voltage or any type of voltage higher than the activation line. App. Br. 10- 11. Appellants argue Sasaki teaches optimum levels of voltages, including the relationship between a gate voltage, a grayscale voltage, and a common voltage, but is “utterly silent with respect to any such teaching of a shielding conductor.” App. Br. 11. Appellants have not persuaded us of Examiner error. The Examiner finds, and we agree, Shin teaches a shielding conductor 88 that is located 3 Appeal 2016-001835 Application 12/792,291 between a pixel electrode 190 and the gate line. Ans. 16 (citing Shin 81- 83). Shin teaches a “common voltage” applied to the shielding conductor, resulting in a reduction of voltage distortion on the pixel electrode. Ans. 17 (citing Shin 79-80). Appellants’ argue the voltage applied to Shin’s shielding electrode is not the “shielding voltage” recited in claim 1 because Shin refers to this voltage as a “common voltage,” another term recited in claim 1. App. Br. 10-11. However, as noted by the Examiner, “shielding voltage” is not defined in claim 1 or in Appellants’ Specification. Ans. 18. Under the broadest reasonable interpretation of the claim, the “shielding voltage” is the voltage supplied to the shielding conductor, and this shielding voltage must be higher than that of the activation signal supplied by the gate line. However, nothing in the claims or Appellants’ Specification precludes the shielding voltage and common voltage from being supplied by a single source. Accordingly, we are not persuaded the Examiner erred in finding Shin teaches a “shielding voltage” by teaching a common voltage applied to a shielding conductor. See Ans. 16-17 (citing Shin 79-83). Although Appellants are correct that Shin does not explicitly teach the shielding voltage being higher than the activation signal (see App. Br. 10), the Examiner relies on Sasaki for this limitation. Final Act. 4 (citing Sasaki, Fig. 6, ^ 108). Appellants argue Sasaki fails to teach a shielding voltage, but the Examiner relies on Shin for this limitation, as noted above. Final Act. 3- 4. Appellants’ arguments are unpersuasive because they are directed to the references individually instead of the combination proposed by the Examiner. One cannot show nonobviousness by attacking references individually when the rejection is based on a combination of references. In re Merck & Co. Inc., 800 F.2d 1091, 1097 (Fed. Cir. 1986); see also In re 4 Appeal 2016-001835 Application 12/792,291 Keller, 642 F.2d 413, 425 (CCPA 1981). The Examiner explained that the combination of Shin and Sasaki, not either reference alone, teaches this limitation. Accordingly, on this record, we sustain the rejection of claim 1. We also sustain the rejections of claims 2-7, which were not argued separately. See App. Br. 9-17. Claim 8 Claim 8 recites: A system comprising: a processor configured to generate display signals; a display configured to generate pixel activation signals, pixel data signals, and common voltage signals based on the display signals, wherein the display is configured to provide the pixel activation signals, the pixel data signals, and the common voltage signals to pixels of the display via signal conductors, and wherein the pixels of the display comprise shielding conductors of equal number of a subset of the signal conductors interposed between pixel electrodes of the pixels and the subset of the signal conductors to shield the pixel electrodes from voltage changes due to parasitic capacitances between the signal conductors and the pixel electrodes when the pixel activation signals or the pixel data signals are provided to the pixels, wherein the display is configured to supply low frequency alternating current voltage signals to the shielding conductors. Appellants argue the Examiner erred in rejecting claim 8 because the Examiner admits that neither Shin nor Hayashi teaches or suggests a “shielding conductor configured to carry a low frequency alternating current voltage,” and Lee ’499 does not cure this deficiency. App. Br. 13-14, Reply 5 Appeal 2016-001835 Application 12/792,291 Br. 4-5. In particular, Appellants argue Lee ’499 teaches driving a common voltage signal high and low when a gate signal is driven high and low, but does not teach any shielding conductor. App. Br. 13-14. Appellants have not persuaded us of Examiner error. As discussed above, the Examiner finds, and we agree, Shin teaches applying a shielding voltage to a shielding conductor. Ans. 16-17 (citing Shin]fl| 79-83). As Appellants acknowledge, Lee ’499 teaches driving a voltage signal high and low when a gate signal is driven high and low, respectively. See App. Br. 13-14 (citing Lee ’499 ^ 28). In other words, Lee ’499 teaches a low frequency alternating current voltage signal. We agree with the Examiner that an ordinarily skilled artisan would have been motivated to combine Lee’s low frequency alternating current voltage signal with Shin’s shielding voltage, which results in the claimed feature, final Act. 8, Ans. 20-21. Appellants’ argument to the contrary is unpersuasive because it focuses on the failure of Lee ’499 to teach or suggest a shielding voltage while ignoring the teachings of Shin and Hayashi. One cannot show nonobviousness by attacking references individually when the rejection is based on a combination of references. In re Merck & Co. Inc., 800 L.2d 1091, 1097 (Led. Cir. 1986); see also In re Keller, 642 L.2d 413, 425 (CCPA 1981). The Examiner explained that the combination of Lee ’499, Shin, and Hayashi, not any reference alone, teaches this limitation. Accordingly, we sustain the rejection of claim 8. Appellants argue the patentability of independent claim 16 for the same reasons as claim 8. App. Br. 13-14. We, therefore, also sustain the rejection of claim 16 for the same reasons. We also sustain the rejections of claims 9 and 17-19, which were not argued separately from their respective independent claims. See App. Br. 13-17. 6 Appeal 2016-001835 Application 12/792,291 Claim 10 Claim 10 recites “[t]he system of claim 8, wherein the shielding conductors are substantially equidistant between the subset of the signal conductors and the pixel electrodes.” Appellants argue the Examiner erred in rejecting claim 10 because Shin, Hayashi, and Lee ’499 do not teach or suggest shielding conductors positioned between pixel electrodes and signal conductors. App. Br. 14-15. In particular, Appellants argue Shin teaches, at best, a shielding electrode 88 adjacent to a subpixel electrode 190a that overlaps data lines 171a and 171b, instead of being located between the pixel electrodes and data lines. App. Br. 14. Appellants argue Hayashi teaches capacity lines 18a and shielding wiring 18b shield against parasitic capacity, but fails to teach shielding conductors interposed between pixel electrodes and signal conductors. App. Br. 15. Appellants also argue Lee ’499 does not teach a shielding conductor and, therefore, does not teach the disputed limitation. Id. Appellants have not persuaded us of Examiner error. The Examiner finds, and we agree, Shin teaches a top-down two-dimensional view of a pixel where the left edge of the shielding conductor 88 is interposed substantially equidistant between electrode 171a on the left (a “signal conductor”) and electrode 190 on the right (a “pixel electrode”). Ans. 22 (citing Shin Fig. 4, Fig. 7A); see also Shin Fig. 6. Appellants have not identified persuasive evidence in the record to rebut the Examiner’s findings. Accordingly, we sustain the rejection of dependent claim 10. Claim 11 Claim 11 recites: A display panel comprising: 7 Appeal 2016-001835 Application 12/792,291 a plurality of pixel electrodes configured to store data signals; a plurality of data signal carriers configured to carry the data signals; a plurality of common electrodes configured to be supplied with common voltage signals; a plurality of transistors corresponding to the plurality of pixel electrodes and coupled thereto, wherein the plurality of transistors is configured to pass the data signals from the plurality of data signal carriers to the plurality of pixel electrodes when activation signals are applied to gates of the plurality of transistors; a plurality of gate lines configured to provide the activation signals to the gates of the plurality of transistors; and a plurality of shielding lines each corresponding to a different one the plurality of gate lines, wherein the plurality of shielding lines are interposed between subsets of the plurality of pixel electrodes and the gate lines, wherein the plurality of shielding lines is configured to shield the plurality of pixel electrodes from parasitic capacitances from the plurality of gate lines, wherein the plurality of shielding lines are configured to carry a shielding voltage higher than that of the activation signals applied to the gates of the plurality of transistors. Appellants argue the Examiner erred in rejecting claim 11 for the same reasons as claim 1. App. Br. 10-12. We disagree for the reasons set forth above with respect to claim 1. Appellants also argue the Examiner erred in rejecting claim 11 because Hayashi does not teach or suggest “shielding lines [] configured to carry a shielding voltage higher than that of the activation signals applied to the gates of the plurality of transistors.” App. Br. 16, Reply Br. 5-6. In particular, Appellants argue that although 8 Appeal 2016-001835 Application 12/792,291 Hayashi teaches a shielding wire 18 included within the gap between pixel electrodes 23, Hayashi is silent regarding shielding wire 18 carrying a shielding voltage higher than that of the activation signals applied to the gates. Id. Appellants argue it is unclear that “any such voltage” is applied to shielding wire 18, “much less a shielding voltage” as recited by claim 11. Appellants have not persuaded us of Examiner error. The Examiner does not rely on Hayashi for the disputed limitation. Ans. 23. Instead, the Examiner relies on the combination of Shin and Sasaki, as set forth in the rejection of claim 1. Id. As explained above with respect to claim 1, Appellants have not persuaded us of Examiner error with respect to the combination of Shin and Sasaki teaching a shielding voltage higher than that of the activation signal supplied by the gate line. Accordingly, we are not persuaded the Examiner erred in rejecting claim 11. We, therefore, sustain the rejection of claim 11 and dependent claims 12-15, which were not argued separately. Claims 3 and 4—Indefiniteness In the Final Action, the Examiner rejected claims 3 and 4 under 35 U.S.C. § 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter regarded as the invention. Final Act. 2. Appellants have not presented arguments that the Examiner erred in rejecting claims 3 and 4 as indefinite. Arguments not made are deemed waived. See 37 CFR § 41.37(c)(l)(iv). Accordingly, we summarily affirm the rejection of claims 3 and 4 as indefinite under 35 U.S.C. § 112(b). DECISION We affirm the decision of the Examiner rejecting claims and 6- 19. 9 Appeal 2016-001835 Application 12/792,291 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1). See 37 C.F.R. § 1.136(a)(l)(iv). AFFIRMED 10 Copy with citationCopy as parenthetical citation