Ex Parte Aipperspach et al

Board of Patent Appeals and Interferences

Jul 30, 2012

11845829 (B.P.A.I. Jul. 30, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/845,829 08/28/2007 Anthony Gus Aipperspach ROC920070234US1 9374
47542 7590 07/31/2012
IBM CORPORATION (ROC)
3605 HIGHWAY 52 NORTH, DEPT 917
ROCHESTER, MN 55901-7829
EXAMINER
KERVEROS, DEMETRIOS C
ART UNIT PAPER NUMBER
2117
MAIL DATE DELIVERY MODE
07/31/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte ANTHONY GUS AIPPERSPACH,
LOUIS BERNARD BUSHARD,
and DENNIS THOMAS COX
____________________

Appeal 2010-003008
Application 11/845,829
Technology Center 2100
____________________

Before ALLEN R. MacDONALD, KRISTEN L. DROESCH,
and BRYAN F. MOORE, Administrative Patent Judges.

MOORE, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2010-003008
Application 11/845,829

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Appellants appeal under 35 U.S.C. § 134(a) (2002) from a final
rejection of claims 1-6, 8-13, and 15-20. We have jurisdiction under 35
U.S.C. § 6(b). Claims 7 and 14 have been cancelled.
We AFFIRM.
Introduction
According to Appellants, the invention relates to built-in self testing
of integrated circuits. (Abstract).

STATEMENT OF THE CASE
Exemplary Claim
Claim 1 is an exemplary claim and is reproduced below:
1. A method for performing on-chip testing of an integrated
circuit including a first combinatorial logic region, a second
combinatorial logic region and a logical built-in self test
(LBIST) circuit, said method comprising:
stimulating the first combinatorial logic region within the
integrated circuit with a test pattern under control of a first
clock signal;
concurrently stimulating the second combinatorial logic
region within the integrated circuit with the test pattern under
control of a different second clock signal; and
interleaving assertion of the first clock signal and
assertion of the second clock signal such that the first and
second combinatorial logic regions load bits of the test pattern
from a scan chain in different cycles.

Prior Art
Nadeau-Dostie US 6,442,722 B1 Aug. 27, 2002

Appeal 2010-003008
Application 11/845,829

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Rejections
Claims 1-6, 8-13, and 15-20 stand rejected under 35 U.S.C. § 112,
first paragraph as failing to comply with the written description requirement.
(Ans. 3). Claims 1-6, 8-13, and 15-20 stand rejected under
35 U.S.C. § 102(b) as being anticipated by Nadeau-Dostie. (Ans. 3-5).

We select claim 1 as representative to decide this appeal for the group
consisting of claims 1-6, 8-13, and 15-20.37 C.F.R. § 41.37(c)(1)(vii).

ISSUES
35 U.S.C. § 112: claims 1-6, 8-13, and 15-20
Appellants assert that the Specification provides written description of
the term interleaving in claim 1 by its description of the terms “offset” and
“staggering.” (Br. 8-11).
35 U.S.C. § 102(b): claims 1-6, 8-13, and 15-20
Appellants assert that “Nadeau-Dostie clearly fails to identically
disclose the ‘interleaving’ step of exemplary Claim 1 as required to support
a rejection for anticipation under 35 U.S.C. § 102.” (Br. 12).
Issues:
1. Has the Examiner erred in rejecting claims 1-6, 8-13, and 15-20
under 35 U.S.C. § 112, first paragraph, on the basis that the
Specification does not provide adequate written description for the
limitation “interleaving assertion of the first clock signal and
assertion of the second clock signal”?
Appeal 2010-003008
Application 11/845,829

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2. Has the Examiner erred in rejecting claims 1-6, 8-13, and 15-20
under 35 U.S.C. § 102(b) because the cited reference does not
disclose “interleaving assertion of the first clock signal and
assertion of the second clock signal”?1

ANALYSIS
35 U.S.C. § 112, first paragraph: claims 1-6, 8-13, and 15-20
The originally-filed Specification's recitation of “offsetting” and
“staggering” of test sequences (2007-11-16 Spec. ¶¶ [24]-[25]) does not
provide adequate support for the later-added claim language, “interleaving
assertion of the first clock signal and assertion of the second clock signal.”
The Examiner states that “[a]ccording to Wikipedia, interleaving in
computer science is a way to arrange data in a non-contiguous way to
increase performance.” (Ans. 7). Further, without citing a dictionary, the
Examiner states that “[t]he term multiplexing is sometimes used to refer to
the interleaving of digital signal data.” (Id.). We find that, as used in the
context of computer science, interleaving means acting on items alternately.2
We find that while offsetting may shift the start of one test sequence from
the start of another test sequence it does not imply that the assertion of the
first clock signal is alternating with the assertion of the second clock signal.
(Ans. 6-7). For example, the specification states that “[m]ultiple clocks are

1 Appellants make additional arguments regarding claims 2-6, 9-13, and 16-
20. (Br. 12-13). We do not reach these additional issues since this issue is
dispositive of the case.
2 Collins English Dictionary, © HarperCollins Publisher (2000) (retrieved
from http://www.xreferplus.com/entry/hcdcomp/interleaving) (last visited
July 23, 2012).
Appeal 2010-003008
Application 11/845,829

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not needed to offset the test sequence in one region of logic from another
region of logic.” (2007-11-16 Spec. ¶ [23]). Additionally, the specification
discloses a “single clock signal.” Id. Thus, the Specification does not
disclose “interleaving assertion of the first clock signal and assertion of the
second clock signal.” Accordingly, we sustain the Examiner's rejection of
claims 1-6, 8-13, and 15-20 under 35 U.S.C. § 112, first paragraph.
35 U.S.C. § 102(b): claims 1-6, 8-13, and 15-20
Claim 1 requires “interleaving” of the assertions of first and second
clock signals. As pointed out above, interleaving means alternating.
Nadeau-Dostie discloses a first clock BistCLK and second clock ClockHS,
which has a frequency 8 times that of BistCLK. (Br. 12) As Appellants
point out, “Figure 4 of Nadeau-Dostie . . . teaches that BistCLK and
ClockHS are asserted at the same time, that is, that the logic-high state of
Clock HS that launches the scan capture in the high speed clock domain is
asserted while the logic-high state of BistCLK that launches the scan capture
for the low speed clock domain is asserted.” (Id.) Therefore, since the
clocks have two different clock speeds the assertion of the two clocks does
not alternate.
It therefore is our opinion that the subject matter of claim 1 does not
read on the Nadeau-Dostie disclosure, and thus is not anticipated by this
reference. The rejection of claim 1 and, it follows, of dependent claims 2-6,
8-13, and 15-20, therefore is not sustained.

Appeal 2010-003008
Application 11/845,829

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DECISION
The Examiner’s rejection of claims 1-6, 8-13, and 15-20 under
35 U.S.C. § 112, first paragraph as failing to comply with the written
description requirement is affirmed. The Examiner’s rejection of claims 1-6,
8-13, and 15-20 under 35 U.S.C. § 102(b) is reversed.

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv) (2010).

AFFIRMED

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