Ex Parte AhlquistDownload PDFPatent Trial and Appeal BoardDec 20, 201612412829 (P.T.A.B. Dec. 20, 2016) Copy Citation United States Patent and Trademark Office UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O.Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 12/412,829 03/27/2009 Brent Ahlquist P067 (88231.0167) 7835 135286 7590 12/22/2016 Holland & Hart LLP/Micron P.O. Box 11583 Salt Lake City, UT 84147 EXAMINER PATEL, JIGAR P ART UNIT PAPER NUMBER 2114 NOTIFICATION DATE DELIVERY MODE 12/22/2016 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): patentdocket @ hollandhart. com micron @ hollandhart. com sesoares @ hollandhart. com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte BRENT AHLQUIST Appeal 2016-002110 Application 12/412,829 Technology Center 2100 Before CAROLYN D. THOMAS, ERIC B. CHEN, and AARON W. MOORE, Administrative Patent Judges. THOMAS, Administrative Patent Judge. DECISION ON APPEAL Appellant seeks our review under 35 U.S.C. § 134(a) of the Examiner’s Final Rejection of claims 1—23, all the pending claims in the present application. See Claim Appendix. We have jurisdiction over the appeal under 35 U.S.C. § 6(b). We AFFIRM. The present invention relates generally to a control signal output pin that provides a control signal indicative of the memory interface control flow. See Abstract. Appeal 2016-002110 Application 12/412,829 Claim 1 is illustrative: 1. An apparatus comprising: a memory array including a plurality of non-volatile memory cells; and a dedicated output status pin operatively coupled to the memory array and configured to provide a status signal from the memory array wherein the status signal is capable of indicating at least a programming error based at least in part on timing of assertion or deassertion of the status signal relative to a write operation for the memory array. Appellant appeals the following rejections: Rl. Claims 1—3, 7, 8, 10, 12—17, and 21—23 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Lee (US 2008/0184002 Al, July 31, 2008) and Oshima (US 2007/0220216 Al, Sept. 20, 2007); R2. Claims 4—6, 18, and 19 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Lee, Oshima, and Majewski (US 2008/0276132 Al, Nov. 6, 2008); R3. Claims 9 and 20 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Lee, Oshima, and Kim (US 2008/0049505 Al, Feb. 28, 2008) ; and R4. Claim 11 is rejected under 35 U.S.C. § 103(a) as being unpatentable over Lee, Oshima, and Kim (US 2009/0187794 Al, July 23, 2009) . ANALYSIS Claims 1—23 Issue: Did the Examiner err in finding that Lee and Oshima collectively teach or suggest a dedicated output status pin, as set forth in claim 1? 2 Appeal 2016-002110 Application 12/412,829 Appellant contends that “Lee does not teach or disclose a dedicated output status pin. The ‘write enable (/WE)’ of Lee that is relied upon by the Office Action is an input signal” (App. Br. 12). Appellant further contends that “Oshima’s status signal ST is relative to the ‘status-read command’ at time t2 and not ‘relative to a write operation’ as recited in Claim 1” (id. at 13). Appellant also contends that “Oshima’s status signal ST is carried in the signal ‘DATA’ . . . not a ‘dedicated output status pin.’ . . . An output pin cannot be ‘dedicated’ if it is part of a bus” (id. at 13). The Examiner finds that “Oshima explicitly discloses [0048] the memory card that has received the status-read command outputs a status signal ST at time t3 [and] [t]he status signal ST (dedicated output status pin) indicates whether the write process has been successfully performed” (Ans. 2—3). We agree with the Examiner. We refer to, rely on, and adopt the Examiner’s findings and conclusions set forth in the Answer. Our discussions here will be limited to the following points of emphasis. As for Appellant’s contention that Lee does not teach a dedicated output status pin (App. Br. 12), we note that the Examiner is also relying on Oshima to teach this feature (see Final Act. 3 and Ans. 2—3). For instance, Oshima discloses: At time t2, a status-read command “70/?” is input, as signal “DATA”, to the memory card 10. Status-reading is therefore performed to determine whether data was successfully written or not in the memory card 10. The memory card 10 that has received the status-read command outputs a status signal ST at time t3. The status signal ST indicates whether the write process has been successfully performed. 3 Appeal 2016-002110 Application 12/412,829 (Oshima 148). In other words, Oshima discloses that status-reading is performed, relative to a write operation, to determine whether the write process was successful. Oshima outputs a status signal ST to indicate the success or not. Thus, we find unavailing Appellant’s above-noted contention that Oshima’s status signal ST is not relative to a write operation given that its purpose is to indicate whether the write process has been successfully performed. Regarding Appellant’s contention that “an output pin cannot be ‘dedicated’ if it is part of a bus” (App. Br. 13), the Examiner finds, and we agree, “[assuming, for argument sake, that the status signal ST is carried on the DATA signal [(although not explicitly indicated in paragraph [0048] as being carried on the DATA signal)], the status signal ST would always be carried in the signal ‘DATA’ ... a ‘dedicated’ output status pin” (Ans. 3—4). The Examiner further finds, and we agree, that “[A]ppellant has failed to disclose or define the word ‘dedicated’ in the specification. . . . [A] general definition of the word is ‘allocated/devoted for a particular service or purpose’” {id. at 4). Here, Oshima states that the status signal ST indicates, i.e., is devoted to showing, whether the write process has been successfully performed. We further emphasize that the claimed term “dedicated output status pin” as written does not necessarily require that the same pin be used each time, nor that this pin be separate from other pins, only that there exist an output pin which indicates the status. Finally, Appellant contends that “[i]f the write enable signal of Lee were to be changed from a control signal (an input to the memory) to an output signal, then Lee would be rendered inoperable” (App. Br. 13). We note that the aforementioned modification, i.e., changing Lee’s input signal 4 Appeal 2016-002110 Application 12/412,829 to an output signal, was never proffered by the Examiner (see Final Act. 3). Instead, the Examiner merely noted that “[o]ne would have been motivated to provide [(i.e., add)] a status signal from the memory because it allows notifying the host apparatus of a failure of a data write” (id. ). As such, we find Appellant’s contention unavailing given the Examiner’s lack of a finding pertaining to changing the input signal. Accordingly, we sustain the Examiner’s rejection of claim 1. Appellant’s arguments regarding the Examiner’s rejection of independent claims 12 and 16 rely on the same arguments as for claim 1, and Appellant does not argue separate patentability for the dependent claims. See App. Br. 10—15. We, therefore, also sustain the Examiner’s rejection of claims 2—23. DECISION We affirm the Examiner’s § 103(a) rejections Rl—R4 of claims 1—23. No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(l)(iv). AFFIRMED 5 Copy with citationCopy as parenthetical citation