Ex Parte Aggarwal et al

Patent Trials and Appeals Board

Jun 26, 2019

14604660 - (D) (P.T.A.B. Jun. 26, 2019)

UNITED STA TES p A TENT AND TRADEMARK OFFICE
APPLICATION NO. FILING DATE
14/604,660 01/23/2015
23494 7590 06/28/2019
TEXAS INSTRUMENTS IN CORPORA TED
PO BOX 655474, MIS 3999
DALLAS, TX 75265
FIRST NAMED INVENTOR
Rajni J. Aggarwal
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www .uspto.gov
ATTORNEY DOCKET NO. CONFIRMATION NO.
TI-72292 2350
EXAMINER
HOANG, TUAN A
ART UNIT PAPER NUMBER
2822
NOTIFICATION DATE DELIVERY MODE
06/28/2019 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
uspto@ti.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Exparte RAJNI J. AGGARWAL,
JOHN P. CAMPBELL, KAIPING LIU, and WEIDONG TIAN
Appeal2018-004723
Application 14/604,660
Technology Center 2800
Before GEORGE C. BEST, N. WHITNEY WILSON, and
WESLEY B. DERRICK, Administrative Patent Judges.
WILSON, Administrative Patent Judge.
DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner's
December 12, 2016 decision finally rejecting claims 11-13 and 16-25,
which constitute all the claims pending in this application. Claim 14 has
been withdrawn. We have jurisdiction over the appeal under 35 U.S.C.
§ 6(b).
We affirm.
1 Appellant is the Applicant, Texas Instruments Incorporated, which is also
identified as the real party in interest (Appeal Br. 3).
Appeal2018-004723
Application 14/604,660
CLAIMED SUBJECT MATTER
Appellant's disclosure is directed to a method for forming an
integrated circuit (Spec. ,r 4). The claimed processes entail a number of
distinct steps, as set forth in the claims, details of which are set forth in
representative independent claim 11, which is reproduced below from the
Claims Appendix of the Appeal Brief (emphasis added):
11. A method of forming an integrated circuit, comprising the
steps:
forming a first ILD layer;
forming a plurality of metal lines in the first ILD layer by
a copper damascene process so that the metal lines extend to a
top surface of the first ILD layer;
forming a dielectric layer on the first ILD layer, the
dielectric layer comprising an etch stop layer;
forming a resistor head mask over the dielectric layer
which exposes areas for resistor heads;
removing dielectric material from the dielectric layer in
the areas exposed by the resistor head mask to form resistor
head cavities in the dielectric layer;
removing the resistor head mask;
forming a layer of refractory metal over the dielectric
layer, extending into the resistor head cavities;
removing the layer of refractory metal from outside the
resistor head cavities to form resistor heads so that edges of the
resistor heads are substantially coplanar with the adjacent
dielectric layer, wherein the adjacent dielectric layer is less
than 200 nanometers thick;
forming a layer of resistor material less than 15
nanometers thick on the dielectric layer and the resistor heads;
patterning the layer of resistor material to form a thin
film resistor layer extending onto the resistor heads;
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Appeal2018-004723
Application 14/604,660
forming a second ILD layer over the dielectric layer and
the thin film resistor layer; and
forming a plurality of vias in the second ILD layer by a
copper damascene process so that instances of the vias make
direct connections to instances of the metal lines;
wherein electrical connections to the resistor heads are
made by interconnects selected from the group consisting of the
metal lines and the vias.
REJECTIONS
1. Claims 11, 13, and 17-20 are rejected under 35 U.S.C. § 103 as
unpatentable over Fujiwara2 in view of Nishimura. 3
2. Claim 16 is rejected under 35 U.S.C. § 103 as unpatentable
over Fujiwara in view of Nishimura, and further in view of Tsutsumi. 4
3. Claims 11 and 12 are rejected under 35 U.S.C. § 103 as
unpatentable over Privitera5 in view of Fujiwara and Nishimura.
4. Claims 21-25 are rejected under 35 U.S.C. § 103 as
unpatentable over Privitera in view of Fujiwara and Nishimura.
DISCUSSION
Details of the rejections are set forth at pages 2-9 of the Final Action.
Of particular interest for purposes of this appeal is the Examiner's finding
that Nishimura discloses a method of manufacturing a component which
2 Fujiwara et al., US 8,040,214 B2, issued October 18, 2011.
3 Nishimura et al., US 2014/0239445 Al, published August 28, 2014.
4 Tsutsumi et al., US 2013/0314165 Al, published November 28, 2013.
5 Privitera, US 8,427,273 B2, issued April 23, 2013.
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Appeal2018-004723
Application 14/604,660
serves a similar function to ( or even corresponds with) the claimed resistor
heads:
Nishimura discloses a method of manufacturing a thin film
resistor (Fig. 2A of Nishimura). As described in [0121], first,
contact holes (vias 33, 32 in Fig. 3A) are formed to the buried
wiring lines (14 & 15). Then a layer of refractory metal (Win
[O 121 J line 7) is deposited into the holes. The portion of
refractory metal outside the vias are removed by a planarization
process ([0121] lines 9-10). These plugs are resistor heads.
A layer of resistor material (metal thin film 51 in Fig. 3C) less
than 15 nanometers thick ([O 103 J lines 1-2) is deposited on the
plugs (32 & 33). The layer of resistor material is patterned (as
shown in Fig. 30 and [0124]) to form a thin film resistor layer
(31) extending onto the resistor heads.
(Final Act. 4, bold, unerline emphasis added). The Examiner determines
that it would have been obvious to form the thin-film resistor of Fujiwara (or
Privitera) using the methods of Nishimura to ensure the flatness of the thin-
film resistor.
Appellant contends that the combination of Fujiwara and Nishimura
does not teach or suggest "forming resistor heads so that edges of the resistor
heads are substantially coplanar with the adjacent dielectric layer, wherein
the adjacent dielectric layer is less than 200 nanometers thick" because
"[n]either Fujiwara nor Nishimura teach resistor heads at all" (Appeal Br. 4).
Appellant argues that both Fujiwara and Nishimura teach vias when a thick
interlayer insulating film is used between the resistor and lower metal lines,
"but there is no suggestion for using a via when only the thin dielectric 101 b
and 102 (FIG. 9 of Fujiwara) is used between the resistor and metal line"
(id.). Therefore, according to Appellant, there is not an adequate reason to
modify cavity 203a of Fujiwara to include the via of Nishimura as resistor
head" (id.).
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Appeal2018-004723
Application 14/604,660
Appellant further argues that the vias 32 and 33 ofNishinmra relied
on by the Examiner as corresponding to the claimed resistor heads (i.e.,
formed by a refractory metal and then removed so that the resistor head is
coplanar with the adjacent dielectric layer and less than 200 nm thick) are
not resistor heads because they do not form part of thin film resistor heads
(id. at 5).
Appellant's arguments are not persuasive, as they essentially are
arguing the references individually and do not address the combined
teachings of the art. Appellant admits that portions of the resistive elements
of Fujiwara and Privitera would be understood by a person of skill in the art
as "resistor heads" (Reply Br. 2). The Examiner finds that Nishimura
teaches a method of forming vias 3 2 and 3 3 6 ( depositing a layer of refractory
metal into a cavity and then removing the portions of the metal outside the
cavities) which a person of skill in the art would have found obvious to
employ in the formation of those resistor heads in Privitera and Fuijiwara, to
make a very thin layer.
Accordingly, having considered the arguments set forth by the
Appellant in the Appeal Brief and the Reply Brief, we determine that the
preponderance of the evidence of record supports the Examiner's
obviousness rejections.
6 For purposes of the rejection, we do not believe it material whether a
person of skill in the art would have considered Nishimura's vias 32 and 33
to be resistor heads, because Nishimura is relied upon by the Examiner as
teaching a method which a person of skill in the art would have incorporated
into making the structures described by Fujiwara and Privitera.
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Appeal2018-004723
Application 14/604,660
CONCLUSION
We AFFIRM the rejection of claims 11, 13, and 17-20 under
35 U.S.C. § 103 as unpatentable over Fujiwara in view of Nishimura.
We AFFIRM the rejection of claim 16 under 35 U.S.C. § 103 as
unpatentable over Fujiwara in view of Nishimura, and further in view of
Tsutsumi.
We AFFIRM the rejection of claims 11 and 12 under 35 U.S.C. § 103
as unpatentable over Privitera in view of Fujiwara and Nishimura.
We AFFIRM the rejection of claims 21-25 under 35 U.S.C. § 103 as
unpatentable over Privitera in view of Fujiwara and Nishimura.
No time period for taking any subsequent action in connection with
this appeal may be extended under 3 7 C.F .R. § 1.13 6( a )(1 )(iv).
AFFIRMED
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