Ex Parte Adams

Patent Trial and Appeal Board

Dec 17, 2013

11656640 (P.T.A.B. Dec. 17, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
11/656,640 01/23/2007 Phillip M. Adams 2456.2.10.1 2368
11653 7590 12/18/2013
PATE BAIRD, PLLC
36 West Fireclay
Murray, UT 84107
EXAMINER
HUISMAN, DAVID J
ART UNIT PAPER NUMBER
2183
MAIL DATE DELIVERY MODE
12/18/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte PHILLIP M. ADAMS
____________

Appeal 2011-007193
Application 11/656,640
Technology Center 2100
____________

Before ST. JOHN COURTENAY III, THU A. DANG, and
CARL W. WHITEHEAD JR., Administrative Patent Judges.

COURTENAY, Administrative Patent Judge.

DECISION ON APPEAL

Appeal 2011-007193
Application 11/656,640
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STATEMENT OF THE CASE
The Examiner finally rejected claims 21-40. Claims 1-20 were
canceled. (App. Br. 2). Appellant appeals therefrom under 35 U.S.C.
§ 134(a). We have jurisdiction under 35 U.S.C. § 6(b).
We affirm.
INVENTION
This invention relates to "systems and methods for extending the
instruction set of existing CPUs via software 'welding' techniques."
(Spec. 1). Claim 21, reproduced below, is representative of the claimed
subject matter:
21. A method for upgrading, exclusively through software, a
former generation processor to execute code written for later
generation processors of the same architectural family, the
method comprising:
identifying a processor architecture;
identifying a first release, corresponding to a first processor
having the processor architecture, comprising a first control unit
and a first execution unit, and supporting exclusively a first
plurality of operation codes;
identifying a second release, subsequent to the first release and
corresponding to a second processor having the processor
architecture, comprising a second control unit and a second
execution unit, and supporting exclusively a second plurality of
operation codes, the second plurality of operation codes
including the first plurality of operation codes and additional
operation codes;
receiving, by the first control unit a stream of instructions
comprising a first operation code, selected from the first
plurality of operation codes, and a second operation code
selected from the additional operation codes;
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recognizing, by the first control unit, the first operation code as
specifying a first instruction native to the first execution unit;
executing, by the first execution unit, the first instruction;
[a] recognizing, by the first control unit, the second operation
code as an unsupported operation code, unsupported by the
first execution unit;
[b] substituting, by the first control unit, in response to
recognizing the second operation code, one or more operation
codes selected exclusively from the first plurality of operation
codes and effective to provide at least one instruction
executable by the first execution unit, in place of the second
operation code;
[c] executing, by the first execution unit, the at least one
instruction.
(Disputed limitations emphasized, some elements lettered).
REFERENCES
The prior art relied upon by the Examiner as evidence in rejecting the
claims on appeal is:
Lee
Spear
US 4,763,242
US 5,367,658
Aug. 9, 1988
Nov. 22, 1994
Experts Exchange, "mmx emulator ... " (December 1999),
http://www.experts-exchange.com/Hardware/Misc/Q_10249692.html.

REJECTIONS
R1. Claims 21-24, 30-34, and 40 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over the combined teachings and suggestions
of Lee and Experts Exchange.
R2. Claims 25-27 and 34-37 stand rejected under 35 U.S.C. § 103(a)
as being unpatentable over the combined teachings and suggestions of Lee,
Experts Exchange, and Official Notice taken by the Examiner.
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R3. Claims 28, 29, 38, and 39 stand rejected under 35 U.S.C.
§ 103(a) as being unpatentable over the combined teachings and suggestions
of Lee, Experts Exchange, Official Notice taken by the Examiner, and Spear.

GROUPING OF CLAIMS
Based on Appellant's arguments, we decide the appeal of the
obviousness rejection R1 of claims 21-24, 30-34, and 40 on the basis of
representative claim 21. See 37 C.F.R. § 41.37(c)(1)(vii)(2004). 1
We address the rejections R2 and R3 separately, infra.

ANALYSIS
We disagree with Appellant's contentions regarding the Examiner's
obviousness rejections of the claims. We adopt as our own: (1) the findings
and reasons set forth by the Examiner in the action from which this appeal is
taken, and (2) the reasons set forth by the Examiner in the Answer in
response to arguments made in Appellant's Appeal Brief. (Ans. 12-18). We
highlight and address specific findings and arguments below:

1 Appellant filed a Notice of Appeal on Sept. 2, 2010. The date of filing the
Notice of Appeal determines which set of rules applies to an ex parte
appeal. If a Notice of Appeal is filed prior to January 23, 2012, then the
2004 version of the Board Rules last published in the 2011 edition of Title
37 of the Code of Federal Regulations (37 C.F.R. § 41.1) applies to the
appeal. See also MPEP 1220, Rev. 8, July 2010.

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R1. CLAIM 21
A.
Regarding the claim 21 limitation:
[b] substituting, by the first control unit, in response to
recognizing the second operation code, one or more operation
codes selected exclusively from the first plurality of operation
codes and effective to provide at least one instruction
executable by the first execution unit, in place of the second
operation code;
Appellant contends that the Lee's processor functional unit 117 ("first
execution unit") and control unit 115 ("first control unit") do not perform
Figure 5's steps 513, 517, 518, and 531 (claim 21's substitution limitation
[b]) because "something other that [sic] the main processor" performs
Figure 5's steps 513, 517, 518, and 531. (Emphasis added; Reply Br. 3; Lee
Fig. 5).
Appellant's contention is not persuasive. The Examiner finds, and we
agree, that Lee would have taught or suggested that Lee's main processor
103, including the first control unit 115, performs the steps 513, 517, 518,
and 531 in Lee's Fig. 5 (the substituting limitation [b]) because Lee
describes the control unit 115 performs steps 513 (col. 7, ll. 1-2), 517 (col.
7, ll. 1-5), 518 (col. 7, ll. 13-15) and 531 (col. 7, ll. 41-45). (Ans. 4-5; 13-
15; Lee, Figs. 1, 5). For these reasons, on this record, we are not persuaded
of Examiner error.
B.
Regarding the claim 21 limitation [b], Appellant contends the
emulation function in Lee is not equivalent to the substituting limitation [b]
because "Lee's emulation codes are not associated with Lee's main
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processor. In contrast, the substituting function from claim 21 has to select
operation codes exclusively from the operation codes already associated
with the first processor." (Reply Br. 4-5).
Appellant's contentions are not persuasive at least because Appellant's
contentions are not commeasure with the broader scope of the claim.
Specifically, claim 21, including limitation [b], does not recite "select[ing]
operation codes exclusively from the operation codes already associated
with the first processor." (Reply Br. 5). For these reasons, on this record,
we are not persuaded of Examiner error.
C.
Regarding the claim 21 limitation [a] "recognizing, by the first control
unit, the second operation code as an unsupported operation code,
unsupported by the first execution unit," Appellant contends:
[T]he assist instructions in Lee should not be equated with the
unsupported code from the Application. . . . Lee describes
assist instructions as instructions that are directed toward a
specific, "appropriate emulation code" so the assist instruction
can be executed. See, Lee, col. 7, lines 46-49.
(Reply Br. 5).
Appellant's contention is not persuasive. The Examiner finds, and we
agree, that Lee's assist instructions would have taught or suggested the
broadest reasonable interpretation of "the second operation code as an
unsupported operation code, unsupported by the first execution unit;"
because Lee's assist instructions are not executable by Lee's first execution
unit 117 in Figure 5, step 513 ("unsupported by the first execution unit").
(Ans. 14). Appellant fails to cite a definition of "unsupported operation
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code" in the Specification that is commensurate with the narrow meaning
imputed by Appellant’s arguments.
For these reasons, on this record, we are not persuaded of Examiner
error. Accordingly, we sustain the rejection R1 of claim 21 and of claims
22-24, 30-34, and 40, which fall therewith.

R2 AND R3
Appellant does not advance separate arguments for the claims rejected
under rejections R2 and R3. (App. Br. 9-13). Arguments not made are
considered waived. See 37 C.F.R. § 41.37(c)(1)(vii) (2004). Accordingly,
we sustain the Examiner's rejections R2 and R3.

DECISION
We affirm the Examiner's rejections R1-R3 of claims 21-40 under
§ 103.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED

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