Ex Parte 8,185,865 B2 et al

Patent Trial and Appeal Board

Dec 21, 2015

95002214 (P.T.A.B. Dec. 21, 2015)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/002,214 09/13/2012 8,185,865 B2 3169.001REX3 9833
26111 7590 12/21/2015
STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005
EXAMINER
GE, YUZHEN
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
12/21/2015 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD
Requester and Respondent

v.

TELA INNOVATIONS, INC.
Patent Owner and Appellant
____________________

Appeal 2015-007258
Reexamination Control 95/002,214
Patent US 8,185,865 B2
Technology Center 3900
____________

Before RICHARD M. LEBOVITZ, JEFFERY B. ROBERTSON, and
ANDREW J. DILLON, Administrative Patent Judges.

DILLON, Administrative Patent Judge.

DECISION ON APPEAL

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STATEMENT OF THE CASE
Patent Owner appeals under 35 U.S.C. § 134(b) (2002) and 315(a)
(pre-AIA) from the final decision of the Examiner adverse to the
patentability of claims 1–25 of U.S. Patent No. 8,185,865 B2 (“the ’865
patent”). Requester appeals under 35 U.S.C. §§ 134(b) the Examiner’s
decision not to adopt certain rejections of claims 1-25. We have jurisdiction
under 35 U.S.C. § 315 (2002).
We affirm.
Related Proceedings
Patent Owner informs us that there are four co-pending matters
regarding related patents:
1. Reexamination Control No. 95/001,832 for related U.S. Patent No.
7,441,211, PTAB Decision on Appeal (Appeal No. 2014-000592) issued on
March 31, 2014, and a Request for Rehearing is pending;
2. Reexamination Control No. 95/002,207 for related U.S. Patent No.
8,127,266, in which a Decision on Appeal was issued on September 23,
2014 (Appeal No. 2014-005984) and in which a reexamination certificate
issued on May 12, 2015 cancelling claims 1-20;
3. Case IPR2014-00094, Taiwan Semiconductor Manufacturing, Ltd.
v. Tela Innovations, Inc., for related U.S. Patent No. 8,490,043, which
proceeding was terminated on September 24, 2014 (Paper No. 27); and
4. Investigation No. 337-TA-906, In the Matter of Certain Standard
Cell Libraries, Products Containing Or Made Using The Same, Circuits
Made Using The Same, And Products Containing Such Integrated Circuits,
for related U.S. Patent No. 8,490,043.
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Invention
The ’865 patent describes a method for generating a biased layout for
making an integrated circuit. One such method includes obtaining a nominal
layout defined by one or more cells, where each cell has one or more
transistor gate features with a nominal gate length. The method further
comprises obtaining an annotated layout where the annotated layout contains
information describing gate length biasing of one or more of the transistor
gate features in one or more cells of the nominal layout. A biased layout is
produced by modifying the nominal layout using the information from the
annotated layout. The biasing modifies a gate length of those transistor gate
features identified by the information of the annotated layout. See Abstract.
Figures 1A and 1B from page 10 of Patent Owner’s Appeal Brief are
depicted below:

Patent Owner describes FIG 1A (cross-sectional view) and 1B (top
view) as depicting field effect transistors (FET) having four terminals
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referred to as the gate, source, drain and body. In most circuits, the body
terminal is simply connected to a node that, in operation, provides a fixed
voltage, and therefore FETs are typically referred to as having three
operational terminals, i.e., the gate, drain, and source. FETs can be
manufactured in a wide range of shapes and sizes. The size and shape of the
gate has a very strong influence on the electrical characteristics of the
transistor.
The gate of a transistor has a width and a length. As shown in Figs.
1A and 1 B, the gate-length determines the lateral distance between the
source and the drain. The gate-width determines the size of the “front”
along which the source and drain face each other. App. Br. 11.
Patent Owner acknowledges the impact of variations in gate width and
length noting: “changes in drive current and leakage current [occur] as a
[result] of small changes in the length of a transistor gate.” Id.

Claims
Claims 1–25 are subject to reexamination and have been rejected
under 35 U.S.C. §§ 102 and 103 as either anticipated or obvious. Claims 1–
24 are original patent claims. Only claims 1 and 25 are independent.
Claims 1 and 25 are illustrative.
1. A method for generating a biased layout for making an
integrated circuit, comprising:
(a) identifying a nominal layout defined by one or more
cells, each cell having one or more transistors having transistor
gate features with a nominal gate length;
(b) identifying an annotated layout, the annotated layout
itself provides information for identifying gate-length biasing of
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one or more of the transistor gate features in one or more cells
of the nominal layout; and
(c) producing a biased layout by modifying the nominal
layout using the information provided by the annotated layout,
such that the biasing modifies a gate length of those transistor
gate features identified by the information of the annotated
layout, the method implemented by a processor executing a
program.

25. A method for generating a biased layout for making an
integrated circuit, comprising:
(a) identifying a nominal layout defined by one or more
cells, each cell having one or more transistors having transistor
gate features with a nominal gate length;
(b) identifying an annotated layout, the annotated layout
itself provides information for identifying gate-length biasing of
one or more of the transistor gate features in one or more cells
of the nominal layout; and
(c) producing a biased layout by modifying the nominal
layout using the information provided by the annotated layout,
such that the biasing modifies a gate length of those transistor
gate features identified by the information of the annotated
layout, and wherein the information in the annotated layout
further defines shape or size parameters for biasing particular
ones of the transistors, the method implemented by a processor
executing a program.

Prior Art
Pramanik US 6,928,635 B2 Aug. 9, 2005

Yuh-Fang Tsai et al., Influence of Leakage Reduction Techniques on
Delay/Leakage Uncertainty, Proceedings of the 18th International
Conference on VLSI Design held jointly with 4th International Conference
on Embedded Systems Design (VLSID ’05), January 3–7, 2005 (hereinafter
“Tsai”).
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Antonio J. Lopez Martin, Cadence Design Environment, Klipsch School of
Electrical and Computer Engineering, October 2002 (hereinafter
“Cadence”).

Patent Owner’s Contentions
Patent Owner contends that the Examiner erred in entering the
following grounds of rejections against claims 1–25 (App. Br. 8):
A. The rejection of claims 1–13, 15, 16, 18, and 20 under 35 U.S.C.
§ 102(e) as being anticipated by Pramanik;
B. The rejection of claims 14 and 17 under 35 U.S.C. § 103(a) as
being unpatentable over Pramanik;
C. The rejection of claim 13, 14, 19, 21, and 23 under 35 U.S.C.
§ 103(a) as being unpatentable over Pramanik and Tsai;
D. The rejection of claims 22 and 24 under 35 U.S.C. § 103(a) as
being unpatentable over Pramanik, Tsai, and Patent Owner’s admitted prior
art;
E. The rejection of claims 16 and 17 under 35 U.S.C. § 103(a) as
being unpatentable over Pramanik and Cadence;
F. The rejection of claim 25 under 35 U.S.C. § 102(e) as being
anticipated by Pramanik.

ANALYSIS
Representative Claims
Patent Owner distinguishes all the cited prior art applied to claim 1–
24 based on the limitations of claim 1 and does not provide arguments for
separate patentability for any other claim. Patent Owner argues claim 25
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separately from claim 1. Accordingly, we will decide the appeal of claim 25
separately and the appeal of claims 1–24 on the basis of claim 1 alone. See
37 C.F.R. § 41.67(c)(1)(vii).
Claim Interpretation
In this proceeding, the claim language should be read in light of the
specification as it would be interpreted by one of ordinary skill in the art. In
re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364 (Fed. Cir. 2004). The
Office must apply the broadest reasonable meaning to the claim language,
taking into account any definitions presented in the specification. Id. (citing
In re Bass, 314 F.3d 575, 577 (Fed. Cir. 2002)).
“Information”
Patent Owner urges that the position of the Office with respect to the
rejection of independent claims 1 and 25, under 35 U.S.C. § 102(e) as
anticipated by Pramanik, as set forth in the Right of Appeal Notice, is not
well founded, arguing that the “tags” of Pramanik fail to provide the claimed
“information.” App. Br. 8–9.
Patent Owner’s Specification does not define what is meant by
“information.” At column 23, lines 37–38, the Specification states
“information describing the bias is contained in the annotated layout or bias
requirements 1110” (emphasis added), but doesn’t identify what constitutes
the “information.”
Similarly, claim 8 recites the identifying of “transistors to be biased”
by means of the “information” in the annotated layout. Claim 12 further
recites that the “information” defines “a shape or size parameters” for
biasing particular transistors, which while further limiting the particular
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“information,” does not provide a definition of the general term
“information” as recited in claim 1.
In response to the first Office Action, during prosecution, Patent
Owner argued that the “information” must identify an “amount of bias.”
Patent Owner expressly described what “amount of bias” means:
It is noted that the amount[] of bias may be specified in several
ways as disclosed in the ’865 patent, including but not limited
to,
[1] providing a specific bias length[],
[2] providing hints to [Optical Proximity Correction]
OPC processing tools,
[3] providing guardband reduction from knowledge of
the CD tolerance split,
[4] providing control for the direction of OPC error,
[5] providing information for sub-resolution assist feature
insertion,
[6] and so on.
Patent Owner Response mailed December 7, 2012, page 4 n.1.
Patent Owner also argues that the ’865 patent, at column 25, lines 35–
43, describes giving “hints” to the OPC implementation rather than explicit
biases or explicit changes in critical dimensions. Rebuttal Br. 8.
Having considered all of the evidence set forth above and within the
record we conclude that a broad yet reasonable definition of “information,”
as claimed, is a general, broad indication to process a particular transistor
according to certain preset rules, where those preset rules may define shapes
or size parameters.
Claims 1 and 25
Patent Owner argues error on the part of the Examiner in the rejection
of claims 1 and 25 in that the “information,” set forth in claims 1 and 25
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must have at least two components. Patent Owner urges that information
must “identify the transistor to be biased” and “provide information to
actually modify a gate length of the identified transistor.” App. Br. 8.
Patent Owner argues that for Pramanik to achieve the goal of
selectively modifying transistor gates,
Pramanik identifies and “tags” transistors that lie in critical
paths so that the post-layout processing tools can apply “a
different set of processing rules to the tagged gates than for
other gates in the layout (step 608),” (Id., 4:59-62.) The
different processing rules, in turn, “cause transistors in these
[tagged] gates to be modified based on the device
characteristics for the technology.” (Id., 5:4-6.) But again, that
modification must still lie within the CD range specified by the
manufacturer. (Id., 5:22-30.)
Id. at 15.
Patent Owner argues that the “tags” of Pramanik “contain no
information describing the bias, any other bias requirements, or even the
direction of OPC control” and merely disclose that a different set of post-
layout processing rules are applied to tagged versus untagged gates. Id. at
18 (emphasis omitted).
In the Action Closing Prosecution, mailed June 11, 2013, the
Examiner finds that Pramanik expressly teaches that certain transistors are
biased during Optical Proximity Correction, based upon whether or not those
transistors were “tagged.” The presence or absence of a “tag” thus provides
“information” regarding which set of processing rules should be applied.
ACP 4–6.
Given our broad, yet reasonable definition of “information” we set
forth above, we find no error in the Examiner’s position that the presence or
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absence of a tag, as described in Pramanik, both identifies a transistor on the
critical path, and provides “information” regarding the biasing which should
occur. We therefore find no error in the Examiner’s rejection of claims 1
and 25.
Patent Owner provides no separate and particular arguments alleging
error in the Examiner’s rejection of claims 13, 14–17, 19, and 21–24 (App.
Br. 26–30). We therefore find no error in the Examiner’s rejection of those
claims.
In view of our affirmance of the Examiner’s rejection of all claims,
we decline to consider Requester’s appeal of the non-adoption of certain
rejections of claims 1–25.

Summary/Conclusion
We sustain the Examiner’s rejections of claims 1–25.

DECISION
The Examiner’s decision adverse to the patentability of claims 1–25 is
affirmed.
Requests for extensions of time in this proceeding are governed by
37 C.F.R. §§ 1.956 and 41.79(e).
In the event neither party files a request for rehearing within the time
provided in 37 C.F.R. § 41.79, and this decision becomes final and
appealable under 37 C.F.R. § 41.81, a party seeking judicial review must
timely serve notice on the Director of the United States Patent and
Trademark Office. See 37 C.F.R. §§ 90.1 and 1.983.
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AFFIRMED

Patent Owner:

STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C.
1100 NEW YORK AVENUE, N.W.
WASHINGTON, DC 20005

Third Party Requester:

HAYNES AND BOONE, LLP
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219