95001832 (P.T.A.B. Nov. 3, 2014)

Ex Parte 7441211 et al

Patent Trial and Appeal BoardNov 3, 2014

95001832 (P.T.A.B. Nov. 3, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/001,832 12/08/2011 7441211 3169.001REX1 1031 26111 7590 11/04/2014 STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C. 1100 NEW YORK AVENUE, N.W. WASHINGTON, DC 20005 EXAMINER CABRERA, ZOILA E ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 11/04/2014 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD Requester and Respondent v. TELA INNOVATIONS, INC. Patent Owner and Appellant ____________________ Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 Technology Center 3900 ____________ Before FRED E. McKELVEY, JAMES T. MOORE, RICHARD M. LEBOVITZ, JEFFERY B. ROBERTSON, and ANDREW J. DILLON, Administrative Patent Judges. Per curiam. NEW DECISION ON APPEAL Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 2 I. INTRODUCTION Patent Owner requests rehearing of a Decision on Appeal (“Decision”) dated Mar. 31, 2014. 37 C.F.R. §41.79. See Patent Owner’s Request for Rehearing Under 37 C.F.R. § 41.79 (dated April 30, 2014). Requester filed a response: Third Party Requester’s Response to Patent Owner’s Request for Rehearing (dated May 20, 2014). The Decision affirmed a rejection of claims 1-36 of U.S. Patent No. 7,441,211 (hereinafter the ʼ211 patent) as being unpatentable under 35 U.S.C. § 103(a) over Rogenmoser (Ex. 2) and Houston (Ex. 3). According to Patent Owner, the Board failed to conduct a de novo 1 review of those portions of the Examiner’s rejections challenged by Patent Owner in its briefs on appeal: (1) Patent Owner’s Corrected Brief on Appeal Under 37 C.F.R. § 41.67 (dated May 7, 2013) and (2) Patent Owner’s Rebuttal Brief on Appeal Under 37 C.F.R. § 41.71, (dated July 22, 2013). Requester filed a responsive brief: Third Party Requester’s Second Respondent Brief in inter partes Reexamination pursuant to 37 C.F.R. § 41.68 (dated May 22, 2013). 1 Patent Owner’s belief that it is entitled to a de novo review is based on its overly broad interpretation of Ex parte Frye, 94 USPQ2d 1072 (BPAI 2010). If a finding or legal conclusion by an examiner is contested by an appellant on appeal, the Board reviews the finding or conclusion anew in light of all the evidence and the argument on that issue. 94 USPQ2d at 1075. Nothing in Frye relieves an appellant from its obligation to overcome an examiner’s rejection by submitting arguments and/or evidence to show that the examiner erred. Id. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 3 We grant the Request for Rehearing to the extent that we (1) vacate the Decision on Appeal dated Mar. 31, 2014 and (2) enter in its place a New Decision on Appeal. II. ABBREVIATIONS The abbreviations set out in Table 1 are used in the record and this Decision. Table 1 Term Meaning ʼ211 patent Involved U.S. Patent No. 7,441,211 ACP Action Closing Prosecution (37 C.F.R. § 1.953 (2012)) BLAZE Patent Owner Tela’s Design Optimization Service Br. Patent Owner’s Corrected Brief on Appeal Under 37 C.F.R. § 41.67, dated May 7, 2013. CD Critical Dimension CEO Chief Executive Officer CLLB Cell-level Lgate Biasing CMOS Complimentary Metal-Oxide Semiconductor EDA Electronic Design Automation FET Field Effect Transistor IC Integrated Circuit ICCAD International Conference on Computer-Aided Designs IDDQ Quiescent Current Leakage IEEE Institute of Electrical and Electronics Engineering, Inc. LGate Gate-length Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 4 LOCOS Local-oxidation-of-silicon MC Monte Carlo Monte Carlo A simulator in which ion implantation is simulated by flowing the history of energetic ion through successive collision with target atoms using binary collision assumption. Wolf, 2 SILICON PROCESSING FOR THE VLSI ERA, pp. 660-1 (1990) (ISBN 0-961672-4-5) MOS Metal-Oxide Semiconductor Field Effect Transistor OPC Optical Proximity Correction PO Patent Owner RAN Used by USPTO to refer to a Right of Appeal Notice Req. Requester TSCM Req. Br. Brief filed by Requester and Respondent on May 22, 2013 in the response to Patent Owner’s brief on appeal filed May 7, 2013. SLIP System Level Interconnect Prediction SOC System on a Chip SPICE Simulation Program with Integrated Circuit Emphasis Tela Tela Innovations, Inc. (Patent Owner) TSMC Taiwan Semiconductor Manufacturing Co., Ltd., i.e., Requester Vdd Voltage Drain-Drain Vth Gate Threshold Voltage VLSI Very Large Scale Integration Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 5 III. Issues Claims 1-36 the involved ʼ211 patent were rejected in an Office Action dated Mar. 5, 2012. See Grounds 1-41. In a Right of Appeal Notice (“RAN”) dated Sept. 19, 2012, the Examiner rejected claims 1-36 on various grounds: Grounds 1-10 and 21-30. Grounds 11-20 and 31-44 were withdrawn. RAN, pp. 13-14 and pp.16-17. An appeal was timely filed by Patent Owner as to claims 1-36. Requester did not cross-appeal from the decision of the Examiner withdrawing Grounds 11-20 and 31-44. Five Grounds are relevant to the appeal: (1) Ground 1: Claims 1-31 as being unpatentable under § 103(a) over Rogenmoser 2 and Houston. 3 (2) Ground 4: inter alia claims 32-36 as being unpatentable under § 103(a) over Rogenmoser, Houston, and Pramanik. 4 (3) Ground 21: Claims 1-31 as being unpatentable under § 103(a) over Rogenmoser and Tsai. 5 2 Rogenmoser, R. et al., “Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits,” 114111996 Parallel Problem Solving from Nature – PPSN IV Lecture Notes in Computer Science (1996). 3 Theodore W. Houston, US 6,954,918 B2 (Oct. 11, 2005). 4 Dipankar Pramanik et al., US 6,928,635 B2 (Aug. 9, 2005). Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 6 (4) Ground 24: inter alia claims 32-36 as being unpatentable under § 103(a) over Rogenmoser, Tsai, and Pramanik. (5) Ground 27: inter alia claims 32-36 as being unpatentable under § 103(a) over Rogenmoser, Tsai, and Hsueh. 6 In its appeal brief, Patent Owner limited its argument in support of reversal to claim 1. Patent Owner did not argue the separate patentability of claims 2-36 apart from claim 1. Accordingly, the rejections of claims 2-36 stand or fall with the rejections of claim 1. 37 C.F.R. § 41.67(c)(1)(vii) (2012). The issues on appeal are: (1) Whether Patent Owner has established that the Examiner erred in rejecting claim 1 under § 103(a) over Rogenmoser and Houston. (2) Whether Patent Owner has established that the Examiner erred in rejecting claim 1 under § 103(a) over Rogenmoser and Tsai. IV. Evidence Based on the issues to be decided, the relevant evidence in this appeal is set out in Table 2, all of which has been considered. 5 Y. Tsai, “Influence of Leakage Reduction Technologies on Delay/Leakage Uncertainty” Proceeding of the 18 th International Conference on VLSI Design held jointly with 4 th International Conference on Embedded System Design (Jan. 3-7, 2005). 6 Shi-Cheng Hsueh et al., US 7,032,194 B1 (April 18, 2006). Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 7 Table 2 Exhibit No. Submitted By Description Date 1 PO U.S. Patent No. 7,441,211 (Gupta) Oct. 21, 2008 2 PO Rogenmoser et al., “Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits,” PARALLEL PROBLEM SOLVING FROM NATURE—PPSN IV LECTURE NOTES IN COMPUTER SCIENCE, Vol. 1141/1996 7 1996 3 PO U.S. Patent 6,954,918 (Houston) 8 Oct. 11, 2005 11 PO Tsai, “Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty,” PROCEEDINGS ON THE 18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN HELD JOINTLY WITH THE 4TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS DESIGN (VLSID ’05), JANUARY 3-7, 2005 9 2005 12 PO Declaration of Scott T. Becker under 37 C.F.R. § 1.132 May 7, 2012 13 PO Declaration of John E. Berg under 37 C.F.R. § 1.132 May 7, 2012 14 PO Declaration of Puneet Gupta under 37 C.F.R. § 1.132 May 6, 2012 7 Also Requester’s Exhibit E8. 8 Also Requester’s Exhibit E9. 9 Also Requester’s Exhibit E12. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 8 15 PO Declaration of Andrew B. Kahng under 37 C.F.R. § 1.132 May 7, 2012 19 PO Press Release: TSMC Announces Power Trim Service for Advanced Chip Leakage Power Reduction April 15, 2008 20 PO Press Release: TSMC and TELE Innovations Announced Strategic Partnership to Enhance Design and Process Co-optimization Feb. 24, 2009 21 PO Press Release: Mellanox and TSMB Collaborate to Enable Next- Generation Green Data Centers Mar. 23, 2010 22 PO Press Release: TSMC Helps LSI Reduce Leakage 25 Percent on Next Generation Product Jan. 6, 2012 24 PO Declaration of Robert Rogenmoser under 37 C.F.R. § 1.132 July 13, 2012 E1 Req Declaration of Harvey Stiegler under 37 C.F.R. § 1.132 June 4, 2012 E2 Req Declaration of Cliff Hou under 37C./F.R. § 1.132 June 5, 2012 E3 Req IEEE 100: The Authoritative Dictionary of IEEE Standards/Terms (7th ed.) © 2000 E6 Req Respondent’s “Response to Patent Owner’s ACP Reply,” Claim Charts CC-D, pages 2-9 (claim 1) N/A The prior art relied upon by the Examiner in support of rejections of claim 1 is: (1) Ex. 2—Rogenmoser; (2) Ex. 3—Houston; and (3) Ex. 11—Tsai. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 9 Patent Owner does not contest the prior art status of the three above-identified prior art references. V. Witnesses Testimony in a reexamination is presented in the form of a declaration. There is no cross-examination in reexamination proceedings. The following witnesses testified in this proceeding with respect to the patentability of claim 1 vis-à-vis (1) Rogenmoser and Houston and (2) Rogenmoser and Tsai. A. Scott T. Becker Scott T. Becker testified on May 7, 2012, on behalf of Patent Owner. Ex. 12 (Becker Decl.), p. 13. Mr. Becker has a bachelor’s degree in Electrical Engineering from the University of Illinois (Champaign-Urbana, IL) and a master’s degree in Electrical Engineering from Santa Clara University. Ex. 12 (Becker Decl.), ¶ 8. At the time of his testimony, he was CEO of Patent Owner Tela Innovations. Ex. 12 (Becker Decl.), ¶ 1. B. Robert Rogenmoser Robert Rogenmoser testified on May 4, 2012, on behalf of Patent Owner. Ex. 24 (Rogenmoser Decl.), p. 10. Dr. Rogenmoser has a master’s degree and a doctorate degree in Electrical Engineering from the Swiss Federal Institute of Technology in Switzerland and a master’s degree in Business Administration from Santa Clara University. Ex. 24 (Rogenmoser Decl.), ¶ 7. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 10 Dr. Rogenmoser was retained to testify on behalf of Patent Owner. Ex. 24 (Rogenmoser Decl.), ¶ 1. He is being compensated at his standard rate of $360/hour and his compensation, is not dependent on and in no way affects the substance of . . . [his testimony]. Ex. 24 (Rogenmoser Decl.), ¶ 14. C. John E. Berg Mr. Berg testified on May 7, 2012, on behalf of Patent Owner. Ex. 13 (Berg Decl.), p. 30. He has bachelor’s degree in Physics from Massachusetts Institute of Technology and a master’s degree in Management from Stanford University. Ex. 13 (Berg. Decl.), ¶8. At the time of his testimony, he was the Chief Technologist at American Semiconductor, Inc., in San Jose, CA. Ex. 13 (Berg Decl.), ¶ 9. Mr. Berg was retained to testify on behalf of Patent Owner. Ex. 13 (Berg Decl.), ¶ 1. He is being compensated at his standard rate of $300/hour and his compensation “is not dependent on and in no way affects the substance of . . . [his testimony].” Ex. 13 (Berg Decl.), ¶ 13. D. Puneet Gupta Dr. Gupta is a named inventor on the ʼ211 patent. Ex. 14 (Gupta Decl.), ¶ 1; Ex. 1 (ʼ211 patent), p.1. He testified on May 6, 2012, on behalf of Patent Owner. Ex. 14 (Gupta Decl.), p. 11. Dr. Gupta has a bachelor’s degree in Electrical Engineering from the Indian Institute of Technology at New Delhi, India, and a doctorate degree Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 11 in Electrical Engineering from the University of California at San Diego. Ex. 14 (Gupta Decl.), ¶ 5. At the time of his testimony, he was an assistant professor in the Electrical Engineering Department of the University of California at Los Angeles (UCLA). Ex. 14 (Gutpa Decl.), ¶ 7. E. Andrew B. Kahng Dr. Kahng is a named inventor on the ʼ211 patent. Ex. 15 (Kahng Decl.), ¶ 1; Ex. 1, p. He testified on May 7, 2012, on behalf of Patent Owner. Ex. 15 (Kahng Decl.), p. 11. Dr. Kahng has a bachelor’s degree in Applied Mathematics and Physics from Harvard University and a master’s degree and a doctorate degree in Computer Science from the University of California at San Diego. Ex. 15 (Kahng Decl.), ¶4. At the time of his testimony, Dr. Kahng was a professor in the Departments of Computer Science and Engineering and Electrical and Computer Engineering at the University of California at San Diego. Ex. 15 (Kahng Decl.), ¶ 3. F. Harvey Stiegler Dr. Stiegler testified on June 4, 2012, on behalf of Requester. Ex. E1 10 (Stiegler Decl.), p. 7. 10 Requester has numbered its exhibits using the prefix ‘E.’ Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 12 He has a bachelor’s degree in Electrical Engineering from Texas Tech University and a master’s and doctorate degree in Computer Engineering from Rice University. Ex. E1 (Stiegler Decl.), ¶¶ 13-15. At the time of his testimony, he was employed as a research scientist at the University of Texas in Dallas, TX. Ex. E1 (Stiegler Decl.), ¶ 5. G. Cliff Hou Dr. Hou testified on June 5, 2012, on behalf of Requester. Ex. E2 (Hou Decl.), p. 4. He has a bachelor’s degree in Control Engineering from Taiwan’s National Chiao-Tung University and a doctorate degree in Electrical and Computer Engineering from Syracuse University. Ex. E2 (Hou Decl.), p. 2 ¶¶ 4 and 6. At the time of his testimony he was employed by Requester TSMC as Vice President of Design and Technology Platform. Ex. E2 (Hou Decl.), p. 2, ¶ 1. H. Observations on Witnesses The witnesses appear to be qualified to testify on the subjects discussed in their respective declarations. Later in this opinion we discuss the weight given to the testimony. VI. Analysis A. The invention The ’211 patent relates generally to the optimization of digital integrated circuits and in particular to gate-length biasing of transistors, all of which are said to improve performance characteristics. Ex. 1 (ʼ211 patent), col. 1:16-18. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 13 A gate-length biasing method described in the ʼ211 patent replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. Ex. 1 (ʼ211 patent), Abstract. Figures 1A (cross-section) and 1B (top view) of schematic representations of a transistor are reproduced below: Depicted above are schematic views of a cross-section and a top view of a transistor Ex. 12 (Becker Decl.), p. 4, ¶ 1; slightly different versions of Fig. 1A and Fig. 1B are reproduced at Br. 15. Fig. 1A (cross-sectional view) and Fig. 1B (top view) depict field effect transistors (FET) having three terminals (electrical connection points) referred to as the gate, source, and the drain, all mounted on a body. Ex. 12 (Becker, Decl.), ¶ 1:5 6; Br. 14. In most circuits, the body terminal is connected to a node that, in operation, provides a fixed voltage, and therefore FETs are typically referred Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 14 to as having three operational terminals, i.e., the gate, drain, and source. Ex. 12 (Becker, Decl.), ¶ 1:7-10; Br. 14. FETs can be manufactured in a wide range of shapes and sizes. Ex. 12 (Becker Decl.), ¶ 1:10; Br. 14. Size and shape of a transistor gate are said to have “a very strong influence on the electrical characteristics of the transistor.” Ex. 12 (Becker Dec.), ¶ 1:10-12. See also Br. 14. A gate of a transistor has a width and a length. Ex. 12 (Becker Decl.), ¶ 2. As shown in Figs. 1A and 1B, the gate-length determines a lateral distance between the source and the drain. Ex. 12 (Becker Decl.), ¶ 2. The gate-width determines the size of the “front” along which the source and drain face each other. Ex. 12 (Becker Decl.), ¶ 2. According to Patent Owner, “[c]hanges in gate-width have very different effects on the electrical characteristics of a FET than do changes in gate-length. Changes in gate-width and [gate-]length also have different effects on a transistor's physical layout.” Br. 15. Two examples of changes are as follows. (1) An increase in gate-width allows more current to flow through a FET, whereas an increase in gate-length allows less current to flow through the FET. Ex. 14 (Gupta Decl.), ¶ 13. (2) An increase in gate-width does not reduce sub-threshold leakage current result from short-channel effect, whereas an increase in gate length reduces sub-threshold leakage current resulting from short-channel effects. Id. at ¶ 12. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 15 On the basis of Patent Owner’s technical background presentation, we understand that it was well-known in the art that gate-length changes result in competing advantages and disadvantages—speed versus leakage current. As the gate-length is increased, there is less current leakage through the transistor; however, more time is required to switch a transistor with a longer gate, resulting in a lower speed of operation. Accordingly, those skilled in the art would have understood that, assuming a constant gate-width: Leakage current = f (1 / (gate-length). One skilled in the art also would have understood that: Speed = f (1 / gate-length). The principle embodied in the first formula is illustrated in ʼ211 patent Fig. 1 reproduced below by the solid curve (normalized leakage as a function of gate-length). ʼ211 patent Fig. 1 Depicted above is a graph of the variation of delay and leakage with gate-length Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 16 B. Claim 1 Claim 1 is the only claim we need to consider. Reproduced below are Fig. 4A and Fig. 7 of the ʼ211 patent. ʼ211 patent Fig. 4A Depicted above is a flow chart of a CLLB embodiment of a library generation step Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 17 ʼ211 patent Fig. 7 Depicted above is a flow chart of an embodiment of a biasing method used to design biased variants for a library generation method Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 18 With reference to ʼ211 patent Figs. 4A and 7, claim 1 reads [figure numbers and footnotes added for illustration]: 1. A gate-length biasing [11] method for modifying a nominal cell [12] of an integrated digital circuit, the nominal cell containing one or more transistors, the method comprising the steps of: (a) selecting a trial set of one or more transistors in the nominal cell [Fig. 4A, 405], each selected transistor having a nominal gate-length; [13] 11 The phrase “biasing a device” implies adjusting the gate-length of the device slightly. Ex. 1 (ʼ211 patent), col. 4:64-65. The Examiner held that biasing a device in the context of the ʼ211 patent means “adjusting the gate length” slightly relative to its unbiased state. RAN, page 17, ¶ 66. 12 A cell is a circuit comprised of one or more transistors configured to perform some function. Ex. 1 (ʼ211 patent), col. 8:13-14. 13 The term “nominal gate-length” refers to the gate-length of an unbiased device. Ex. 1 (ʼ211 patent), col. 4:66-67. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 19 (b) determining trial small bias lengths [Fig. 4A, 410] for the selected trial set of transistors [Fig. 4A, 405], the trial small bias lengths [14] all less than a predefined fraction of the nominal gate-length; [15] (c) adjusting [16] the gate-lengths of the selected trial set of transistors by the small bias lengths to create a trial biased cell; (d) comparing the trial biased cell to a current best biased cell with respect to a predefined goal [Fig. 7, 755] including a tradeoff between reducing a leakage power for the biased cell and reducing an impact on timing delays [17] for the digital circuit [Fig. 7, 780]; and 14 The small bias length may be, for example, less than 10% of the nominal gate-length or less than a predefined fraction of the nominal gate-length. The bias length may be determined by evaluating a design tradeoff, such as leakage power versus circuit delay, i.e., speed. The gate-length biasing methodology may be applied, for example, at a cell level, that is, to all transistors within the cell, or to a single transistor within the cell. Ex. 1 (ʼ211 patent), col. 3:20-25. 15 One embodiment of the CLLB library generation 305 [Fig. 4A] focuses on less than 10% biasing. However, alternative embodiments may include biasing over 10%. Bias lengths less than 10% of the nominal gate-length are said to be advantageous for several reasons. Ex. 1 (ʼ211 patent), col. 8:63 – col. 9:29. 16 Gate-length biasing includes optimizing a circuit by adjusting a nominal gate-length of a transistor by a small bias length. Ex. 1 (ʼ211 patent), col. 3:20-22. 17 Under biasing method 750, a design goal is established, for example, minimum delay. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 20 (e) updating the current best biased cell based on the comparison. C. Rejection based on Rogenmoser and Houston 1. Examiner’s Rejection The Examiner’s rejection of claim 1 is set out in an Office Action dated Mar. 5, 2012. Off. Action, p. 3-5. In relevant part, the rejection was explained in paragraphs 5-6 as follows [bold, italics and underlining in original; footnotes added]: 5. With respect to claim 1, Rogenmoser discloses a [gate- length biasing] [18] method for modifying a nominal cell of an integrated digital circuit, the nominal cell containing one or more transistors, the methods comprising the steps of: (a) selecting a trial set of one or more transistors in the nominal cell, each selected transistor having a nominal size [gate-length] (p. 853, 3 Optimization Method, 3.1 Monte Carlo, step 1 “Assign a set of random sizes for each transistor”); (b) determining trial small bias size [lengths] all less than a predefined fraction of the nominal size [gate-length] (p. 853, 3 Optimization Method 3.1 Monte Carlo, step 3, “Increase, decrease each sizes of the set by a fixed step”); 18 The Examiner set out differences between Rogenmoser and claim 1 in brackets. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 21 (c) adjusting the size [gate-length] of the selected trial set of transistors by the small bias size [lengths] to create a trial biased cell (p. 853, 3 Optimization Method, 3.1 Monte Carlo, step 3, “Increase, decrease each sizes of the set by a fixed step”); (d) comparing the trial biased cell to a current best biased cell (step 4, “Evaluate the solution; if this set has a better fitness continue with this test, otherwise use the previous one”; this evaluation for fitness test requires comparing the current solution to the previous solution) with respect to a predefined goal including a tradeoff between reducing a leakage power for the biased cell and reducing an impact on timing delays for the digital circuit (p. 852, 2.1 Objective Functions, “The most important optimization goal for these circuits was to minimize the propagation delay for all inputs to the output for both, the high to low (01) and the low to high (10) transitions with limited increase in power consumption”); and (e) updating the current best biased cell based on the comparison (see Steps 4 and 5;[ 19 ] the current best solution is used for comparison in step 4 of the next iteration). 19 “4. Evaluate the solution; if this set has a better fitness continue with this set, otherwise use the previous one.” Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 22 6. Although Rogenmoser’s transistor size optimization method does not specifically mention adjusting gate-length as indicated with square brackets above, changing the size of a transistor would imply changing the gate size of the transistor as well (see [Ex. 3] Houston, 1:33-38 “Conventionally, one feature that distinguishes a low power cell from other cells, such as high performance cells, is a large cell footprint. The footprint is larger because a low power cell has a gate that is longer than the gate of a high performance cell, which requires the contacts of the low power cell to be further apart from each other”). To the extent that Rogemoser’s transistor size optimization method does not disclose a method of biasing the gate-lengths, Houston specifically discloses this (see Figure 5). Houston discloses that the gate-length can be adjusted, without changing the function or footprint of a cell ([Ex. 3] 3:13-8-9, “A footprint refers to the size of the cell”, to make a selected cell either a high performance cell or a low power cell ([Ex. 3], 3:60-66). Houston discloses that “it is desirable to have lower power cells 18 and high power cells 20 [20] that have the same function to also have the same footprint so that one may 5. If maximum number of evaluations is reached stop, else goto [step] 3.” Ex. 2 (Rogenmoser), p. 853. 20 See Houston’s Fig. 1 and Fig. 2. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 23 substitute for another without disrupting the total layout” ([Ex. 3] 3:25-29). Accordingly, it would have been obvious for one of ordinary skill in the art, at the time of the invention, to modify Rogenmoser’s IC [integrated circuit] optimization method to vary the gate-length without changing the footprint, as taught by Houston, to improve flexibility in IC design (see [Ex. 3] Houston, 3:5-41 [21] ). The Examiner adhered to the rejection in the RAN, pp. 3-5 (re-stating the rejection) and 19-25 (analysis of PO’s arguments responding to the Off. Action of Mar. 5, 2012). 2. PO’s Arguments on Appeal (a) Preamble of claim 1 Requester has taken the position that “the preamble of claim 1 is a mere [statement of] intended use, and does not provide patentable weight.” Ex. E6, p. 2; Req. Br. 10 (first full paragraph). Patent Owner disagrees. Br. pp. 5 and 27-28. The Examiner does not appear to have addressed the weight to be given the preamble. 21 “Conventionally, the design and manufacture of a low power cell requires the use of a cell footprint that is larger than the footprint of a high performance cell because of the low power cell’s longer gate. * * * [T]he requirement to use a different size footprints make it difficult and costly to change from a low power cell, such as low power cell 18, to a high performance cell, such as high performance cell 20, or vice versa because such a change may require a rearrangement of other cells 14 [see Houston Fig. 1].” Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 24 Principles applicable to preambles are summarized in Rowe v. Dror, 112 F.3d 473, 478 (Fed. Cir. 1997): 22 A claim preamble has the import that the claim as a whole suggests for it. Where a patentee uses the claim preamble to recite structural limitations of his claimed invention, the PTO and courts give effect to that usage. Conversely, where a patentee defines a structurally complete invention in the claim body and uses the preamble only to state a purpose or intended use for the invention, the preamble is not a claim limitation. (citations omitted). While it would appear that the claim 1 preamble can be viewed as stating an intended use, in this case even if the preamble is given weight it would make no difference as to the outcome. In a light most favorable to Patent Owner, we elect to treat the preamble as a claim limitation. (b) Standard of Claim Construction In a reexamination proceeding involving an unexpired patent, the USPTO gives language of claims its broadest reasonable construction consistent with the specification. See, e.g., In re Etter, 756 F.2d 852, 856-58 (Fed. Cir. 1985) (en banc); In re Am. Acad of Sci. Tech Ctr., 367 F.3d 1359, 1363-64 (Fed. Cir. 2004); In re Yamamoto, 740 F.2d 1569, 1571 (Fed. Cir. 1984), announcing a claim construction standard different from that applicable in an infringement 22 See also Kropa v. Robie, 187 F.2d 150 (CCPA 1951) (discussion of effect of preamble to claim). Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 25 context as set out, e.g., in Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc). According to Patent Owner, the Federal Circuit applied the Phillips standard in a reexamination in In re Baxter Int’l, Inc., 678 F.3d 1357, 1366 (Fed. Cir. 2012). Br. 21. What the Federal Circuit said in Baxter was that “[t]o ascertain the scope and meaning of the . . . claims, we look to the words of the claims . . ., the specification, the prosecution history, and, lastly any relevant extrinsic evidence.” Baxter, at 1362. We understand the court’s statement on page 1365-66 to be that in the reexamination before it, that the Board applied a construction identical to that which had been urged by the patent owner. (c) Sizing versus Biasing Rogenmoser describes its subject matter in terms of transistor “size” (Ex. 2, p. 849) or “sizes” (Ex. 2, p. 851) whereas claim 1 uses the terms “biasing” and “gate-length biasing”. According to Patent Owner, Rogenmoser is directed to transistor “sizing” whereas the claimed invention is directed to a “biasing” technique. Br. 9. Further according to Patent Owner, “sizing” is different than “biasing.” Still further according to Patent Owner, the Examiner has misinterpreted the terms “biasing” and “gate-length biasing” in an unreasonably broad manner that fails to distinguish those terms from “sizing.” Br. 22. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 26 The Examiner found that “[t]he phrase ‘biasing a device’ implies adjusting the gate-length of the device slightly.” RAN, p. 17; Ex. 1, col. 4:65-66. As a result, in context of claim 1 the Examiner construed “biasing” to mean adjusting a transistor gate-length slightly relative to its unbiased state. A specification is the single best guide to the meaning of disputed claim terms, Phillips at 1350, a principle of law applied by the Examiner, RAN 20. The specification supports the Examiner’s construction of “biasing.” The Examiner found that the term “sizing” does not appear in claim 1. RAN, p. 19. Rather, the term appears in Rogenmoser. The issue thus becomes what is the significance of Rogenmoser’s use of the terms “size” or “sizing”? In essence, the Examiner found that “biasing” is one way to “size” a transistor. Off. Action, p. 4 (“changing the size of a transistor would imply changing the gate size of the transistor as well”). Rogenmoser exemplifies “sizing” in terms of a change in gate-width changes as opposed to gate-length changes. Ex. 2 (Rogenmoser), p. 851: In the simple case of an inverter most designers can optimize the transistor sizes using an accurate circuit simulator combined with extracted transistor models from fabricated devices. Typically, the PMOS is sized 1.5 to 3 times larger than the NFET from experience and after a few simulation runs the final size of the two is fixed. Because the current through a MOS transistor is Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 27 proportional to W/L (W; width, L: length of the channel) only W is adjusted and L is kept minimal. Mr. Becker testified (Ex. 12, p. 8:2-7): Sizing of a transistor in digital circuits is virtually universally done by choosing a gate-width for that transistor because the gate-length is pre-selected to be the nominal size (typically the nominal polysilicon linewidth) in a given semiconductor manufacturing process. Sizing defines the nominal cell layout. The design phase activity of sizing is complete when changes in gate-width no longer impact the timing of the digital integrated circuit design as determined by simulation. Mr. Berg further testified (Ex. 13, page 15:1-7): Sizing of a transistor in digital circuits is done throughout the industry by choosing a gate-width for that transistor when the gate-length is pre-selected to be the nominal size in a given semiconductor manufacturing process. Sizing typically defines the boundaries of nominal cell layout because the cell must be large enough to accommodate the presence of all the cell’s transistors. The design phase activity of sizing is complete when changes in gate-width no longer impact the timing of the digital integrated circuit design as determined by simulation. Dr. Gupta (Ex. 14,¶ 30) and Dr. Kahng (Ex. 15, ¶ 31) testified along the same lines as Mr. Becker and Mr. Berg. Dr. Rogenmoser, the author of the Rogenmoser article (Ex. 2), testified that “[t]he difficulties associated with optimizing the size, i.e., the gate-width and the gate-length of FET’s in a circuit is discussed [in his article].” Ex. 24, ¶ 27. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 28 Dr. Rogenmoser does not identify where any discussion is set out; we note, however, that Rogenmoser states that “only the width and length of the MOS (Metal Oxide Semiconductor) transistors can be adjusted.” Ex. 2, page 1, first full paragraph. Dr. Rogenmoser goes on to testify that in embodiments described in his article “only transistor widths are changed.” Ex. 24, ¶ 34. Dr. Stiegler testified (Ex. E1, ¶¶ 22-24): 22. I understand the term “sizing” to mean determining both the gate length and gate width of a transistor. 23. Sizing is a technique for determining a desired length and width of a transistor, which includes making adjustments as needed. Specifically there are many design goals that must be considered during the design process, and properly setting and adjusting the size of transistors is important in these goals. Choosing the size of a gate, including both gate-length and gate width, is important to the design goals. 24. In a typical design process, as designers we would select an initial size for all of the components and transistors of a circuit, and then perform a simulation on the circuit. The simulation would reveal many things about the circuit, for example, that the speed of some transistors need[s] to [be] increased, and that some transistors may be faster than needed. In response, a designer would typically re-size some (or all) of the transistors as needed to balance speed and power needs. Re-sizing a transistor means one or more components of the transistor (e.g., gate length or gate width) is adjusted. Biasing a transistor also means one or more components Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 29 of the transistor (e.g., gate length or gate width is adjusted. Patent Owner’s witnesses appear to restrict the meaning of “sizing” to variations of gate-width only, whereas Requester’s witness views “sizing” as more broadly to include variations in gate-length, gate-width, or both. To the extent that there is a conflict between Patent Owner’s witnesses and Dr. Stiegler, we credit the testimony of Dr. Stiegler over that of Patent Owner’s witnesses. One skilled in the art would have known that determining a proper “size” of a transistor logically would involve a consideration of both gate-width and gate-length. As noted earlier, Rogenmoser says that both width and length are factors to be considered. The adjustment of either length, width, or both is supported by (1) Rogenmoser (1996) and (2) post-Rogenmoser prior art (Houston (as early as 2002) and Tsai (2005)) revealing that as of 2002 both gate-width and gate-length were known factors that one skilled in the art would have taken into consideration in designing a transistor. Ex. 3 (Houston patent), Fig. 5, element 174; col. 3:64-66 (discussing a gate-length embodiment); Ex. 11, ¶ 3 (increasing gate-length) and ¶ 4.1.1 (gate-length biasing). Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 30 (d) Tapeout Patent Owner urges that the Examiner’s rejection with respect to the rejection of claim 1 “demonstrates a fundamental misunderstanding between the separate concepts of “biasing” and “sizing” in the context of semiconductor circuit design and manufacturing, and the ’211 patent.” Br. 9. Patent Owner argues that Rogenmoser is directed to “sizing” and not “biasing” as claimed, urging that sizing is “pre-tapeout activity directed towards arriving at nominal transistor dimensions” while biasing refers to a process whereby the “actual size of a transistor on an IC device then may be skewed from the nominal size through blanket manufacturing adjustments.” Id. at 11. 23 In support of a distinction between “sizing” and “biasing,” Patent Owner cites the ’211 Specification separate use of both terms, quoting, as one example, “[t]his allows gate-length biasing-based optimization to be possible at any point in a design flow, unlike sizing-based methods.” Specification, col. 6:4-6 (italics added). 23 According to counsel for Patent Owner (Br. 16-17): There are two broadly recognized separate sets of activities that occur in order to respectively develop and deliver these integrated circuits to customers. The first set of activities is design and the second set of activities is manufacturing. At the completion of design activities, the information needed to produce the designed integrated circuit is provided to a manufacturer. The process of transferring this information from the designer to the manufacturer is referred as ‘tape-out”’. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 31 Patent Owner thus argues that when the term “gate-length biasing” is properly construed, and the references are properly understood, “it becomes clear that the art cited in support of the pending rejections does not teach the ‘gate-length biasing method’ recited in independent claim 1 of the ‘211 patent.” Br. 8-9. The Examiner found that Rogenmoser teaches transistor size optimization, citing page 853, where Rogenmoser discusses Optimization Methods which include the steps of “[a]ssign[ing] a set of random sizes for each transistor” followed by the step of increasing or decreasing each size of the set by a fixed step. RAN, pp. 3-4. The Examiner found that the transistor size optimization technique described by Rogenmoser does not explicitly describe biasing of the gate- lengths of transistors, but relied on Houston for the necessary teaching. Houston, in Figure 5, describes changing the transistor gate length. RAN 5. See Fig. 5, element 174 (“Change gate length without changing the contact-to-centerline distance or make cell model replacement”). Requestor maintains that Patent Owner’s attempt to distinguish “sizing” from “biasing” based on pre-tapeout fails, noting that three embodiments are described in the ʼ211 specification of gate-length biasing and that only one of those embodiments describes a process which occurs after tape-out. ʼ211 Specification, col. 22:64-col. 23:6: The general gate-length biasing methodology of the present invention can be applied to a circuit design in many different ways. For example, [1] the mask maker or integrated circuit (IC) fab can implement gate-length biasing via optical proximity correction (OPC). Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 32 Alternately, [2] the provider of the cell library can offer an enhanced library containing gate-length biased variants of standard cells. As another example, [3] electronic design automation (EDA) tool vendors may implement some or all of the gate-length biasing as part of their software design tools (e.g., as part of the design rule-checker). Requester points out that the remaining two examples (i.e., [2] and [3]) of gate-length biasing describe the use of an enhanced library containing “gate-length biased variants of standard cells” or, the use of “gate-length biasing as part of their software design tools.” Requestor further points out that these two examples both take place prior to tapeout. Req. Br. 3-4. Requestor still further points out correctly that claim 1 contains no temporal [i.e., time,] limitation which would limit the point in time at which the “gate-length biasing” would occur. Id. Requester’s argument is supported by the testimony of Dr. Stiegler (Ex. E1, ¶¶ 18 and 20). Paragraph 18 states in part: Biasing can occur prior to or after tape-out. In fact, I have personal experience in performing and implementing biasing operations to optimize my circuit designs before tape-out. Paragraph 20 states in part: I do not believe there to be an industry-wide, accepted definition of the term ‘tape-out’ or the point in time where on may determine a tape-out has occurred. Tape- out may be considered to be the time at which a design Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 33 data base is declared finalized; or it may be considered to be the time at which the final mask-making pattern information has been generated. The term “tape-out” can also be used to refer to the process of translating the design database into mask data. Dr. Stiegler discusses the significance of that part of the specification describing alternatives [2] and [3] quoted above, noting (Ex. E1, p. 5:6-9): Providing of an enhanced library containing gate-length biased variants of standard cells refers to an activity in a design process that occurs prior to the tape-out of a design. Implementing gate-length biasing as part of EDA design tools refers to an activity in a design process that occurs prior to the tape-out of a design. The fundamental basis of Patent Owner’s argument in support of error is a failure of the Examiner to acknowledge the alleged distinction between “sizing” and “biasing” urged by Owner. Patent Owner describes “gate-length biasing” as being implemented utilizing: optical proximity correction, which occurs after tape-out; as well as a library containing gate-length biased variants of standard cells; or, the use of gate-length biasing as a part of the software design tools, both of which occur prior to tape-out. Claim 1 contains no limitation stating the time when the claimed process of gate-length biasing takes place in the design flow. Rogenmoser describes transistor size optimization. Rogenmoser further describes the known use of circuit simulators, such as SPICE, to alter the “width and length of the channel of the MOS” at page 849. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 34 Rogenmoser still further describes a particular embodiment which acknowledges that current through a MOS transistor is proportional to the relationship of the width and length of the channel and therefore only adjusts the width of the channel while keeping the length of the channel at a minimum. Page 851. However, Houston at Figs. 2 and 5 and associated discussion of Figs. 2 and 5 expressly describes the biasing of transistor gate length. According to Patent Owner, Houston is not directed to gate-length biasing. Br. 32-35. Patent Owner reasons that “Houston requires that the contacts be moved farther apart to accommodate the longer gate length . . . .” Br. 33; Ex. 3, Fig. 2 and col. 3:60-64. We have not found a limitation in claim 1 requiring that the “size” of the transistor before and after biasing must be the same. Patent Owner also argues that Rogenmoser and Houston cannot be “combined” essentially because Rogenmoser is said to be limited to what Patent Owner refers to as “sizing.” Br. 2. As noted earlier, Rogenmoser describes a process of (1) assigning a random size for each transistor, (2) increasing (or decreasing) each size by a fixed step (illustrated by varying gate- width), and (3) evaluating the increase (or decrease). Ex. 2, p. 853 (steps 1, 3 and 4). Rogenmoser’s process can be considered “biasing” of width when a size of a transistor is increased in successive steps. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 35 However, even if Rogenmoser is limited to “sizing” as defined by Patent Owner, Houston overcomes Patent Owner’s “sizing” concerns. Once Houston became prior art in 2003, the non-automaton 24 person skilled in the art as of 2004 would have recognized that biasing of gate-length could be accomplished using the 1996 Rogenmoser technique. Patent Owner criticizes Rogenmoser because it describes randomly assigning gate-widths as opposed to using a fixed gate-width. Br. 34. As a result, Patent Owner maintains that Rogenmoser’s process would not be used for determining gate-length. Id. The Rogenmoser objective is exemplified by describing a means to determine an appropriate gate-width. The assigned random gate-width size is a nominal size—the starting point. The increased gate-width size is the biased gate width size. Houston teaches that changing gate-length of a transistor 25 within a cell while maintaining the cell size means that a second cell 24 KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 421 (2007). 25 Dr. Stiegler testified that Houston describes sizing by making adjustments to the size (gate-length in this instance) of a transistor in a circuit, citing to Houston, col. 6:18-34. A cell is made up of one or more transistors. In the context of Houston, one skilled in the art would understand that adjustments are to gates of transistors within cells, not to Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 36 can be substituted for a first cell without having to geometrically re-design an entire integrated chip (IC), e.g., a cell 20 could be substituted for a cell 18 in integrated circuit 10 as shown in Fig. 1 reproduced below. Houston Fig. 1 Depicted above is a block diagram of an integrated circuit 10 having a plurality of cells 14 shown as low power cells 18 and high performance cells 20 As a consequence, we disagree with Patent Owner’s assertion that Rogenmoser would not be utilized to determine gate-length. cells per se. Adjustment of the size of a cell would defeat Houston’s purpose of being able to substitute one cell for another. Whether a Houston cell is low performance or high performance is a function of the transistor or transistors within the cell. Fig. 2 thus shows a modification of the gate- length of a transistor and Fig. 5 (element 174) would be understood as referring to a gate-length change—not a cell dimension change. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 37 D. Rejection based on Rogenmoser and Tsai 1. The Examiner’s Rejection Claim 1 also stands rejected under § 103(a) as being unpatentable over Rogermoser and Tsai. Rejection, Ground 21 in the Off. Action, p. 16 and the RAN, p. 14. In making the rejection, as to claim 1 the Examiner relied on pages 2-9 of Requester’s Exhibit E6, which the Examiner incorporated by reference into the explanation of the rejection. RAN, p. 14. A copy of the relevant parts of pages 2-9 is attached as Appendix 1 to this opinion. Rogenmoser has been discussed earlier in this opinion. Relevant parts of Tsai are discussed in Appendix 1. The Examiner’s position on obviousness is revealed through his adoption of Requester’s analysis of Rogenmoser and Tsai. 2. Patent Owner’s Arguments Patent Owner acknowledges that “Tsai . . . discuss[es] increasing gate-length as a mechanism to reduce active leakage” but contends that reduction of active leakage was “investigated solely for the purpose of exploring its effect on uncertainty and process variation—not in conjunction with gate-length biasing.” Br. 37. Patent Owner goes on to argue that “Tsai does not disclose or teach gate-length biasing.” Id. Requester disagrees. Req. Br. 14. As noted by Requester, Tsai recognizes gate-length modification as “mainstream active leakage reduction technique[].” Req. Br. 14; Ex. 11, ¶ 3 Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 38 (“increasing the gate length not only reduces the leakage power but also reduces the leakage and delay uncertainties”). Moreover, as also noted by Requester, “Tsai is replete with discussion of how the gate change affects leakage power in addition to power uncertainties or delay uncertainties. For example, FIG. 3 reproduced below illustrates modification of gate-lengths and . . . [the] effect of [gate-length modification] on ‘Leak[age] Power”—a separately plotted parameter.” Req. Br. 14; Ex. 11, ¶ 4.1.1. Figure 3 of Tsai is reproduced below: Tsai teaches that “[i]t can be seen [from FIG. 3] that increasing the gate length by 10% of minimum gate length achieves 85%, 55%, and 30% in leakage savings, leakage uncertainty reduction and delay uncertainty reduction, respectively.” Req. Br. 14 n.23; Ex. 11, ¶ 4.1.1 (col. 1). Patent Owner also argues that Tsai is essentially irrelevant because Tsai is concerned with “area.” Br. 37-38. According to Patent Owner, Tsai’s area concern is inconsistent with the nature of gate-length biasing of an integrated digital circuit. Br. 38. Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 39 We agree with Requester that claim 1 is not “limited to being ‘area constrained.’” Req. Br. 15. Patent Owner maintains that Tsai does not teach how to implement “gate-length biasing.” Br. 38. Requester correctly points out that implementation is not a process step in claim 1. Req. Br. 15. Lastly, Patent Owner suggests that Rogenmoser and Tsai cannot be “combined.” Br. 38. Rogenmoser and Tsai both describe adjustment of the size of a transistor gate. Rogenmoser exemplifies gate-width adjustment, while Tsai exemplified gate-length adjustment. Both references adjust to achieve specific properties for transistors. We find that both references relate to the same field of endeavor and on that basis the teachings in both references may be combined and considered in connection with the obviousness issue before us. E. Long-felt Need and Commercial Success Patent Owner argues that “secondary considerations” of satisfying a long-felt need and subsequent commercial success weigh in favor of non- obviousness. Br. 39-42. Requester disagrees. Req. Br. 16-18. Secondary considerations, including satisfaction of a long-felt need and commercial success can have a significant impact on an obviousness analysis. See, e.g., The Barbed Wire Patent, 143 U.S. 275, 282 (1892); In re Cyclobenzaprine Hydrochloride Extended-Release Capsule Patent Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 40 Litigation, 676 F.3d 1063, 1075-1080 (Fed. Cir. 2012) (long-felt need and commercial success should be considered before ultimate decision made on obviousness); In re Tiffin, 443 F.2d 394 (CCPA 1971), modified on reh’g, 448 F.2d 791 (CCPA 1971); Ex parte Artsana USA, Inc., 2014 WL 4090808 (PTAB Aug. 18, 2014) (finding commercial success to be entitled to considerable weight); Murata Mfg. Co., Ltd. v. Synqor, Inc., 2014 WL 1397381 *11-14 (PTAB Apr. 10, 2014) (same). In the case before us, the Examiner declined to give controlling weight to Patent Owner’s evidence of long-felt 26 want and commercial success. RAN, pp. 28-30. The “secondary considerations” evidence is based on the testimony of Mr. Becker (Ex. 12) and four press releases (Exs. 19-22). Requester responds relying on testimony of Mr. Hou (Ex. E2). All the evidence has been considered. Mr. Becker testified that “[t]hird party requester TSMC currently holds an exclusive license, within a defined field-of-use [not described], to practice the ʼ211 patent.” Ex. 12, ¶ 30. According to Mr. Becker, “[t]here have been over one hundred separate customer designs [none described] enhanced by Tela’s gate-length 26 A showing of a satisfaction of a long-felt want generally requires evidence [not present in the case before us] that those attempting to solve the long-felt want were unable to do so notwithstanding their knowledge of the prior art. Toledo Pressed Steel Co. v. Standard Parts, Inc., 307 U.S. 350, 356 (1939) ("[b]ut it does not appear that either was familiar with the relevant prior art"); In re Allen, 814, 324 F.2d 993, 997 (CCPA 1963) (same). Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 41 biasing technology under the TSMC’s license of the ʼ211 patent. These designs, with [Patent Owner] Tela’s gate-length biasing included, have result in the production and shipment of over 350,000 300mm wafers representing over 100 million parts.” Id., ¶31. Patent Owner points out (Br. 39) that a Press Release dated 2008/04/15 (which we take to mean April 15, 2008) states (Ex. 19, p. 2 of 3): Power leakage has long been an issue for IC [integrated circuit] design, especially in the small geometries,” “said Fu-Chieh Hsu, vice president of Design & Technology Platform at TSMC. “With the Blaze DFM technology, we now have a tool that discovers areas for optimization that was not previously possible. This means we can provide customers with the ability to minimize power leakage problems, thereby saving their time and money to meet the market demand.” According to the Press Release, TSMC announced the it was able to “deliver substantial reduction in leakage power above and beyond existing techniques already employed in . . .[a] chip.” Br. 40; Ex. 19, p. 1. In Press Release dated 2009/02/24 (which we take to mean Feb. 24, 2014), Mr. Hsu states that “[w]e are very pleased to Tela’s move to acquire Blaze DFM and look forward to working with them to jointly support and enhance this unique power consumption reduction capability to our customers.” Br. 40, Ex. 20, p. 1. According to Patent Owner, “commercial success is attributable, at least in part, to the inventions defined by the claims of Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 42 the ʼ211 patent, as TSMC . . . has publicly announced. Br. 41; Ex. 22, p. 1 (“Power Trim is a first-of-its-kind technology that blends a layer of design technology with advanced semiconductor processing to optimize a design’s power leakage. Tela Innovations provides the patented Power Trim technology and services under an exclusive license to TSMC.”). Exhibit 21 shows that TSMC refers to its program as a program implementing patented technology. Br. 41; Ex. 21, p. 1 (“PowerTrim is a patented power optimization technology platform based on TSMC’s advanced manufacturing processes to reduce leakage in device manufactured on TSMC 90 nm and small process geometries.”). Requester in rebuttal relies on testimony of Dr. Hou, a TSMC Vice-President in charge of Design and Technology Platform. Ex.E2, ¶ 1. According to Dr. Hou, TSMC’s decision to include BLAZE MO in the Power Trim Service stemmed from a business cost-benefit analysis, rather than from any merits of the ʼ211 patent (Ex. E2, ¶ 10), a fact relied upon by the Examiner (RAN, p. 29). Although it is not entirely clear what is meant by BLAZE MO, we assume that BLAZE MO is technology based on the ʼ211 patent. Dr. Hou testified that a majority of TSMC’s customers do not use the BLAZE MO product offered with the Power Trim Service (Ex. E2, ¶ 12) a fact relied upon by the Examiner (RAN, p. 28). Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 43 As a result, according to Dr. Hou some “customers have implement and completed CD [critical dimension] biasing, including gate-length biasing, all before tapeout. Ex. E2, ¶13. The Examiner observed that (RAN, p. 28): Patent Owner has failed to present any sales data or market share data that shows actual success in the market. Nor has Patent Owner provided any information regarding the actual commercial value of the license. Evidence of an exclusive license to one licensee, without other evidence, is not enough by itself to show commercial success. The Examiner also found that (RAN, pp. 28-29): [i]t is questionable how “objective” a marketing statement, designed to promote products and services, made by an exclusive licensee can be. The Examiner also found that the evidence failed to establish a sufficient nexus (RAN, p. 29): 27 Assuming arguendo that the shipment of 350,000 wafers represents commercial success, for which there is no reliable evidence because there is [no] corroborating evidence and no data to serve as a reference point or any other date to measure the level of success, there is no evidence that links the shipment of 350,000 wafers to the 27 In re Fielder, 471 F.2d 640, 642 (CCPA 1973) (there must be a nexus between commercial success and invention); Solder Removal Co. v. United States International Trade Commission, 582 F.2d 628, 199 USPQ 129 (CCPA 1978) (same). Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 44 use of PowerTrim Service that has been enhanced with the patented aspect of the gate CD biasing technology. Lastly, the Examiner noted that the evidence suggests that TSMC’s customer who used the PowerTrim Service did so because it was frequently provided without charge. RAN, pp. 29-30; Ex. E2, ¶ 11. The Examiner credited the testimony of Dr. Hou over that of Mr. Becker and the Press Releases. We have no basis for disagreeing with the Examiner’s credibility determinations; indeed, we would make the same credibility determinations were we assessing credibility in the first instance. We, like the Examiner and Requester, have difficulty finding that a sufficient nexus exists between the “commercial” product sold and the claimed subject matter because it is not entirely clear on the record precisely what is involved in the “PowerTrim Service” or the BLAZE MO product. We, like the Examiner, find it difficult to assign much weight to Press Releases, which the Examiner found were documents attempting to obtain customers. We, like the Examiner, also find that the sale of 350,000 units does not establish the extent of the market or market share. 28 28 Sales data standing alone is weak evidence of commercial success. In re Huang, 100 F.3d 135, 139 (Fed. Cir. 1996). Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 45 F. Summary For the reasons given, when the prior art as a whole is weighed against the evidence of long-felt want and commercial success as a whole, on the record before us we hold that the subject matter of claim 1 would have been obvious notwithstanding Patent Owner’s position on long-felt want and commercial success. ORDER Upon consideration of the record, and for the reasons given, it is ORDERED that Patent Owner’s Request for Rehearing is granted to the extent that (1) our Decision dated Mar. 31, 2014 is vacated and (2) a New Decision on Appeal is entered in its place. FURTHER ORDRED that the Examiner’s rejection of claims 1-31 over Rogenmoser and Houston is affirmed. FURTHER ORDERED that the Examiner’s rejection of claims 32-36 over Rogenmoser, Houston and Pramanik is affirmed. FURTHER ORDERED that the Examiner’s rejection of claim 1-31 over Rogenmoser and Tsai is affirmed. FURTHER ORDERED that the Examiner’s rejection of claims 32-36 over Rogenmoser, Tsai and Pramanik is affirmed. FURTHER ORDERED that the Examiner’s rejection of claims 32-36 over Rogenmoser, Tsai and Hsueh is affirmed. FURTHER ORDERED that the time for seeking rehearing of this New Decision on Appeal is set out in 37 C.F.R. § 71.79. FURTHER ORDERED that the time for seeking judicial review of this New Decision on Appeal is set out in 37 C.F.R. § 90.3 Appeal 2014-000592 Reexamination Control 95/001,832 Patent US 7,441,211 B1 46 FURTHER ORDERED that requests for extensions of time in this proceeding are governed by 37 C.F.R. §§ 1.956. AFFIRMED Patent Owner: STERNE, KESSLER, GOLDSTEIN & FOX P.L.L.C. 1100 NEW YORK AVENUE, N.W. WASHINGTON, DC 20005 Third Party Requester: HAYNES AND BOONE, LLP 2323 VICTORY AVENUE, SUITE 700 DALLAS, TX 75219 ack Claim Chart Cc-o Attorney Docket No. 34789.54 U.S. Patent No. 7,441,211 30. Claims 1-31 are unpatentable under 35 U.S.c. 103 as being obvious over Rogenmoser in view of Tsai Reasons to combine these references are provided where appropriate. U.S. Patent No. 7,441,211 Rogenmoser and Tsai 1.0 A gate-length biasing method for modifying a nominal cell of an integrated digital circuit, the nominal cell containing one or more transistors, the method comprising the steps of: Rogenmoser provides a method for transistor size optimization. See title. "Transistor size optimization is a traditional obligation in VLSI (Very Large Scale Integration) design. It is used to improve the perfonnance of a circuit to achieve a design goal in a specific technology. This design goal can either be boosting operating speed, lowering power consumption, or lowering area requirements. In this context the netlist of the circuit is already detennined, only the width and the length ofthe MOS (Metal Oxide Semiconductor) transistors can be adjusted." Pg. 849. "In general, circuit designers manually optimize circuits by trial and error using an accurate circuit simulator such as SPICE. '" Still, it is a tedious work of assigning sizes (i.e. width and length of the channel ofthe MOS) to all transistors, verifying the perfonnance by simulation, and starting this process over again by reassigning new transistor sizes. An experienced designer may obtain acceptable results after a few iterations, while less trained designers may spend much more time optimizing even a small circuit. Automated tools are therefore a welcome alternative." pg. 849-50. Rogenmoser then discusses automated transistor sizing tools / methods, including those discussed below. Furthennore, the preamble of claim 1 is a mere intended use, and does not provide patentable weight. If the body of a claim fully and intrinsically sets forth all of the limitations of the claimed invention, and the preamble merely states, for example, the purpose or intended use of the invention, rather than any distinct definition of any of the claimed invention's limitations, then the preamble is not considered a limitation and is of no significance to claim construction. Pitney Bowes, Inc. v. Hewlett-Packard 2 l.l Claim Chart CC-D Attorney Docket No. 34789.54 U.S. Patent No. 7,441,211 U.S. Patent No. 7,441,211 Rogenmoser and Tsai Co., 182 F.3d 1298, 1305 (Fed. Cir. 1999). To the extent the Examiner finds the preamble a limiting element, Rogenmoser suggests that the length of the transistor can be adjusted. See pg. 849, first paragraph. To the extent that Rogenmoser does not specifically discuss gate-length biasing, the relevant functionality is obvious in light ofTsai as discussed below. See element 1.4. (a) selecting a trial set ofone or One optimization method described by Rogenmoser more transistors in the nominal is a stochastic optimization method using Monte cell, each selected transistor Carlo analysis. having a nominal gate-length~ "The first stochastic optimization method is based on [Wur93], where transistors of Domino CMOS circuits were sized in an incremental way. The procedure looks as follows: 1. Assign a set of random sizes for each transistor 2. Evaluate the solution (calculate the fitness function) 3. Increase, decrease each sizes of the set by a fixed step (minimum feature size) or do not change it at all (with equal probability) 4. Evaluate the solution; if this set has a better fitness continue with this set, otherwise use the previous one. 5. If maximum number of evaluations is reached stop, else goto 3" Pg. 853, emphasis added. The '211 patent describes: "The term 'nominal gate- length' refers to the gate-length of an unbiased device." 4:66-67. Thus, step 1 above provides for selecting a trial set ofone or more transistors in the nominal cell, each selected transistor having a nominal gate-length. Rogenmoser illustrates determining a trial bias lengths for the selected trial set of (b) determining trial small bias 1.2a amount. transistors, the trial small bias "The first stochastic optimization method is based on lengths all less than a predefined [Wur93], where transistors of Domino CMOS fraction of the nominal gate- circuits were sized in an incremental way. The 3 Claim Chart CC-D Attorney Docket No. 34789.54 U.S. Patent No. 7,441,211 U.S. Patent No. 7,441,211 Rogenmoser and Tsai length; procedure looks as follows: l. Assign a set of random sizes for each transistor 2. Evaluate the solution (calculate the fitness function) 3. Increase, decrease each sizes of the set by .§ fixed step (minimum feature size) or do not change it at all (with equal probability) 4. Evaluate the solution; if this set has a better fitness continue with this set, otherwise use the previous one. 5. If maximum number of evaluations is reached stop, else goto 3" Pg. 853, emphasis added. In step 3 of the Monte Carlo optimization method, Rogenmoser teaches that the transistor sizing is increased/decreased (biased) by a "fixed step", which is a predefined fraction of a gate-length. "The step size is first set to four times minimum feature size. After the first third of the optimization it is reduced to twice the minimum feature size and to the minimum for the last third." pgs. 853-54. (b) [determining trial small bias Tsai illustrates a small bias length, which is less than lengths for the selected trial set of 1.2b a predefined fraction of the nominal gate-length. transistors,] the trial small bias Tsai illustrates a leakage reduction technique which lengths all less than a predefined includes "gate length biasing by increasing gate fraction of the nominal gate- length by 10% of the minimum gate length." Table length; 2. Tsai also teaches "The optimized gate length is the trade-off between power, delay and area. Simulation results in Fig. 3 show the achievable leakage power savings and leakage/delay uncertainties. In our experiment, we increase the gate length by 10% as point A shown in Fig. 3 ...." Section 4.1.1. 4 Claim Chart CC-D Attorney Docket No. 34789.54 U.S. Patent No. 7,441,211 U.S. Patent No. 7,441,211 Rogenmoser and Tsai 1 l-O! I,: I,I~ I,l 1.!5 1.3 1,]5 1,4 1.4' U Reasons to Combine One ofordinary skill in the art would have had reason to modify the disclosure of Rogenmoser with the teachings ofTsai. One ofordinary skill in the art would have had reason to combine the teachings ofTsai and Rogenmoser as they are both directed to the same goal, optimization of transistor size based performance criteria on delay and power. The aspect of the transistor that is sized, and the amount of the trial sizing, during the optimization is merely simple substitution with predictable results. Like Rogenmoser, Tsai contemplates using Monte Carlo analysis in determining a performance for a transistor sizing. See Tsai section 1. Tsai teaches finding an "optimized gate length" but does not specifically describe its method for determining a trial biased length to find the optimized length. Tsai does, however, illustrate several different trial biased lengths were used and evaluated for their leakage and delay. See Fig. 3. Moreover, Rogenmoser provides an exemplary methodology to optimize the determination of the amount of the gate length change. A finding of obviousness is supported by combining prior art elements according to known methods to provide predictable results, as is provided in the present combination, The optimization method of Rogenmoser performs the same function when applying the teachings of Tsai. This merely applies a known technique, i.e., use IC design methodology for ! optimization, to a known device ready for 5 1.3 Claim Chart CC-D Attorney Docket No. 34789.54 U.S. Patent No. 7,441,211 U.S. Patent No. 7,441,211 Rogenmoser and Tsai improvement to yield predictable results. See MPEP 2143. The optimizing the transistor length using the Rogenmoser method would also provide the exact same benefits to Rogenmoser. The MPEP states that a conciusion of obviousness is supported by the "use ofknown technique to improve similar devices (methods, or products) in the same way." MPEP § 2141.III.(C). "The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no (c) adjusting the gate-lengths of the selected trial set of transistors by the small bias lengths to create a trial biased cell; change in their respective functions, and the combination yielded nothing more than predictable results to one ofordinary skill in the art." MPEP 2143 citing KSR. Rogenmoser illustrates adjusting the dimension of a transistor to create a trial cell. "The first stochastic optimization method is based on [Wur93], where transistors of Domino CMOS circuits were sized in an incremental way. The procedure looks as follows: 1. Assign a set of random sizes for each transistor 2. Evaluate the solution (calculate the fitness function) 3. Increase l decrease each sizes of the set b:y a fixed step (minimum feature size) or do not change it at all (with equal probability) 4. Evaluate the solution; if this set has a better fitness continue with this set, otherwise use the previous one. 5. If maximum number ofevaluations is reached stop, else goto 3" Pg. 853, emphasis added. Thus, Step 3 of the Monte Carlo optimization method of Rogenmoser teaches that the transistor size is 6 1.4 Claim Chart CC-D Attorney Docket No. 34789.54 U.S. Patent No. 7,441,211 U.S. Patent No. 7,441,211 Rogenmoser and Tsai increased/decreased by an amount (biased). The '211 patent describes: "The phrase 'biasing a device' implies adjusting the gate-length of the device slightly." 4:65-66. In the absence of further recitation or disclosure, to the extent required by the claimed "bias", the relative tenn "slightly" is provided by the method of Rogenmoser. See, MPEP 2173.05(b). Tsai illustrates determining an optimized gate length to a current best biased cell with (d) comparing the trial biased cell based on a tradeoff between reducing a leakage respect to a predefined goal power for the biased cell and reducing an impact on including a tradeoff between timing delays. reducing a leakage power for the Tsai describes "The optimized gate length is the biased cell and reducing an trade-off between the power, delay and area. impact on timing delays for the Simulation results in Fig. 3 show the achievable digital circuit; and leakage power savings and leakage/delay uncertainties. In our experiment, we increase the gate length by 10% as point A shown in Fig. 3. It can be seen that increasing the gate length by 10% of minimum gate length achieves 85%, 55%, and 30% in the leakage savings, leakage uncertainty reduction and delay uncertainty reduction, respectively." Section 4.1.1. Fig. 3 illustrates "Design trade-off for optimized gate length" including leakage uncertainty, leakage power, EDP (energy-delay product), and Delay Uncertainty. " , _M...__.....:..~~____.. ____: __ .... L.'klge u.1ctnllnly .:\ ... ...,... -r Ltak P6\Wf ., . ..... " ... EDP\'" ~~ lk\l;iIrtainiy 1 :Jr' I.: W 1.2 125 I,) 1.)5 I.a IAj Lj NOflmltiHd Galli L8ngtt1 Tsai also describes "All the evaluated techniques reduce dynamic/leakage power at the cost of delay penalty." Section 4.3. "Many active leakage power reduction techniques are based on adiusting transistor 7 1.5 Claim Chart CC-D Attorney Docket No. 34789.54 U.S. Patent No. 7,441,211 U.S. Patent No. 7,441,211 Rogenmoser and Tsai physical parameters ... Their impact on the delay and power uncertainties should be considered when optimizing yield, performance, and power." Tsai at Section 1. Moreover, Tsai recognizes that it was known in the prior art the "impacts of the dynamic power management techniques on the delay variations"and fabrication yield." Tsai at Section 1. "We investigate the uncertainty-power-delay trade- off and suggest techniques for designs targeting different requirements." Tsai at Abstract. "Increasing Gate Length From equation (1), increasing the gate length not only reduces the leakage power but also reduces leakage and delay uncertainties ...." Tsai at Section 3. "Among the variations in transistor parameters, variations in gate length and threshold voltage are found to have most significant impacts on circuit performance and power consumption." Tsai at Section 2, citations omitted. Rogenmoser illustrates an optimization method biased cell based on the (e) updating the current best which includes updating a current best biased cell comparison. based on the comparison of a trial cell and current best ceiL "The first stochastic optimization method is based on [Wur93], where transistors of Domino CMOS circuits were sized in an incremental way. The procedure looks as follows: 1. Assign a set of random sizes for each transistor 2. Evaluate the solution (calculate the fitness function) 3. Increase, decrease each sizes of the set by a fixed step (minimum feature size) or do not change it at all (with equal probability) 4. Evaluate the solution; if this set has a better fitness continue with this set, otherwise use the previous one. 5. If maximum number of evaluations is reached stop, else goto 3" 8 Claim Chart CC-D Attorney Docket No. 34789.54 U.S. Patent No. 7,441,211 U.S. Patent No. 7,441,211 Rogenmoser and Tsai Pg. 853, emphasis added. Thus, Step 4 of the Monte Carlo optimization method of Rogenmoser teaches updating the current optimum (best) transistor size if the comparison shows the biased transistors have "better fitness." The Monte Carlo optimization process is iterative and continues (see step 5) to bias the devices. 2.0 The method of claim I wherein the step of adjusting the gate- lengths of the selected transistors comprises: increasing the gate- lengths of a majority of the selected transistors by the small bias lengths. See claim 1. Rogenmoser also discloses biasing (e.g., increasing) the gate-lengths in a majority of selected transistors. "All transistors in a circuit are sized by the GA or MC [Monte Carlo] except predefined minimum sized transistors ... " pg. 850. See also, Table I at pg. 851; and reciting increase, decrease each sizes at step 3 ofpg. 853. Furthermore, to the extent that Rogenmoser does not specifically disclose increasing "small bias lengths" under the broadest reasonable interpretation of the claim term, it would have been obvious to use the methodology of Rogenmoser to include increasing the gate-lengths of a majority of selected transistors by a small bias amount. Furthermore, the recitation of majority of the selected transistors is merely an exercise in grouping, in particular as claim 1 defines the selected transistors as including a group defined by a single transistor. 3.0 The method of claim 2 wherein the step of increasing the gate- lengths of the transistors is based on reducing a leakage power for the biased cell. Tsai describes the relevant functionality. See claims 1 and 2. "The optimized gate length is the trade-off between the power, delay and area. Simulation results in Fig. 3 show the achievable leakage power savings and leakage/delay uncertainties. In our experiment, we increase the gate length by 10% as point A shown in Fig. 3. It can be seen that increasing the gate length by 10% ofminimum gate length achieves 85%, 55%, and 30% in the leakage savings, leakage uncertainty reduction and delay uncertainty reduction, respectively." Section 4.1.1. See also, FIG. 5, compare "LB" and "Orig". See also, section 4.3 including "The results show that increasing the gate length by 1 0% achieves 86% savings in leakage 9 Claim Chart CC-D Attorney Docket No. 34789.54 U.S. Patent No. 7,441,211 U.S. Patent No. 7,441,211 Rogenmoser and Tsai power and 86.6% yield." "BL reducers} leakage and delay uncertainties". Tsai at Section 4.3. See also, claim 2, claim 1, element 1.4. Furthermore, the '211 patent in its Background of the Invention, illustrates as admitted prior art that "gate leakage is linearly proportional to gate-length, and subthreshold leakage has an exponential dependence on gate-length." 1 :55-57, see also, 2:52-55. 4.0 The method ofclaim 2 wherein See, claims 2 and 3. the step of increasing the gate- Tsai recognizes increasing gate-lengths based on lengths of the transistors is based reducing leakage power variability. See FIG. 1.on reducing a leakage power "increasing the gate length not only reduces the variability for the digital circuit. leakage power but also reduces the leakage and delay uncertainties." Tsai at Section 3. Tsai describes "The optimized gate length is the trade-off between the power, delay and area. Simulation results in Fig. 3 show the achievable leakage power savings and leakage/delay uncertainties. In our experiment, we increase the gate length by 10% as point A shown in Fig. 3. It can be seen that increasing the gate length by 10% of minimum gate length achieves 85%, 55%, and 30% in the leakage savings, leakage uncertainty reduction and delay uncertainty reduction, respectively." Section 4.1.1. See also, FIG. 3, section 4.3, Table 3. Furthermore, the '211 patent recognizes in its Background of the Invention section, as admitted prior art, that leakage variability is a known "design concern". See 1:41-49. Thus, one of ordinary skill in the art would have recognized leakage power variability as an design goal for the optimization method of Rogenmoser in view ofTsai. The method of claim 1 wherein See claim 1, claim 2, claim 3. the step of adjusting the gate 5.0 Furthermore, the claim recites a set of transistors lengths of the selected transistors including one transistor. Thus, increasing the gate comprises: increasing the gate- length of this one transistor is increasing each of the lengths of each of the selected selected transistors. The recitation is merely an transistors by the small bias activity in grouping. lengths. I 10