Ex Parte 7402855 et al

Patent Trial and Appeal Board

Jul 15, 2015

95001359 (P.T.A.B. Jul. 15, 2015)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,359 05/21/2010 7402855 93714-000200US-790979 9398
20350 7590 07/16/2015
KILPATRICK TOWNSEND & STOCKTON LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO, CA 94111-3834
EXAMINER
MCNEIL, JENNIFER C
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
07/16/2015 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

KILOPASS TECHNOLOGY, INC.,
Requester,

v.

SIDENSE CORPORATION,
Patent Owner.
____________

Appeal 2014-001851
Reexamination Control 95/001,359
Patent 7,402,855 B2
Technology Center 3900
____________

Before KARL D. EASTHOM, KEVIN F. TURNER, and STEPHEN C. SIU,
Administrative Patent Judges.

SIU, Administrative Patent Judge

DECISION ON APPEAL
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Reexamination Control 95/001,359
Patent 7,402,855 B2

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In an earlier Decision (2012-008939) mailed October 12, 2012
(“Decision”), the Board reversed the Examiner’s decision favorable to the
patentability of claims 1–11 of U.S. Patent No. 7,402,855 B2 (“the’855
patent”). Decision 14. Our reversal of the Examiner’s decision in
connection with the prior art rejections of claims 1–11 was designated new
grounds of rejection pursuant to 37 C.F.R. § 41.77(b).
Patent Owner elected to reopen prosecution, proposed amendments to
claim 1, and canceled claims 6–8. PO Req. 2–4.
1
Requester filed comments
pursuant to 37 C.F.R. § 41.77(c) in response to Patent Owner’s initial
request to reopen prosecution.
2
In accordance with 37 C.F.R. § 41.77(d), the
Examiner determines that “[t]he amendment to the claims does not make
them patentable” but that “Patentee has overcome the new grounds of
rejection” on other grounds. Ex’r. Determ. 2, 10.
3

Pursuant to 37 C.F.R. § 41.77(e), Patent Owner and Requester each
submitted a response to the Examiner’s Determination.
4
Pursuant to 37
C.F.R. § 41.77(f), the proceeding has been returned to the Board so that we
may reconsider the matter and issue a new decision.

1
“Request to Reopen Prosecution Under 37 C.F.R. § 41.77(b)(1),” filed
November 13, 2012 (“PO Request” or “PO Req.”).
2
See “Requester’s Reply to Patent Owner’s Response After Board
Decision,” filed December 12, 2012 (“3PR Resp.”).
3
See “Determination under 37 CFR 41.77(d)” mailed February 6, 2013
(“Examiner’s Determination” or “Ex’r Determ.”).
4
“Requester’s Comments Under 37 C.F.R. 41.77(e),” filed March 6, 2013
(“3PR Resp. to Exr’s Determination”) and “Patent Owner Comments Under
37 C.F.R. § 41.77(e),” filed April 8, 2013 (“PO Resp. to Exr’s
Determination”).
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Claim 1 previously recited “isolation devices including transistors,
each having a gate oxide corresponding to said thick gate oxide portion.” In
the previous Decision, we concluded that, even if claim 1 recites transistors
each having a gate oxide with the same thickness as the thick gate oxide
portion, “[i]t follows that it would have been obvious [over the cited
combinations of prior art references] to make the two gate oxides the same
thickness . . ..” Decision 9.
Patent Owner now amends claim 1 to recite transistors, each having a
gate oxide “identical to said thick gate oxide portion and the thin gate oxide
portion of the anti-fuse is identical to a gate oxide of a low voltage transistor
formed on the substrate.” Patent Owner also argues that “all claims pending
upon entry of this amendment would be in condition for allowance.” PO
Request 19. Amended claim 1 follows:
1. (Amended) An anti-fuse memory array comprising:
a plurality of anti-fuse transistors arranged in rows and columns, each
anti-fuse transistor including
a polysilicon gate over a channel region in a substrate, the
channel having a preset length;
a diffusion region proximate to a first end of the channel region;
a variable thickness gate oxide between the polysilicon gate and
the substrate, the variable thickness gate oxide having a thick gate
oxide portion extending from the first end of the channel region to a
predetermined distance of the preset length, and a thin gate oxide
portion extending from the predetermined distance to a second end of
the channel region,
an oxide breakdown zone proximate to the second end of the
channel region fusible to form a conductive link between the
polysilicon gate and the channel region;
bitlines coupled to the diffusion regions of a column of anti-
fuse transistors;
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a sense amplifier coupled to a pair of the bitlines through
isolation devices, said isolation devices including transistors, each
having a gate oxide [corresponding] identical to said thick gate oxide
portion, and the thin gate oxide portion of the anti-fuse is identical to a
gate oxide of a low voltage transistor formed on the substrate; and
wordlines coupled to the polysilicon gates of a row of anti-fuse
transistors.

With respect to Patent Owner’s proposed amendment to claim 1, we
are not persuaded that the proposed amendment to claim 1 is sufficient to
overcome the prior art rejections for at least the reasons set forth by the
Examiner (Ex’r. Determ. 2–6) and as previously explained in the prior
Decision. For example, we are not persuaded by Patent Owner that the cited
combination of prior art references fails to disclose or suggest a gate oxide
with the same (or “identical”) thickness as the thick gate oxide portion for at
least the previously discussed reasons. See, generally, Decision 6–13.
Patent Owner argues that the combination of Peng, Curd, Nguyen, Oh,
and APA fails to disclose or suggest this feature because “[i]t is well known
in this art that maintaining compatibility with standard CMOS process . . . is
a far more challenging endeavor than maintaining CMOS compatibility in
designing new peripheral transistors” and that “Peng ’751 uses process steps
not available in CMOS in forming the thick and thin gate oxides under the
gate of its transistor.” PO Req. 11; PO Resp. to Exr’s Determination 4, 11.
This argument was previously presented and addressed. See, e.g., Decision
10–11. Patent Owner does not provide sufficient further evidence to
demonstrate that claim 1, in fact, recites or otherwise requires “CMOS”
processing and/or that Peng, for example, fails to disclose “CMOS
processes.”
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Patent Owner acknowledges that Peng “discloses an anti-fuse with
thick and thin gate oxides under the gate” but argues that “one skilled in the
art would normally be deterred from forming both the thick and thin gate
oxides of high and low voltage transistors under one gate electrode since
doing so would be in violation of the design rules, and common wisdom
would render such device undesirable.” PO Req. 12, PO Resp. to Exr’s
Determination 11. We are not persuaded by Patent Owner’s argument at
least because, as Patent Owner points out, Peng discloses this feature.
Patent Owner also argues that “while Peng clearly wanted to maintain
compatibility with standard CMOS processes . . . he was unable to achieve
that with the thick and thin gate oxide embodiment.” PO Req. 12, PO Resp.
to Exr’s Determination 12. As previously discussed, “Peng discloses CMOS
processes throughout.” Decision 11 (citing Peng 5:53-57, 7:23-33; accord
Van Buskirk ¶ Declaration 8). Patent Owner does not demonstrate
persuasively that Peng also discloses the inability to achieve “CMOS
processes.” Also, as previously discussed, Patent Owner does not
demonstrate that claim 1 recites or otherwise requires “CMOS processes.”
Patent Owner also argues that “Nguyen provides no indication as to
whether the gate oxide of the isolation transistor 310 is ‘identical’ to the gate
oxide in Nguyen’s memory cells” and that “Nguyen nowhere suggests
making the oxides in the high voltage transistors and in the memory cells
identical.” PO Req. 12–13; PO Resp. to Exr’s Determination 13. We are
not persuaded by Patent Owner for at least the previously stated reasons
(Decision 12) and for reasons set forth by the Examiner. Ex’r. Determ. 5–6.
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Patent Owner argues that “Kim provides no indication as to whether
isolation transistors NM4-NM6 have any structural commonality with Kim’s
memory cells. PO Req. 14, PO Resp. to Exr’s Determination 13. Claim 1
stands rejected as obvious over the combination of Peng and Kim, rather
than Kim in isolation. One cannot show nonobviousness by attacking
references individually where the rejections are based on combinations of
references. In re Keller, 642 F.2d 413 (CCPA 1981); In re Merck & Co.,
Inc., 800 F.2d 1091 (Fed. Cir. 1986). We are not persuaded by Patent
Owner’s argument.
The Examiner states that “while Examiner does not agree with
Patentee’s position with regard to the thicknesses of the gate oxides, it is
nonetheless, Examiner’s position that Patentee has overcome the new
grounds of rejection on the basis of the arguments [and IEEE dictionary
evidence] directed to the terms ‘bitline’ and ‘wordline’ not being
interchangeable.” Ex’r. Determ. 2, 6–10. Claim 1 recites “bitlines coupled
to the diffusion regions of . . . transistors.” Patent Owner argues that Peng
fails to disclose such a “bitline.” PO Resp. to Exr’s Determination 19. The
Examiner concurs with Patent Owner. See Ex’r. Determ. 10–11. However,
Peng discloses a “memory array . . . laid out in a grid” with “the
crosspoint[s]” including “MOS transistor[s] having . . . its source connected
to a row line R1.” Peng 5:33-37, 6:26. In other words, the “row line” of
Peng is coupled to the diffusion region of transistors. Because both the “row
line” of Peng and the claimed “bitline” are connected to diffusion regions of
transistors (e.g., source/drain), we are not persuaded by Patent Owner or the
Examiner of a difference between Peng and claim 1.
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Patent Owner argues that a dictionary definition (i.e., the IEEE
dictionary definition) of a “bitline” requires that the bitline “connect[] the
memory cell drain” and that Peng fails to disclose a “bitline” that connects
the memory cell drain. PO Resp. to Ex’r Determination 17. We are not
persuaded by Patent Owner’s argument because Patent Owner does not point
out sufficient differences between the “bitline” of claim 1 that is coupled to
the diffusion regions of transistors and the row line of Peng that is also
coupled to the diffusion regions of transistors. Patent Owner also argues that
the row line of Peng differs from the claimed “bitline” that is coupled to the
diffusion regions of transistors because Peng refers alternatively to the “row
line” by the term “wordline.” However, Patent Owner does not demonstrate
that the “row line” is no longer coupled to the diffusion regions of transistors
when referred to arbitrarily as a “bitline.” Patent Owner’s proffered
definition further defines a “bit-line” as “[t]he line that connects the memory
cell drain to the sense amplifier during the read cycle and to a data line or
latch during a write cycle.” See Ex’r Determ. 6. Claim 1 does not recite a
drain, a latch, and a sense amplifier, and we decline to import such
limitations from an extrinsic source that might otherwise distinguish a bit
line from a word line.
Claim 1 also recites “wordlines coupled to the . . . gates of . . .
transistors.” Based on a dictionary definition (i.e., the IEEE dictionary
definition) and the Taylor Declaration, Patent Owner argues that Peng fails
to disclose such “wordlines” (i.e., lines coupled to the gates of transistors).
PO Resp. to Exr’s Determination 17–18; Ex’r Determ. 6. The Examiner
concurs with Patent Owner’s conclusion. See Ex’r. Determ. 10–11.
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However, even upon consideration of the dictionary definition and the
Taylor Declaration, we are still not persuaded by the Examiner and Patent
Owner. Peng discloses crosspoints in a memory array having transistors that
have “its gate connected to a column line.” Peng 5:33–35. Patent Owner
does not demonstrate persuasively a patentable difference between the
wordlines coupled to the gates of transistors, as recited in claim 1, and the
column lines of Peng that are also coupled to the gates of transistors.
Patent Owner argues that because Peng also refers to the column line
as a “bitline,” the column line of Peng somehow differs from the claimed
wordline. See, e.g., PO Resp. to Exr’s Determination 17–18. For reasons
similar to those above, we are not persuaded by Patent Owner’s argument.
Patent Owner does not demonstrate sufficiently that the column line of Peng
is no longer connected to the gates of transistors, as recited in claim 1, when
the column line is referred to arbitrarily as a “wordline.” In fact, as
previously described, Peng discloses that the column line is connected to the
gates of transistors.
Patent Owner argues that “if the Peng reference was modified so that
the ‘bitline’ and ‘wordline’ are interchanged, then the memory cell described
in Peng would be inoperable.” PO Resp. to Exr’s Determination 18. We are
not persuaded by Patent Owner’s argument at least because Patent Owner
does not demonstrate sufficiently that a “row line” and “column line” (of
Peng) would function differently if referred to by alternative names, such as
“wordline” and “bitline,” respectively, or “bitline” and “wordline,”
respectively. In either case, voltages are applied selectively to select a
desired memory cell in an array. See, e.g., Peng 5:27–40, 5:45–49, 6:26–31.
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The claims themselves do not require any structural difference when
the words “bitline” and “wordline” are interchanged in the claims.
Furthermore, notwithstanding that Patent Owner argues that the words mean
something to an ordinary artisan, Patent Owner does not explain, what, if
any, structural elements would be incorporated from its proposed definitions
(of “bitline” and “wordline”) into the claims. Therefore, apart from an
arbitrary choice of interchanging words, if these claims as written would be
allowed, the record would not show what the claims encompass and how
they distinguish over the prior art. During prosecution, Patent Owner has a
duty to “make [its] intended meaning explicitly clear.” In re Morris, 127
F.3d 1048, 1056 (Fed. Cir. 1997)) (“The problem in this case is that the
appellants failed to make their intended meaning explicitly clear. . . . Such
evasiveness we cannot condone, particularly when the public must rely on
the written record to define the resulting property right.”) Under Patent
Owner’s theory, a would-be infringer simply could add the word “bitline”
where Patent Owner’s marketed product corresponds to its claimed
“wordline” and vice versa to avoid infringement of Patent Owner’s claims.
In any event, even if the words “bitline” and “wordline,” as claimed,
carry some sort of implicit voltage or other structural distinction, we further
note that APA discloses a “bitline” that is connected to the source/drain of a
transistor and a “wordline” that is connected to the gate of a transistor.
Spec. Fig. 1 (Prior Art). The combination of the known feature of selecting
a desired memory cell in an array by selectively applying voltages to lines
connected to the source/drain of transistors and gates of the transistors,
respectively (where the lines connected to the source/drain of transistors is
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referred to as “wordlines” and the lines connected to the gates of transistors
is referred to as “bitlines,” as disclosed by Peng – see, e.g., Peng 5:27–40,
5:45–49, 6:26–31) with the known feature of performing the same operation
with the names of lines reversed (as disclosed by APA) would have resulted
in no more than the predictable result of selecting a desired memory cell
from an array by applying selective voltages on access lines in the array.
Such a result would have been obvious to one of ordinary skill in the art.
“The combination of familiar elements according to known methods is likely
to be obvious when it does no more than yield predictable results.” KSR Int’l
Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).
DECISION
Based on the foregoing discussion, the Examiner's decision to confirm
claims 1–5 and 9–11 is reversed. In accordance with 37 C.F.R. § 41.77(a)
and (b), and as discussed, reversal of the Examiner's determination
constitutes a NEW GROUND OF REJECTION. The new grounds of
rejection are as follows:
1) Claims 1-5 and 9-11 under 35 U.S.C. § 103(a) as unpatentable over
Peng, Curd, and any one of Oh or APA;
2) Claims 1-5 and 9-11 under 35 U.S.C. § 103(a) as unpatentable over
Peng, Curd, Oh, and APA;
3) Claims 1-5 and 9-11 under 35 U.S.C. § 103(a) as unpatentable over
Peng, Nguyen, and any one of Oh or APA;
4) Claims 1-5 and 9-11 under 35 U.S.C. § 103(a) as unpatentable over
Peng, Nguyen, Oh, and APA;
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5) Claims 1-5 and 9-11 under 35 U.S.C. § 103(a) as unpatentable over
Peng and Kim;
6) Claims 1-5 and 9-11 under 35 U.S.C. § 103(a) as unpatentable over
Peng, Kim, and APA.
Section 41.77(b) provides that “[a] new ground of rejection . . . shall
not be considered final for judicial review.” That section also provides that
Patent Owner, WITHIN ONE MONTH FROM THE DATE OF THE
DECISION, must exercise one of the following two options with respect to
the new grounds of rejection to avoid termination of the appeal proceeding
as to the rejected claims:
(1) Reopen prosecution. The owner may file a response
requesting reopening of prosecution before the examiner. Such a
response must be either an amendment of the claims so rejected
or new evidence relating to the claims so rejected, or both.

(2) Request rehearing. The owner may request that
the proceeding be reheard under § 41.79 by the Board
upon the same record. The request for rehearing must
address any new ground of rejection and state with
particularity the points believed to have been
misapprehended or overlooked in entering the new
ground of rejection and also state all other grounds
upon which rehearing is sought.

In accordance with 37 C.F.R. § 41.79(a)(1), the “[p]arties to the
appeal may file a request for rehearing of the decision within one month of
the date of: . . . [t]he original decision of the Board under § 41.77(a).” A
request for rehearing must be in compliance with 37 C.F.R. § 41.79(b).
Comments in opposition to the request and additional requests for rehearing
must be in accordance with 37 C.F.R. § 41.79(c)-(d), respectively. Under 37
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C.F.R. § 41.79(e), the times for requesting rehearing under paragraph (a) of
this section, for requesting further rehearing under paragraph (c) of this
section, and for submitting comments under paragraph (b) of this section
may not be extended.
An appeal to the United States Court of Appeals for the Federal
Circuit under 35 U.S.C. §§ 141-144 and 315 and 37 C.F.R. § 1.983 for an
inter partes reexamination proceeding “commenced” on or after November
2, 2002 may not be taken “until all parties’ rights to request rehearing have
been exhausted, at which time the decision of the Board is final and
appealable by any party to the appeal to the Board.” 37 C.F.R. § 41.81. See
also MPEP § 2682 (8th ed., Rev. 8, July 2010).
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.
In the event neither party files a request for rehearing within the time
provided in 37 C.F.R. § 41.79, and this decision becomes final and
appealable under 37 C.F.R. § 41.81, a party seeking judicial review must
timely serve notice on the Director of the United States Patent and
Trademark Office. See 37 C.F.R. §§ 90.1 and 1.983.

REVERSED

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ack

For PATENT OWNER:

KILPATRICK TOWNSEND & STOCKTON LLP
TWO EMBARCADERO CENTER
EIGHTH FLOOR
SAN FRANCISCO, CA 94111-3834

For Third Party Requestor:

PERKINS COIE LLP
PATENT-SEA
P.O. BOX 1247
SEATTLE, WA 98111-1247