Ex Parte 7376779 et al

Patent Trial and Appeal Board

Oct 28, 2013

95001475 (P.T.A.B. Oct. 28, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,475 10/27/2010 7376779 ACQI-010/17US
310578-2064
3879
58249 7590 10/28/2013
COOLEY LLP
ATTN: Patent Group
1299 Pennsylvania Avenue, NW
Suite 700
Washington, DC 20004
EXAMINER
BANANKHAH, MAJID A
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
10/28/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

HEWLETT-PACKARD COMPANY and INTERNATIONAL BUSINESS
MACHINES CORPORATION
Requester and Respondent

v.

ACQIS LLC
Patent Owner and Appellant
____________

Appeal 2013-007833
Reexamination Control 95/001,475
Patent 7,376,779 B2
Technology Center 3900
____________

Before STEPHEN C. SIU, BRUCE R. WINSOR, and STANLEY M.
WEINBERG, Administrative Patent Judges.

SIU, Administrative Patent Judge

DECISION ON APPEAL
Appeal 2013-007833
Reexamination Control 95/001,475
Patent 7,376,779 B2

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Patent Owner appeals under 35 U.S.C. §§ 134 and 315 the Examiner’s
decision to reject claims 6-94. Claims 1-5 were cancelled. We have
jurisdiction under 35 U.S.C. §§ 134 and 315. An oral hearing was
conducted on October 7, 2013.

STATEMENT OF THE CASE
This proceeding arose from a request by David L. McCombs on
behalf of Hewlett-Packard Company and International Business Machines
Corporation for an inter partes reexamination of US Patent 7,376,779 B2,
titled “MULTIPLE MODULE COMPUTER SYSTEM AND METHOD,”
and issued to William W.Y. Chu on May 20, 2008 (the “’779 patent”).
The ’779 patent describes multi-module computing (col. 4, l. 9).
Claim 6 reads as follows:
6. A computer system comprising:
a peripheral console comprising a power supply, a first
coupling site and a second coupling site, each coupling site
comprising a connector and a slot, the console being an enclosure
housing the coupling sites,
an Ethernet hub controller powered by the power supply, and
a plurality of computer modules; each computer module
coupled to one of the coupling site through the connector and the slot,
comprising
a CPU,
a graphics controller,
a main memory coupled to the CPU,
an interface controller coupled to a differential signal
channel for communicating an encoded serial data stream of
Peripheral Component Interconnect (PCI) bus transaction,
interconnection circuitry coupled to said CPU, said
interconnection circuitry connectable to the peripheral console;
and
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wherein said CPU is uncoupled from any primary output
circuitry when said interconnection circuitry is disconnected from the
peripheral console; and
wherein each of the computer modules is substantially similar
in design to each other.

The Examiner cites the following references:
Sheets US 4,670,837 June 2, 1987
Pan et al. (“Pan”) US 5,588,850 Dec. 31, 1996
Hong US 5,764,924 June 9, 1998
Cohen et al. (“Cohen”) US 5,737,524 Apr. 7, 1998
Coulson US 5,862,350 Jan. 19, 1999
Bourgeois et al. (“Bourgeois”) US 5,965,957 Oct. 12, 1999
Ahern US 6,088,752 July 11, 2000
Gallagher et al. (“Gallagher”) US 6,742,068 B2 May 25, 2004

Jlchatcom, Inc., www.jlchatcom.com, 1997 (“Chatcom”).

QuantumNet Product Overview, QuantumNet – Next Generation
Computing and Networking Concentrators, www.quantumnet.com, 1997
(“QuantumNet”).

IEEE Std 1355-1995 – Standard for Heterogeneous InterConnect, Oct.
30, 1998 (“OMI”).

Stefan Haas, “The IEEE 1355 Standard: Developments, Performance
and Application in High Energy Physics,” thesis for the degree of Doctor of
Philosophy, University of Liverpool, December 1998 (“Haas”).

Universal Serial Bus Specification, http://poweredusb.org/pdf/
usb11.pdf, 1998 (“USB”).

Patent Owner appeals the Examiner’s rejection of the following
claims under 35 U.S.C. § 103(a):

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Claims 6-15, 21-25, 31-50, and 61-94 over:
1) Gallagher, OMI, and Haas;
2) Gallagher and Hong;
3) QuantumNet, OMI, and Haas;
4) QuantumNet and Hong;
5) Chatcom, OMI, and Haas; or
6) Chatcom and Hong

Claims 16-20, 26-30, and 51-60 over:
1) Gallagher, OMI, Haas, and Sheets;1
2) Gallagher, Hong, and Sheets;
3) QuantumNet, OMI, Haas, and Sheets;
4) QuantumNet, Hong, and Sheets;
5) Chatcom, OMI, Haas, and Sheets; or
6) Chatcom, Hong, and Sheets

Claims 36-40 over:
1) Gallagher, OMI, Haas, and Bourgeois;
2) Gallagher, Hong, and Bourgeois;
3) QuantumNet, OMI, Haas, and Bourgeois;
4) QuantumNet, Hong, and Bourgeois;
5) Chatcom, OMI, Haas, and Bourgeois; or
6) Chatcom, Hong, and Bourgeois

Claims 71-80 over:
1) Gallagher, OMI, Haas, and USB;
2) Gallagher, Hong, and USB;

1 Patent Owner appeals the Examiner’s rejection of claims 16-20, 26-30, and
51-60 as obvious over Gallagher, OMI, and Sheets (PO App. Br. 11).
However, the Examiner rejects these claims as obvious over Gallagher,
OMI, Haas, and Sheets (RAN 3). We assume Patent Owner appeals the
Examiner’s rejection of claims 16-20, 26-30, and 51-60 as obvious over
Gallagher, OMI, Haas, and Sheets.
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3) QuantumNet, OMI, Haas, and USB;
4) QuantumNet, Hong, and USB;
5) Chatcom, OMI, Haas, and USB; or
6) Chatcom, Hong, and USB

Claims 81-85 and 92-94 over:
1) Gallagher, OMI, Haas, and Pan;
2) Gallagher, Hong, and Pan;
3) QuantumNet, OMI, Haas, and Pan;
4) QuantumNet, Hong, and Pan;
5) Chatcom, OMI, Haas, and Pan; or
6) Chatcom, Hong, and Pan

Claims 8, 17, 24, 32, 47, 58, 59, 69, 74, 76-80, 81-85, and 86-89 over
Gallagher, Hong, and Ahern.

Claims 18, 43, 67, and 82 over:
1) Gallagher, Hong, Sheets, and Cohen; or
2) QuantumNet, Hong, Sheets, and Cohen

Claims 31-35, 68, and 83 over:
1) Chatcom, OMI, Haas, and Coulson; or
2) Chatcom, Hong, and Coulson

Claim 28 over:
1) Chatcom, OMI, Haas, Sheets, and Coulson; or
2) Chatcom, Hong, Sheets, and Coulson

Claim 18 over Chatcom, Hong, Sheets, and Cohen; and
Claims 34, 67, and 82 over Chatcom, Hong, and Cohen;
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ISSUE

Did the Examiner err in rejecting claims 6-94?

PRINCIPLES OF LAW

The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co., 383 U.S. 1, 17-
18 (1966).
“The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).

ANALYSIS

Gallagher and Haas
Claim 6 recites “an interface controller coupled to a differential signal
channel for communicating an encoded serial data stream of Peripheral
Component Interconnect (PCI) bus transaction.” Patent Owner argues that
Gallagher fails to disclose or suggest “a ‘differential signal’ channel that
communicates an ‘encoded . . . PCI . . . bus transaction” because, according
to Patent Owner, “standard PCI interfaces are not compatible with PCI
Express Interfaces” (PO App. Br. 14). We disagree with Patent Owner for at
least the reasons set forth by the Requester (see e.g., Comments by Third
Party Requester, filed June 24, 2011 (“3PR Comments”), at 8-9).
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For example, the Examiner does not rely on Gallagher to provide the
disclosure of a “differential signal channel” that communicates an encoded
PCI bus transaction. Instead, the Examiner relies on Haas to provide this
disclosure (RAN 16, 466-467). One cannot show nonobviousness by
attacking references individually where the rejections are based on
combinations of references. In re Merck & Co., Inc., 800 F.2d 1091, 1097
(Fed. Cir. 1986).
Also, while Patent Owner argues that Gallagher fails to disclose a
“PCI Express Interface,” Patent Owner does not indicate where claim 6, for
example, requires a “PCI Express Interface.” (PO App. Br. 14). Claim 6
recites a “(PCI) bus transaction” and “an interface controller” but does not
recite a “PCI Express Interface.”
Patent Owner argues that Haas discloses a “PCI bus controller [that]
interfaces with a standard PCI bus” but “nowhere does Haas . . . teach or
suggest . . . any encoding . . . [of] a PCI bus transaction” (PO App. Br. 14-
15) or that “encoding is carried out with respect to a PCI bus transaction”
(PO App. Br. 15). Claim 6 recites an interface controller for communicating
an encoded serial data stream of PCI bus transaction. Hence, claim 6 recites
encoded data. We disagree with Patent Owner for at least the reasons set
forth by the Requester (3PR Comments at 9-10) and the Examiner (RAN
448-450).
For example, Haas discloses a “PCI-DS interface” that includes a
“PCI bus controller chip” that “interface[s] to the PCI bus” (p. 43, Fig. 27).
Patent Owner does not indicate an explicit definition of the term “encoded”
data in the Specification. In the absence of a specialized definition of the
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term “encoded,” we broadly but reasonably construe the term “encoded”
(with respect to describing data) as would have been understood by one of
ordinary skill in the art in light of the Specification to include data that is
expressed “in terms of a code,” the “code” including data that is
“convert[ed] . . . from one form of representation to another” or
“represent[ed] . . . in symbolic form” .2 Hence, “encoded” data is data that
has been converted or formatted from one form into another desired
representation or format. This broad but reasonable definition comports
with the Specification that discloses a specific example of encoders that
“format the . . . data bits to [another more suitable] form . . .” (col. 16, ll. 13-
14).
The Examiner and Requester equate the “PCI-DS interface” (Fig. 27)
of Haas with the interface controller as recited in claim 6, for example. Haas
discloses that the “PCI-DS interface” interfaces with a PCI bus (p. 43). One
of ordinary skill in the art would have understood that a data bus (such as the
PCI bus of Haas) is used to transmit data and that an interface that interfaces
with the data bus would receive data transmissions from the interfaced bus.
One of ordinary skill in the art also would have understood that a PCI bus
would be used to transmit (or communicate) data pertaining to PCI bus
transactions.
As noted above, encoded data (broadly but reasonably construed as
would have been understood by one of ordinary skill in the art) is data that
has been converted or formatted into a desired representation or format. One

2 IEEE, The Authoritative Dictionary of IEEE Standards Terms, Seventh
Edition, 2000, pp. 182, 379.
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of ordinary skill in the art would have understood that the data received
(from the PCI bus) at the interface in Haas would have been converted or
formatted into a desired representation or format that would be utilized on a
PCI bus because Haas, in fact, discloses both a PCI bus that one of ordinary
skill in the art would have understood transmits or communicates data and
that the PCI bus is connected with the PCI-DS interface (Fig. 27).
Patent Owner argues that Haas fails to disclose that the data
communicated by the “interface controller” (i.e., the PCI-DS interface) is
encoded. However, Patent Owner does not persuasively demonstrate that
the data received from a PCI bus (and “communicated”) by the PCI-DS
interface in Haas is not converted or formatted into a representation or
format suitable for transmission on the PCI bus (i.e., “encoded”). One of
ordinary skill in the art would have understood that data transmitted on a
PCI bus would have been converted or formatted into a desired
representation or format that is compatible with transmission on the PCI bus.
Otherwise, the data would not be able to be successfully transmitted on the
bus, not having been formatted properly for transmission on the bus. Hence,
one of ordinary skill in the art would have understood that the data
transmitted on the PCI bus of Haas and received (and “communicated”) by
the interface of Haas would have been “encoded.”
Patent Owner argues that Haas fails to disclose or suggest “that a PCI
bus transaction is communicated as an encoded serial data stream to the DS-
DE link” (PO App. Br. 16). Claim 6 recites an interface controller for
communicating an encoded serial data stream of PCI bus transaction. As
described above, we disagree with Patent Owner that Haas fails to disclose
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or suggest communicating encoded data (i.e., communicating data that has
been converted or formatted into a representation or format suitable for use).
For example, Haas discloses that in the PCI-DS interface (Fig. 27),
signals “are routed to the FPGA” (p. 43). One of ordinary skill in the art
would have understood that “routing” data in the PCI-DS interface would
have included “communicating” data because in both cases, data is
transmitted from one location to another. In addition, as described above,
the data that is communicated in the PCI-DS interface of Haas is encoded
data because, as previously explained, the data received from a PCI bus (Fig.
27) has been converted or formatted into a desired representation or format
that is compatible with transmission on the PCI bus (i.e., “encoded”).
Claim 9, for example, recites that the serial bit stream of PCI bus
transaction comprises encoded PCI address and data bits. Patent Owner
argues that Haas fails to disclose or suggest that “the encoded PCI bus
transaction comprises ‘encoded PCI address . . . bits’” (PO App. Br. 17).
Hence, Patent Owner argues that the data stream received at and
communicated by the “PCI-DS interface” of Haas does not comprise address
bits and that the data received is not “encoded.” We disagree with Patent
Owner for at least the reasons set forth above and by the Requester (3PR
Comments at 10-11) and the Examiner (RAN 455-457).
Patent Owner also has not persuasively demonstrated that the data
stream received at and communicated by the “PCI-DS interface” of Haas
does not include address bits. As described above, in Haas, the “PCI-DS
interface” interfaces with a PCI bus and receives a data stream of PCI bus
transactions. For example, Requester points out that a PCI bus transaction
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includes “[an] address phase” and “a physical address (32 bits)” (3PR
Comments at 11), which Patent Owner does not refute. Patent Owner does
not persuasively demonstrate a difference between the “address phase” or
“physical address (32 bits)” of the PCI bus transaction as received at and
communicated by the “PCI-DS interface” of Haas and the claimed limitation
of a data stream including “address bits.”
Claim 8, for example, recites that “the encoded serial bit stream
comprises 10 bit packets.” Patent Owner argues that Haas fails to disclose
or suggest “that the ‘encoded serial bit stream comprises 10 bit packets” (PO
App. Br. 18). We disagree with Patent Owner for at least the reasons set
forth by the Requester (Comments 11-12). Requester explains, and Patent
Owner does not refute, that Haas discloses data packets of a size other than
10 bit packets (id.). Claim 8 recites “10 bit packets.” To rebut a case of
obviousness, “the applicant must show that the particular range is critical,
generally by showing that the claimed range achieves unexpected
results . . .” In re Woodruff, 919 F.2d 1575 (Fed. Cir. 1990). As the
Examiner explains, however, Patent Owner has not persuasively
demonstrated an unexpected or unpredicted benefit of using 10 bit packets
(ACP 18) over data packets of other sizes.
Patent Owner argues that the use of 10 bit packets, as opposed to
using bit packets of other sizes, enables “transmission rates to keep pace
with processor and I/O advances for the next 10 years or more” and
“improves the physical signal so that bit synchronization is easier, design of
receivers and transmitters is simplified, error detection is improved, and
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control characters can be distinguished from data characters” (PO App. Br.,
19, citing PCI Express White Paper, pp. 1 and 5).
PCI Express White Paper states that “PCI Express uses an “encoded”
bandwidth (i.e., “8b/10b encoding”) and that such an approach “improves
the physical signal.” (p. 5). Hence, PCI Express White Paper discloses that
using an encoded bandwidth as opposed to using 10 bit packets improves a
signal. Also, PCI Express White Paper does not disclose that such a benefit
is unexpected or unpredicted or that such a benefit even applies when
compared to utilizing any other size data packets. Nor does PCI Express
White Paper provide specific technical facts that would lead one of ordinary
skill in the art to understand the specific benefits, if any, of utilizing 10 bit
packets instead of packets of a different size. Rather, PCI Express White
Paper merely states general “benefits” of utilizing an “encoded” bandwidth
without providing specific details.
PCI Express White Paper also states that the “new bus technology is
expected to allow . . . transmission rates to keep pace with processor and I/O
advances for the next 10 years or more” (p. 1) but does not indicate that
utilizing 10 bit packets instead of other specific sizes would result in such
“advances for the next 10 years or more.” Also, as stated above, PCI
Express White Paper merely provides general statements of hypothesized
improvements by using a “new bus technology” rather than specific facts
that one of ordinary skill in the art would have understood as specific
unexpected or unpredictable benefits of using 10 bit packets instead of any
other particular size packets.
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Patent Owner does not provide additional arguments in support of
claims 7-94 or arguments with respect to OMI, Sheets, Bourgeois, USB,
Ahern, Cohen, or Pan.
Patent Owner argues that it would not have been obvious to one of
ordinary skill in the art to have combined Gallagher with another reference,
such as Haas, because “[t]he claimed invention solves a long-felt need” (PO
App. Br. 28). In particular, Patent Owner argues that the claimed features of
1) an “encoded serial data stream of . . . (PCI) bus transaction,” 2) “encoded
serial bit stream comprises 10 bit packets,” 3) “differential signal,” 4) “serial
channels,” and 5) “transmit[ting] data in opposite directions” (PO App. Br.
27) are characteristics of “PCI Express” and that PCI Express “solves a
long-felt need” by satisfying “the need to unburden and replace the outdated,
parallel PCI bus in modern computer systems” (PO. App. Br. 28). We
disagree with Patent Owner for at least the reasons set forth by Requester
(see e.g., 3PR Comments 5-6).
Patent Owner also asserts various alleged features of a PCI bus (e.g., a
parallel bus that is reaching its performance limits) and various alleged
features of PCI Express (e.g., a high-speed bus that maintains backward
compatibility) (PO App. Br. 28) but does not persuasively show how any of
the cited claim features3 solve a “long-felt need,” what any alleged “long-
felt need(s)” is/are, or that “others tried and failed” to provide solutions to
any alleged “long-felt need.” Norgren Inc. v. Int’l Trade Commission, 699
F.3d 1317, 1327 (Fed. Cir. 2012) (insufficient to show long-felt need when

3 i.e., providing for an encoded serial data stream of PCI bus transaction,
encoded serial bit stream, differential signal, serial channels, or transmit data
in opposite directions (PO App. Br. 27).
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evidence fails to show that “others tried and failed”). Rather, Patent Owner
merely indicates various features of a PCI bus and PCI Express as disclosed
by a reference that describes general aspects of the PCI Express system.
Patent Owner argues that it would not have been obvious to one of
ordinary skill in the art to have combined Gallagher with another reference,
such as Haas, because of alleged “[c]ommercial success of the claimed
invention” (PO App. Br. 29). We disagree with Patent Owner for at least the
reasons set forth by Requester (see e.g., 3PR Comments 6-7). As the
Federal Circuit ruled in Ormco Corp. v. Align Tech., Inc., 463 F.3d 1299,
1311-12 (Fed. Cir. 2006), “[e]vidence of commercial success, or other
secondary considerations, is only significant if there is a nexus between the
claimed invention and the commercial success.” Id. (evidence did not show
that the commercial success was the result of claimed and novel features).
In order to establish a proper nexus, the patentee must offer “proof that the
sales were a direct result of the unique characteristics of the claimed
invention-as opposed to other economic and commercial factors unrelated to
the quality of the patented subject matter.” In re Huang, 100 F.3d 135, 140
(Fed. Cir. 1996).
In the present case, Patent Owner contends that there was “wide
adoption” of PCI Express but does not provide any specifics regarding the
breadth or nature of the alleged “wide adoption,” proof of sales, statements
of overall relevant market conditions, or an indication of any specific
commercial activity. (PO App. Br. 30). Therefore, Patent Owner does not
sufficiently demonstrate that the claimed invention was, in fact, “wide[ly]
adopted.” Even assuming that PCI Express was, in fact, “wide[ly] adopted,”
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as Patent Owner contends, Patent Owner does not persuasively demonstrate
that any alleged “wide adoption” was due to any specific claim feature.
Patent Owner argues that it would not have been obvious to one of
ordinary skill in the art to have combined Gallagher with another reference,
such as Haas, because of “[l]icenses taken by major players in the computer
industry” (PO App. Br. 30). We disagree with Patent Owner for at least the
reasons set forth by Requester (see e.g., 3PR Comments 6-7). For example,
the Federal Circuit has held that the mere fact that a patent has been licensed
is insufficient for purposes of demonstrating commercial success. See
Stratoflex, Inc. v. Aeroquip Corp., 713 F.2d at 1539. When a license of a
patent is presented as evidence of the success of a patent, the patentee must
provide additional evidence of the importance of the claimed invention
within the license. Id. Without a showing of nexus, “the mere existence of
... licenses is insufficient to overcome the conclusion of obviousness” when
there is a strong prima facie case. SIBIA Neurosciences, Inc. v. Cadus
Pharm. Corp., 225 F.3d 1349, 1358 (Fed.Cir. 2000).
In the present case, Patent Owner merely asserts that “[l]icenses
[were] taken by major players” (PO App. Br. 30). Even assuming Patent
Owner’s contention to be true that licenses were, in fact, “taken by major
players,” Patent Owner, at best, would show “the mere existence of . . .
licenses.” As above, a showing of “the mere existence of . . . licenses” is
insufficient to overcome the conclusion of obviousness. In the absence of a
showing of a nexus between any specific claim feature to the alleged
licensing “by [unnamed] major players,” we cannot agree with Patent Owner
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that the mere alleged licensing activity rebuts the strong prima facie case of
obviousness.
Patent Owner argues that it would not have been obvious to one of
ordinary skill in the art to have combined Gallagher with another reference
because “[t]he invention has been copied” (PO App. Br. 29-30). We
disagree with Patent Owner for at least the reasons set forth by Requester
(see e.g., 3PR Comments 7-8) and the Examiner (RAN 443-444).
For at least the above reasons, we affirm the Examiner’s rejection of
claims 6-15, 21-25, 31-50, and 61-94 as unpatentable over Gallagher, OMI,
and Haas; claims 16-20, 26-30, and 51-60 as unpatentable over Gallagher,
OMI, Haas, and Sheets; and claims 36-40, 71-85, and 92-24 as unpatentable
over Gallagher, OMI, Haas, and one of Bourgeois, USB, or Pan.
Affirmance of the rejection for the above-referenced claims based on
Gallagher and Haas renders it unnecessary to reach the propriety of the
Examiner’s decision to reject those claims on a different basis. Cf. In re
Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009). As such, we need not reach
the propriety of the rejection of those claims over QuantumNet or Chatcom,
alone or in combination with OMI, Haas, Pan, Hong, Sheets, Cohen,
Bourgeois, USB, and/or Coulson. We also need not reach the propriety of
the rejection of those claims over Gallagher and Hong.

CONCLUSION
The Examiner did not err in rejecting claims 6-94.
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DECISION
We affirm the Examiner’s decision to reject claims 6-15, 21-25, 31-
50, and 61-94 under 35 U.S.C. § 103(a) as unpatentable over Gallagher,
OMI, and Haas; claims 16-20, 26-30, and 51-60 under 35 U.S.C. § 103(a) as
unpatentable over Gallagher, OMI, Haas, and Sheets; claims 36-40 under 35
U.S.C. § 103(a) as unpatentable over Gallagher, OMI, Haas, and Bourgeois;
claims 71-80 under 35 U.S.C. § 103(a) as unpatentable over Gallagher,
OMI, Haas, and USB; and claims 81-85 and 92-94 under 35 U.S.C. § 103(a)
as unpatentable over Gallagher, OMI, Haas, and Pan.
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.

AFFIRMED

alw
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PATENT OWNER:

COOLEY LLP
ATTN: PATENT GROUP
1299 PENNSYLVANIA AVENUE, NW
SUITE 700
WASHINGTON, DC 20004

THIRD PARTY REQUESTER:

DAVID L. McCOMBS
HAYNES AND BOONE, LLP IP SECTION
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219