Ex Parte 7376779 et al

Patent Trial and Appeal Board

May 21, 2015

95001475 (P.T.A.B. May. 21, 2015)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,475 10/27/2010 7376779 ACQI-010/17US
310578-2064
3879
58249 7590 08/07/2017
COOLEY LLP
ATTN: Patent Group
1299 Pennsylvania Avenue, NW
Suite 700
Washington, DC 20004
EXAMINER
BANANKHAH, MAJID A
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
08/07/2017 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

HEWLETT-PACKARD COMPANY and INTERNATIONAL BUSINESS
MACHINES CORPORATION,
Requester,

v.

ACQIS LLC,
Patent Owner.
____________

Appeal 2013-007833
Reexamination Control 95/001,475
Patent 7,376,779 B2
Technology Center 3900
____________

Before STEPHEN C. SIU, DENISE M. POTHIER, and BRUCE R.
WINSOR, Administrative Patent Judges.

SIU, Administrative Patent Judge

DECISION ON REMAND

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Patent 7,376,779 B2

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This matter returns to us from the Federal Circuit, granting a joint
motion to remand the appeal to the Patent Trial and Appeal Board for further
proceedings (“Order”) on June 13, 2017. Order 2.
In an earlier Decision, mailed October 28, 2013 (“Decision”) and an
earlier Decision on Request for Rehearing, mailed May 21, 2015 (“Dec. on
Reh’g” or “Decision on Rehearing”), another Board panel1 affirmed the
Examiner’s decision to reject claims 6–94 of US Patent 7,376,779 B2 (“the
’779 patent”) under 35 U.S.C. 103(a) over various combinations of
references. See, e.g., Decision 17.
Subsequently, petitions for Inter Partes Review for US Patent
8,041,873 B2 (“the ’873 patent) and US Patent RE42,814 (“the ’814 patent)
were filed on September 10, 2014 (IPR2014-01462, IPR2014-01469
respectively). A different panel at the Board determined in those
proceedings that claims 54, 57, 60, and 61 of the ’873 patent (IPR2014-
01462) were not shown by a preponderance of the evidence to be
unpatentable over the combination of Horst2 and LVDS Owner’s Manual,3
that claims 56 and 59 were not shown by a preponderance of the evidence to
be unpatentable over the combination of Horst and Pocrass,4 and claim 58
was not shown by a preponderance of the evidence to be unpatentable over

1 Administrative Patent Judge Weinberg participated in the previous
decisions in Appeal 2013-007833.
2 Robert W. Horst, TNet: A Reliable System Area Network (Feb. 1995)
(“Horst”).
3 National Semiconductor, LVDS Owner’s Manual: Design Guide (Spring
1997) (“LVDS Owner’s Manual”).
4 U.S. Patent No. 5,428,806 (issued June 27, 1995) (“Pocrass”).
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the combination of Horst and Deters.5 IPR2014-01462, Paper 61 2, 18.
That same panel at the Board determined that claims 24 and 31–33 of the
’814 patent (IPR2014-01469) were not shown by a preponderance of the
evidence to be unpatentable over the combination of Horst, Mathers,6 and
LVDS Owner’s Manual and that claims 31–33 were not shown by a
preponderance of the evidence to be unpatentable over the combination of
Bogaerts,7 Gulick,8 Mathers, and James9. IPR2014-01469, Paper 56, 2, 23.
Both the ’873 patent and the ’814 patent are alleged by Patent Owner to be
related to the ’779 patent.
Claim 54 of the ’873 patent is as follows:
54. A computer module insertable into a coupling site
of a console for data communication, comprising:
a main circuit board;
a processing unit coupled to the main circuit board;
a main memory coupled to the processing unit;
a low voltage differential signal (LVDS) channel
comprising two sets of unidirectional, multiple serial bit
channels to transmit data in opposite directions for
communicating an encoded serial bit stream of Peripheral
Component Interconnect (PCI) bus transaction; and
a peripheral bridge directly coupled to the processing
unit, the peripheral bridge comprising an interface controller
directly coupled to the LVDS channel.

Claim 24 of the ’814 patent is as follows:

5 U.S. Patent No. 5,227,957 (issued July 13, 1993) (“Deters”).
6 U.S. Patent No. 6,012,145 (issued Jan. 4, 2000) (“Mathers”).
7 A. Bogaerts et al., RD24 Status Report: Application of the Scalable
Coherent Interface to Data Acquisition at LHC (Oct. 1996) (“Bogaerts”).
8 U.S. Patent No. 6,148,357 (issued November 14, 2000) (“Gulick”).
9 U.S. Patent No. 5,961,623 (issued October 5, 1999) (“James”).
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24. A method for operating a computer system, said
method comprising:
inserting an attached computer module ("ACM") into a
bay of a console in a modular computer system, the console
comprising a first low voltage differential signal (LVDS)
channel comprising two unidirectional serial channels that
transmit encoded data of Peripheral Component Interconnect
(PCI) bus transaction in opposite directions; said ACM
comprising
a microprocessor unit coupled to a mass memory storage
device;
a north bridge to communicate address and data bits of
PCI bus transaction in serial form, said north bridge directly
coupled to said microprocessor unit;
a main memory coupled to said microprocessor unit
through said north bridge; and
a second LVDS channel comprising two unidirectional
serial channels that transmit data in opposite directions, said
second LVDS channel extending/ram said north bridge to
convey said address and data bits of PCI bus transaction in
serial form;
applying power to said computer system and said ACM
to execute a security program, said security program being
stored in said mass memory storage device; and
prompting for a user password from a user on a LCD
display coupled to the console.

Claim 54 of the ’873 patent recites a “Peripheral Component
Interconnect (PCI) bus transaction.” During proceedings of IPR2014-01462,
Patent Owner argued that the broadest reasonable construction of the claim
term “Peripheral Component Interconnect (PCI) bus transaction,” as recited
in claim 54 of the ’873 patent, is “command, address, and data information,
in accordance with the PCI standard, for communication with an
interconnected peripheral component” and that the term “PCI bus
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transaction” “should [be] limit[ed] . . . to a bus transaction . . . in accordance
with the Peripheral Component Interconnect protocol.” IPR2014-01462,
Prelim. Resp. 4, 6. Hence, Patent Owner proposed that one of skill in the art
would have broadly but reasonably construed the claim term “Peripheral
Component Interconnect (PCI) bus transaction” to have included a
transaction that is in accordance with the PCI protocol but would have
construed the term to exclude any transaction that is not in accordance with
the PCI protocol. The Board adopted Patent Owner’s proposed construction
of this claim term and determined that Petitioner failed to demonstrate by a
preponderance of the evidence that (1) claims 54, 57, 60, and 61 are
unpatentable over the combination of Horst and LVDS Owner’s Manual, (2)
claims 56 and 59 are unpatentable over the combination of Horst and
Pocrass, or (3) claim 58 is unpatentable over the combination of Horst and
Deters. IPR2014-01462, Paper 14 at 7; Paper 61 at 2, 18.
During Inter Partes review of IPR2014-01469, Patent Owner argued
that, under a broadest reasonable construction standard, the claim term “PCI
bus transaction” “cannot reasonably be broader than a bus transaction of the
Peripheral Component Interconnect protocol standard” and that “[t]he Board
. . . should limit ‘PCI’ to the ‘Peripheral Component Interconnect’ protocol
standard and ‘PCI bus transaction’ to a bus transaction according to that
protocol standard.” IPR2014-01469, Prelim. Resp. 6–7. In other words,
Patent Owner reiterated the same proposed broadest reasonable construction
of the term “PCI bus transaction” as proposed in IPR2014-01462; namely,
Patent Owner contends that one of skill in the art would have broadly but
reasonably construed the term “Peripheral Component Interconnect (PCI)
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bus transaction” to have included a transaction that is in accordance with the
PCI protocol but would have construed the term to exclude any transaction
that is not in accordance with the PCI protocol. In IPR2014-01469, as in
IPR2014-01462, the Board adopted Patent Owner’s proposed construction of
the term “PCI bus transaction,” which, as described above, was the same
proposed construction of that term as proposed by Patent Owner (and
adopted by the Board) in IPR2014-01462, and determined that Petitioner
failed to show by a preponderance of the evidence that claims 24 and 31–33
of the ’814 patent are unpatentable over the combination of Horst, Mathers,
and LVDS Owner’s Manual or that claims 31–33 of the ’814 patent are
unpatentable over the combination of Bogaerts, Gulick, Mathers, and James.
IPR2014-01469, Paper 11, 7; Paper 56 2, 23.
No other relevant proposed construction of any other claim term in
either of these matters was proposed, disputed, or otherwise discussed in
either IPR2014-01462 or IPR2014-01469.
As stated above, the ’779 patent is the subject of the instant
proceeding, Reexamination Control 95/001,475, and is alleged by Patent
Owner to be related to both the ’873 patent and the ’814 patent. Claim 6 of
the ’779 patent is as follows:

6. A computer system comprising:
a peripheral console comprising a power supply, a first
coupling site and a second coupling site, each coupling site
comprising a connector and a slot, the console being an
enclosure housing
the coupling sites,
an Ethernet hub controller powered by the power supply,
and
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a plurality of computer modules; each computer module
coupled to one of the coupling site through the connector and
the slot, comprising
a CPU,
a graphics controller,
a main memory coupled to the CPU,
an interface controller coupled to a differential signal
channel for communicating an encoded serial data stream of
Peripheral Component Interconnect (PCI) bus transaction,
interconnection circuitry coupled to said CPU, said
interconnection circuitry connectable to the peripheral console;
and
wherein said CPU is uncoupled from any primary output
circuitry when said interconnection circuitry is disconnected
from the peripheral console; and
wherein each of the computer modules is substantially
similar in design to each other.

At appeal to the Patent Trial and Appeal Board, a different panel
affirmed the Examiner’s rejections of claims 6–15, 21–25, 31–50, and 61–94
of the ’779 patent over the combination of Haas,10 Gallagher,11 and OMI;12
claims 16–20, 26–30, and 51–60 over the combination of Gallagher, OMI,
Haas, and Sheets;13 claims 36–40 over the combination of Gallagher, OMI,
Haas, and Bourgeois;14 claims 71–80 over the combination of Gallagher,

10 Stefan Haas, “The IEEE 1355 Standard: Developments, Performance and
Application in High Energy Physics,” thesis for the degree of Doctor of
Philosophy, University of Liverpool, December 1998 (“Haas”).
11 U.S. Patent No. 6,742,068 B2 (issued May 25, 2004) (“Gallagher”).
12 IEEE Standard 1355-1995 – Standard for Heterogeneous InterConnect,
October 30, 1998 (“OMI”).
13 U.S. Patent No. 4,670,837 (issued June 2, 1987) (“Sheets”).
14 U.S. Patent No. 5,965,957 (issued October 12, 1999) (“Bourgeois”).
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OMI, Haas, and USB;15 and claims 81–85 and 92–94 over the combination
of Gallagher, OMI, Haas, and Pan.16 Notably, none of the cited references in
the reexamination of the ’779 patent were relied on in either of IPR2014-
01462 or IPR2014-01469. Additionally, none of the cited references in
either IPR2014-01462 or IPR2014-01469 were relied on or cited to in the
’779 patent reexamination proceeding.
During this ’779 reexamination proceeding, Patent Owner argued that
Haas fails to disclose or suggest “‘encoding . . . [of] a PCI bus transaction.’”
Decision 7 (citing PO App. Br. 15). In the Decision, we stated that “[w]e
disagree with Patent Owner” (Decision 7) and provided a detailed
explanation as to the reasons for our conclusion (id. at 7–10). For example,
in view of Patent Owner’s argument that Haas supposedly fails to disclose or
suggest “encoding” of data, we indicated a broadest, reasonable construction
of the term “encoding” as would have been understood by one of skill in the
art in light of the Specification and also explained how Haas discloses such
“encoding.” Id.
At rehearing, Patent Owner presented a new argument, namely, that
Haas “merely shows a PCI bus controller connected to a parallel PCI Bus”
but fails to disclose “an encoded serial data stream of a PCI bus transaction.”
Req. Reh’g. 6. In the Decision on Rehearing, we explained that (1) new
arguments are not permitted at rehearing and that (2) in any event, each of

15 Universal Serial Bus Specification, http://poweredusb.org/pdf/usb11.pdf,
1998 (“USB”).
16 U.S. Patent No. 5,588,850 (issued December 31, 1996) (“Pan”).
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Gallagher, Haas, and OMI discloses “serial” transmission of data. See, e.g.,
Decision on Rehearing 3–5.
In summary, during the reexamination proceeding of the ’779 patent,
Patent Owner argued that Haas fails to disclose or suggest both “encoding”
data and “serial” transmission of data. Both of these issues were addressed
in detail in the Decision and/or Decision on Rehearing, including the
broadest, reasonable construction of these terms as adopted by the Board, as
the record reflects. During Inter Partes review proceedings of the ’873
patent and ’814 patent, Patent Owner argued that a broadest reasonable
construction of the term “PCI bus transaction” includes transactions in
accordance with the PCI protocol but excludes transactions not in
accordance with the PCI protocol. This proposed construction was adopted
by the Board in both corresponding Inter Partes review matters. Patent
Owner does not indicate that a broadest reasonable construction of the term
“PCI bus transaction,” discussed in the Inter Partes review proceedings, was
argued or otherwise addressed in this reexamination proceeding or that a
broadest reasonable construction of either of the terms “encoding” or “serial
transmission,” discussed in the reexamination proceeding, was argued or
otherwise addressed in the Inter Partes review proceedings of matters
alleged to be related to the ’779 patent.
Pursuant to an Order by the Federal Circuit, mailed June 13, 2017,
and mandate, we issued an order (“Board Order”), mailed June 22, 2017,
authorizing Patent Owner to file a brief by July 7, 2017. Patent Owner did
not file such a brief by the originally stated deadline but was granted an
extension until July 21, 2017. As explained in the Board Order, the Federal
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Circuit stated that Patent Owner’s brief may address specific points
regarding Patent Owner’s alleged inconsistencies between claim
construction in the ’779 patent reexamination proceeding and the Inter
Partes Reviews of the ’873 patent (IPR2014-01462) and the ’814 patent
(IPR2014-01469). Board Order 2.
In Patent Owner’s Brief on Claim Construction, filed July 21, 2017
(“PO Remand Brief”), Patent Owner states that “[t]he Board’s construction
of the claim term ‘encoded serial data stream of PCI bus transaction,’ in this
inter partes reexamination [of the ’779 patent] conflicts with the Board’s
construction of nearly identical limitations in two inter partes reviews
(IPR2014-01462 and -01469, the ‘IPRs’) of related patents.” PO Remand
Brief 1. As described above, in this reexamination proceeding, claim terms
that were at issue and ultimately construed were “serial” transmission of data
and “encoded” data while the claim term discussed in both IPR2014-01462
and IPR2014-01469 was “PCI bus transaction.” Contrary to Patent Owner’s
implied assertions, the arguments presented in the reexamination proceeding
were not focused on the “PCI bus transaction” limitation. Id. at 9 (citing PO
App. Br. 16). On the other hand, the claim term that was at issue and
ultimately construed in the inter partes review of IPR2014-01462 and
IPR2014-01469 was “PCI bus transaction.” Patent Owner appears to assert
that a “conflict” exists between claim construction of “serial” or “encoded”
and claim construction of “PCI bus transaction” but does not explain
persuasively the precise nature of this alleged “conflict” between claim
construction of different claim terms.
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Patent Owner states that (1) “the Board . . . erroneously [found] that
the claim . . . was met by encoded data present on the parallel PCI bus in
Haas [in this reexamination proceeding of the ’779 patent],” (2) “[t]he
Board’s construction of the ‘encoded serial data stream of [PCI] bus
transaction’ in the ’779 patent conflicts with the Board’s IPR constructions
because the Board’s ’779 construction points only to parallel data on a
parallel PCI bus as meeting the encoded serial data stream of PCI bus
transaction” (but that “the Board’s IPR construction requires encoded data
be in serial form”), (3) “the Board acknowledged . . . that the . . . busses in
Gallagher and Haas . . . are parallel busses . . . not . . . serial channels” and
“the ’779 patent’s . . . serial . . . limitations was met by ‘data received from a
[parallel] PCI bus,” (4) “the Board’s IPR construction requires that the PCI
bus transaction actually be communicated as the encoded serial data stream
over the differential signal channel, not just as any data,” and, in this
reexamination proceeding, “[t]he Board never addressed . . . that a PCI bus
transaction was actually communicated as an encoded serial data stream.”
PO Remand Brief 2, 5–7 (citing Decision 9–10).
In other words, Patent Owner argues that, in this reexamination
proceeding, we allegedly previously construed the claim term “serial data
stream” (e.g., transmission of data) to include a “parallel” data stream (e.g.,
transmission of data) and subsequently, determined that a disclosure of a
“parallel” data stream (e.g., transmission of data) by at least one cited prior
art reference (i.e., Haas) was sufficient to meet the claim limitation of “serial
data stream” (e.g., transmission of data). Patent Owner’s characterization of
this reexamination proceeding and our determination in this regard is
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incorrect. As the record shows and as discussed above, despite Patent
Owner’s untimely presentation of arguments regarding “serial” transmission
of data in a Request for Rehearing, we nevertheless explained in detail how
each of Gallagher, Haas, and OMI discloses “serial” transmission of data.
See, e.g., Decision on Rehearing 3–5 (citing Gallagher 15:39–42, Haas 43,
and OMI 2).
Patent Owner also argues that “Patent Owner preserved the claim
construction and reasoning applied by the Board in the IPRs in this
reexamination by making the same arguments in Patent Owner’s Appeal
Brief.” PO Remand Brief 2. Patent Owner does not demonstrate
sufficiently, however, that “the same arguments” (pertaining to claim
construction issues), in fact, were presented “in the IPRs” as in “this
reexamination.” As summarized above, we do not independently identify
any common arguments between claim construction arguments in this
reexamination proceeding (pertaining to the terms “serial” and “encoded”)
and claim construction of a different term (i.e., “PCI bus transaction,” not
raised in this reexamination proceeding) in the inter partes reviews alleged
to be related to this reexamination proceeding.
Patent Owner argues that “the Board never found . . . that the
information . . . transmitted . . . in Haas is a PCI bus transaction that has
been encoded.” PO Remand Brief 2. As the record reflects and as
summarized above, this argument (regarding the “encoded” claim limitation)
was previously raised and addressed in this reexamination proceeding. See,
e.g., PO App. Br. 14–15, Decision 7–10. We further note that Patent Owner
does not demonstrate persuasively that any issue was raised regarding the
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“encoded” claim term in any of IPR2014-01462 or IPR2014-01469, nor do
we independently identify this issue in the inter partes reviews.
Patent Owner argues that “the Board should adopt the same
construction for the ’779 patent’s . . . PCI bus transaction limitations [as in
IPR2014-01462 and IPR2014-01469].” PO Remand Brief 8. Patent Owner
does not demonstrate that any arguments were previously raised in this
reexamination proceeding regarding the claim term “PCI bus transaction.”
Nor does Patent Owner allege or argue that any of the cited references in this
reexamination proceeding (none of which were relied upon in either of
IPR2014-01462 or IPR2014-01469) fails to disclose or suggest a “PCI bus
transaction.” In view of these observations, claim construction of the term
“Peripheral Connect Interconnect (PCI) bus transaction” at this point in the
proceeding is untimely and unnecessary.
Also, given that this specific limitation (i.e., “PCI bus transaction”)
was not sufficiently argued in this reexamination proceeding, the Board in
this proceeding has not construed such a recitation in our decision, related to
this phrase or otherwise, in such a way as to conflict with a different panel
authoring the decisions related to allegedly relevant IPRs. As such, Patent
Owner has not adequately preserved as an argument in this proceeding
regarding the limitation ““Peripheral Connect Interconnect (PCI) bus
transaction” over the cited references in this reexamination proceeding.
Patent Owner argues that “Patent Owner preserved the argument that
the ’779 patent’s . . . [claim] limitations require . . . encoded . . . serial data
streams . . .” and that, in any event, according to Patent Owner, “good cause
exists to allow Patent Owner to raise its . . . arguments [regarding “serial,” as
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recited in the disputed claims] because the Board reached its construction of
the encoded [aspect of the claimed data] for the first time in its Decision on
Appeal,” because “it is in the public interest” to do so, because “the IPR
claim constructions arose after the Board issued its Decision on Appeal and .
. . Rehearing and are therefore superseding intervening facts,” and because
“the Supreme court [will] consider the question [of] . . . [w]hether inter
partes review . . . violates the Constitution.” PO Remand Brief 9, 10, 12, 13.
We need not assess the relevance of any of these arguments to
whether or not Patent Owner preserved arguments pertaining to claim
construction of the term “serial” or the term “encoded” because arguments
pertaining to claim construction of the terms “serial” and “encoded” were
previously raised and addressed in this reexamination proceeding. See, e.g.,
PO App. Br. 15, Req. Reh’g. 6, Decision 3–10; see also above discussion.
Patent Owner re-states arguments that each of Gallagher, OMI and
Haas supposedly fails to disclose or suggest “serial” or “encoded” data, as
recited in the disputed claims. PO Remand Brief 14–22. As discussed
above, these issues were previously raised and addressed.
Based on the foregoing and upon careful review of each of the
involved records, we identify no discrepancy or inconsistency between claim
construction of the terms “serial” transmission of data and “encoded” data in
the ’779 patent reexamination proceeding and claim construction of the
different term “PCI bus transaction” in IPR2014-01462 and IPR2014-01469.
Also, we identify no inconsistency between our previous affirmance of the
Examiner’s rejection over various combinations of references including
Gallagher, OMI, and Haas of claims 6–94 (with respect to our claim
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construction of the terms “encoded” or “serial”) and determinations in
IPR2014-01462 and IPR2014-01469 with respect to claim construction of
the different term “PCI bus transaction” based on references other than any
of the references relied upon in this reexamination proceeding (e.g.,
Gallagher, OMI, or Haas).
In view of the above, we maintain our affirmance the Examiner’s
decision to reject claims 6–94 over the previously stated grounds. See
Decision and Decision on Rehearing.

AFFIRMED

PATENT OWNER:

COOLEY LLP
ATTN: Patent Group
1299 Pennsylvania Avenue, NW
Suite 700
Washington, DC 20004

THIRD PARTY REQUESTER:

David L. McCombs
HAYNES AND BOONE LLP, IP Section
2323 Victory Avenue, Suite 700
Dallas, TX 75219

msc