Ex Parte 6816814 et al

Patent Trial and Appeal Board

May 19, 2015

95000667 (P.T.A.B. May. 19, 2015)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/000,667 05/11/2012 6816814 ART-12-5019REX 1428
25226 7590 05/19/2015
MORRISON & FOERSTER LLP
755 PAGE MILL RD
PALO ALTO, CA 94304-1018
EXAMINER
LIE, ANGELA M
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
05/19/2015 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

ARTERIS, INC. and QUALCOMM TECHNOLOGIES INCORPORATED,
Requester,

v.

SONICS, INC.,
Patent Owner.
____________

Appeal 2015-001312
Reexamination Control 95/000,667
Patent 6,816,814 B2
Technology Center 3900
____________

Before STEPHEN C. SIU, BRADLEY W. BAUMEISTER, and
IRVIN E. BRANCH, Administrative Patent Judges.

SIU, Administrative Patent Judge.

DECISION ON APPEAL
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Patent Owner appeals under 35 U.S.C. §§ 134 and 315 the Examiner’s
rejections of claims 1–8, 14–20, 23–30, and 36–39 over various references.1
PO App. Br. 7–8. Requester appeals the Examiner’s decision not to adopt
the rejections of claims 9–13, 14–18, and 31–39 over various references.
3PR App. Br. 5.2 We have jurisdiction under 35 U.S.C. §§ 134 and 315. An
oral hearing was conducted on April 15, 2015.

STATEMENT OF THE CASE
This proceeding arose from a May 31, 2012 request by Arteris, Inc.
(“Requester”) for an inter partes reexamination of claims of U.S. Patent
6,816,814 B2, titled “Method and Apparatus for Decomposing and
Verifying Configurable Hardware” and issued to Jeffrey Allen Ebert, Ravi
Venugopalan, and Scott Carlton Evans, on November 9, 2004 (“the
’814 patent”).
The ’814 patent describes a method and system for hardware
verification. Spec. 1:8. Claim 1 reads as follows:
1. A computer implemented method comprising:
automatically decomposing a configurable hardware system
into a set of one or more units;
creating a test-bench for each of the set of units; and
verifying each of the set of units before verifying the
configurable hardware system, wherein the configurable hardware
system is customized at design creation time by using specified values
for a set of parameters and a first instance of the configurable

1 Patent Owner Appeal Brief, Inter Partes Reexamination, dated
June 23, 2014 (“PO App. Br.”).
2 Brief on Appeal by Appellant Requestor in an Inter Partes Reexamination
Proceeding, dated June 23, 2014 (“3PR App. Br.”).
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hardware system is different in function than a second instance of the
configurable hardware system.

The cited references are as follows:

Nightingale US 6,876,941 B2 Apr. 5, 2005
Devins US 6,427,224 B1 July 30, 2002
Bollano WO 02/08966 A2 Jan. 31, 2002
Kelsey US 5,452,227 Sept. 19, 1995
Nadeau-Dostie US 6,868,532 B2 Mar. 15, 2005

Patent Owner appeals the Examiner’s rejections of claims 1–4, 18–20,
and 23–26 under 35 U.S.C. § 102(e) as anticipated by Nightingale; claims 5–
8 and 27–30 under 35 U.S.C. § 103(a) as unpatentable over Nightingale;
claims 1–4, 14–20, and 23–26 under 35 U.S.C. § 102(b) as anticipated by
Bollano; claims 1–4, 14–20, 23–26, and 36–39 under 35 U.S.C. § 103(a) as
unpatentable over Devins; claims 18 and 19 under 35 U.S.C. § 102(b) as
anticipated by Kelsey; and claims 1, 4, 5, 23, 26, and 27 under 35 U.S.C.
§ 102(e) as anticipated by Nadeau-Dostie.
Requester appeals the Examiner’s non-adoption of the rejections of
claims 9–13 and 31–35 under 35 U.S.C. § 102(e) as anticipated by
Nightingale or under 35 U.S.C. § 103(a) as unpatentable over Devins; claims
14–17 and 36–39 under 35 U.S.C. § 103(a) as unpatentable over Kelsey; and
claims 16 and 38 under 35 U.S.C. § 103(a) as unpatentable over Nadeau-
Dostie.

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ISSUE

Did the Examiner err in rejecting claims 1–8, 14–20, 23–30 and 36–
39 and in not rejecting claims 9–13 and 31–35?

PRINCIPLES OF LAW

In rejecting claims under 35 U.S.C. § 102, “[a] single prior art
reference that discloses, either expressly or inherently, each limitation of a
claim invalidates that claim by anticipation.” Perricone v. Medicis Pharm.
Corp., 432 F.3d 1368, 1375 (Fed. Cir. 2005) (citation omitted).
The question of obviousness is resolved on the basis of underlying
factual determinations including (1) the scope and content of the prior art,
(2) any differences between the claimed subject matter and the prior art, and
(3) the level of skill in the art. Graham v. John Deere Co., 383 U.S. 1, 17–
18 (1966).
“The combination of familiar elements according to known methods
is likely to be obvious when it does no more than yield predictable results.”
KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007).

ANALYSIS

Nightingale – Patent Owner’s Appeal (Claims 1–8, 18–20, and 23–30)

Claim 1, for example, recites that the configurable hardware system is
customized at design creation time by using specified values for a set of
parameters. Claims 5 and 27 recite a similar feature. Patent Owner argues
that Nightingale discloses a “configuration file” but that the configuration
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file is generated “after design creation time.” PO App. Br. 11–12, 14–15.
We are not persuaded by Patent Owner’s argument.
As the Examiner points out, Nightingale discloses a “configuration
file containing predetermined parameters identifying the type of the device”
to be tested. Nightingale 6:47–48. Nightingale also discloses that this
process “allows the developer of each individual component to design and
test that component.” Nightingale 9:35–37; 11:62, 65–67 (emphasis added).
Patent Owner does not indicate an explicit definition of the term “at design
creation time” in the Specification. Patent Owner also does not demonstrate
persuasively a difference between a developer (of Nightingale) “designing”
a component in a system with predetermined parameters from a
configuration file and a system (containing the component) that is
customized “at design creation time,” as recited in claim 1, for example. In
both, a component and a system are configured while being “designed.”
Claim 1 recites automatically decomposing a system into a set of
units. Claims 5 and 27 recite a similar feature. Patent Owner argues that
Nightingale “is silent with respect to . . . any kind of decomposition” and
that one of ordinary skill in the art would have understood the term
“decomposition” to include “either logically or physically
separating/breaking up a system into its constituent components/units.”
PO App. Br. 9, 12, 15.
Nightingale discloses that a “system” includes “a number of
individual components connected together” and the user is enabled “to
design and test the component [within the overall system].” Nightingale
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1:18–24; see also PO App. Br. 12–13 (citing Goossens Aff.3 ¶ 6). Even if
Patent Owner’s proposed construction of the term “decomposition” is
correct, Patent Owner does not demonstrate persuasively a difference
between Patent Owner’s construction of the term “decomposition” as “either
logically or physically separating/breaking up a system into its constituent
components/units” and Nightingale’s disclosure of individually designing
and/or testing a component in a “system” of components. In both cases, one
component of a system of components is designed or tested separately from
other components in the system (i.e., “logically or physically” separating a
system into constituent components).
Patent Owner also argues that “Nightingale is completely silent with
respect to ‘automatically decomposing.’” PO App. Br. 13. Patent Owner
agrees with the Examiner that one of ordinary skill in the art would have
construed the term “automatically decomposing” broadly but reasonably as
“at least part of the decomposition is . . . processed by a computer without
human involvement,” but Patent Owner argues that “automatically
decomposing” further “require[s] at least identification and separating of the
constituent units of a system be done automatically.” RAN 58, PO App. Br.
10 (citing Goossens Aff. ¶¶ 10–12, Goossens Supp. Aff.4 ¶ 9). Hence Patent
Owner argues that “decomposing” must include “identification and
separating of the constituent units of a system” and that “automatically”

3 Affidavit Pursuant to 37 C.F.R. § 1.132 and MPEP 2616, Kees Goossens,
dated August 29, 2012 (“Goosens Aff.”).
4 Supplemental Affidavit Pursuant to 37 C.F.R. § 1.132 and MPEP 2616,
Kees Goossens, dated February 17, 2013 (“Goosens Supp. Aff.”).
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decomposing must include performing this process “by a computer without
human involvement.”
Dr. Goossens testifies that “manual selection” of a core is not “an
automated process” and that, in the opinion of Dr. Goossens, “it was not
obvious to one skilled in the art . . . how to automate a decomposition of a
[system-on-chip] SoC” or “a configurable hardware system.” Goosens Aff.
¶¶ 10–12. Dr. Goossens also testifies that “decomposition . . . inherently
involve[s] the step of deciding how to divide up the system.” Goosens Supp.
Aff. ¶ 9. However, Dr. Goossens does not assert, provide evidence in
support of, or demonstrate persuasively how one of ordinary skill in the art
would have broadly but reasonably understood “automatically
decomposing” to require also “at least identification and separating of the
constituent units of a system be done automatically.”
During examination, claims are to be given their broadest reasonable
interpretation consistent with the specification, and the language should be
read in light of the specification as it would be interpreted by one of ordinary
skill in the art. In re Amer. Acad. of Sci. Tech Ctr., 367 F.3d 1359, 1369
(Fed. Cir. 2004) (citations omitted). The Office must apply the broadest
reasonable meaning to the claim language, taking into account any
definitions presented in the specification. Id. (citing In re Bass, 314 F.3d
575, 577 (Fed. Cir. 2002)). Hence, we turn to the Specification to ascertain
how one of ordinary skill in the art would have construed the term
“automatic decomposition” in light of the Specification.
The Specification discloses a “decomposition module 109 [that] maps
the configuration data . . . onto the parameters of a unit of system 400 (e.g.,
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unit 1)” and “determine[s] how unit 1’s parameters should be configured to
meet the requirements of the system 400.” Spec. 5:54–60. Hence, based on
the disclosure of the Specification, one of ordinary skill in the art would
have understood that “automatically decomposing” a system includes using
a “module” of a system to configure a selected unit or component in a
system based on the use of parameters (or configuration data) corresponding
to the selected unit or component.
Nightingale discloses a “configuration file containing predetermined
parameters identifying the type of the device” and a “processing unit” that
“dynamically generat[es] a test environment for the device,” the device
being a component within a system. Nightingale 1:18–20; 6:47–51. In other
words, Nightingale, like the Specification, discloses a system component
(the “processing unit” or “module”) that is used to configure a selected unit
or component (i.e., the “device”) in a system (that “consist[s] of a number of
individual components connected together” – Nightingale 1:19–20) and
configuring the selected unit or component in the system based on the use of
parameters (i.e., predetermined parameters from a configuration file)
corresponding to the selected unit or component (i.e., the “device”). We are
not persuaded by Patent Owner’s argument that Nightingale fails to disclose
“automatically decomposing,” as would have been understood by one of
ordinary skill in the art in light of the Specification.
Claim 5 recites a “hardware system design hierarchy.” Patent Owner
argues that Nightingale “is silent with respect to hierarchy of the [device
under test] DUT.” PO App. Br. 16–17. Claim 5 recites a hardware system
design hierarchy of one or more hierarchy levels, decomposing a unit at a
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first level of hierarchy into a lowest level of hierarchy, and verifying units of
a hierarchy level.
Regarding a hardware system design hierarchy of one or more
hierarchy levels, Nightingale discloses a system having “a number of
individual components connected together” and enabling a user “to design
and test the component [within the system].” Nightingale 1:18–23. Hence,
Nightingale discloses a system (i.e., at one level of “hierarchy”) and a
component within the system at another (lower) level of “hierarchy.” In
other words, Nightingale discloses a system of “one or more hierarchy
levels.”
Regarding decomposing a unit at a first level of hierarchy into a
lowest level of hierarchy, Nightingale also discloses identifying a type of a
device within a system (i.e., a device in a bus protocol system) via
“predetermined parameters” read from a “configuration file” and
“dynamically generat[ing] a test environment for the device.” Nightingale
3:11–16. Hence, Nightingale discloses, at least, logically or physically
separating/breaking up a system into components (i.e., identifying and
configuring a device within a system – see e.g., Nightingale 1:23–24), as
Patent Owner argues one of ordinary skill in the art would have construed
the term “decomposing.” In other words, Nightingale discloses
decomposing a unit at a first level of hierarchy (i.e., system level hierarchy)
into a lowest level of hierarchy (i.e., level of the device being tested, the
device being a component within the system and, hence, at a lowest level
within the system).
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Regarding verifying units of a hierarchy level, as previously
discussed, Nightingale discloses testing components (or units) in a system
and “generat[ing] result data indicating compliance with the bus protocol.”
3:24–25. Patent Owner does not demonstrate persuasively a difference
between verifying compliance of a device at a particular hierarchy level
within a system (of Nightingale) and verifying units of a hierarchy level, as
recited in claim 5.
Patent Owner argues that “in order to debug or verify a system,” it
would not have been obvious to one of ordinary skill in the art to have tested
a system in parts (rather than as a whole) based on “basic knowledge” or
“common sense” of the skilled artisan. PO App. Br. 17. As previously
discussed, Patent Owner does not explain sufficiently a difference between
the disclosure of Nightingale of testing and verifying a component or unit of
a system and verifying a unit, as recited in claim 1, for example.
Patent Owner does not provide additional arguments in support of
claims 1–8, 18–20, and 23–30. The Examiner did not err in rejecting claims
1–8, 18–20, and 23–30. Affirmance of the rejections for claims 1–8, 18–20,
and 23–30 based on Nightingale renders it unnecessary to reach the
propriety of the Examiner’s decision to reject those claims or not to reject
those claims on a different basis. Cf. In re Gleave, 560 F.3d 1331, 1338
(Fed. Cir. 2009). As such, we need not reach the propriety of the rejection
of those claims over Devins, Bollano, Kelsey, or Nadeau-Dostie.

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Nightingale – Requester’s Appeal (Claims 9–13 and 31–35)

With respect to claims 9 and 31, the Examiner finds that Nightingale
discloses “specifying configuration data in order to automatically generate
suitable testing environment for a tested device,” but fails to disclose
“generating a configurable hardware unit based on the configuration
parameters.” ACP 88 (citing Nightingale 3:65 – 4:16; 14:34–40).
Nightingale discloses “developing components for integration into a
system [that includes “a number of individual components connected
together”]” by using “predetermined parameters” that “identify[] the type of
device and capabilities of the device” and generating “an RTL representation
of the hardware component.” Nightingale 1:15–16, 18–20, 40–41; 3:12–14.
Hence, Nightingale discloses generating a representation of a “hardware
unit” that is based on configuration parameters (i.e., “predetermined
parameters”), as recited in claim 9, for example. The Examiner does not
point out sufficient differences between generating a unit (of a system), as
recited in claim 9, for example, and generating “an RTL representation” of a
hardware component “used to produce the actual hardware component,” as
disclosed by Nightingale. Nightingale 1:15–16, 18–20, 23–24, 40–41, 43–
45. In both instances, a unit or component of a system is generated based on
parameters.
Patent Owner argues that Nightingale discloses “generating test
environments, not configurable hardware units.” PO Resp. Br. 5. However,
Patent Owner does not explain sufficiently a difference between using
“predetermined parameters” from a configuration file to “generate” an RTL
representation of a “hardware component” and “the actual hardware
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component,” as disclosed by Nightingale (see e.g., Nightingale 1:40–44;
3:12–14, 27–28, 39–41) and generating a configurable hardware unit based
on configuration data, as recited in claim 9, for example.
Patent Owner does not provide additional arguments in support of
claims 9–13 and 31–35. The Examiner erred in refusing to adopt the
rejection of claims 9–13 and 31–35 as anticipated by Nightingale. Reversal
of the Examiner’s decision not to adopt the rejection of claims 9–13 and 31–
35 based on Nightingale renders it unnecessary to reach the propriety of the
Examiner’s decision to reject those claims or not to reject those claims on a
different basis. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009). As
such, we need not reach the propriety of the Examiner’s refusal to reject
those claims over Devins.

Devins – Patent Owner’s Appeal (Claims 14–17 and 36–39)

Claim 14 recites “individual units decomposed from a configurable
hardware system.” Claim 36 recites a similar feature. Patent Owner argues
that one of ordinary skill in the art would have construed the term
“decomposition” broadly but reasonably to include “either logically or
physically separating/breaking up a system into its constituent
components/units” and that Devins fails to disclose “decomposition” of
units, as recited in claim 14. PO App. Br. 9, 21.
Devins discloses “‘cores’ which together constitute an entire ‘system-
on-a-chip’, or SOC” and that “the functioning of both the individual cores as
they are developed, and of the cores interconnected as a system must be
verified.” Devins 1:36–37, 65–67. To this end, Devins discloses “low-level
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code [that] interfaces with a core being simulated” “for a ‘split-domain’
mode . . . in which only the low-level code is executed.” Devins 2:45–46,
49–51. In other words, even if Patent Owner’s construction of the term
“decomposition” is correct, Devins discloses an “individual unit” (i.e., a
“core” within a system) that is “decomposed” (i.e., the “core” being verified
separately from the system and, hence, either logically or physically
separating/breaking up a system into its constituent components or “cores”)
from a configurable hardware system (i.e., a system-on-a-chip or “SOC” of
Devins).
Patent Owner argues that “Devins fails to disclose any decomposition
of a configurable hardware system” because Devins “fails to describe
expressly how the individual cores are obtained.” PO App. Br. 18. We are
not persuaded by Patent Owner’s arguments. As previously discussed,
Devins discloses, for example, testing and verifying an individual “core”
(i.e., a component that is “interconnected as a system”) within a system,
which Patent Owner does not distinguish persuasively from a “unit” (or
core) “decomposed” (i.e., logically or physically separating/breaking up a
system into its constituent components/units, according to Patent Owner)
from a system. In both cases, a component (e.g., a “core”) of a system is
configured and verified separately from the system as a whole (i.e.,
“logically or physically separated” from the system as a whole).
Patent Owner also argues that Devins fails to disclose “units being
verified prior to hardware system” and that providing “units being verified
prior to hardware system” would not have been “basic knowledge or
common sense” to one of ordinary skill in the art. PO App. Br. 21–22.
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Claim 14 recites “verifying the configurable hardware system after verifying
the individual units.” As previously discussed, Devins discloses “the
functioning of both the individual cores as they are developed, and of the
cores interconnected as a system must be verified.” Devins 1:28, 65–67.
Patent Owner does not explain a meaningful difference between verifying a
core (i.e., one component within a system) then verifying the cores
interconnected as a system (i.e., verifying the system itself) and verifying a
system after verifying the individual units (of the system), as recited in claim
14. In both cases, individual components of a system are verified and then
the system (containing the interconnected components) is verified.
Patent Owner does not provide additional arguments in support of
claims 14–17 and 36–39. The Examiner did not err in rejecting claims 14–
17 and 36–39 as unpatentable over Devins. Affirmance of the Examiner’s
rejection of claims 14–17 and 36–39 based on Devins renders it unnecessary
to reach the propriety of the Examiner’s decision to reject those claims or
not to reject those claims on a different basis. Cf. In re Gleave, 560 F.3d
1331, 1338 (Fed. Cir. 2009). As such, we need not reach the propriety of the
Examiner’s rejection or non-adoption of the rejection of those claims over
Bollano, Kelsey, or Nadeau-Dostie.

CONCLUSION
The Examiner did not err in rejecting claims 1–8, 14–20, and 23–30,
and 36–39 but erred in not rejecting claims 9–13 and 31–35.
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DECISION
We affirm the Examiner’s rejection of claims 1–4, 18–20, and 23–26
under 35 U.S.C. § 102(e) as anticipated by Nightingale; claims 5–8 and 27–
30 under 35 U.S.C. § 103(a) as unpatentable over Nightingale; and claims
14–17 and 36–39 under 35 U.S.C. § 103(a) as unpatentable over Devins.
We reverse the Examiner’s decision not to adopt the rejection of
claims 9–13 and 31–35 under 35 U.S.C. § 102(e) as anticipated by
Nightingale.
Pursuant to 37 C.F.R. § 41.77(a), the above-noted reversal constitutes
a new ground of rejection. Section 41.77(b) provides that “[a] new ground
of rejection . . . shall not be considered final for judicial review.” That
section also provides that Patent Owner, WITHIN ONE MONTH FROM
THE DATE OF THE DECISION, must exercise one of the following two
options with respect to the new grounds of rejection to avoid termination of
the appeal proceeding as to the rejected claims:
(1) Reopen prosecution. The owner may file a
response requesting reopening of prosecution before
the examiner. Such a response must be either an
amendment of the claims so rejected or new evidence
relating to the claims so rejected, or both.

(2) Request rehearing. The owner may request that
the proceeding be reheard under § 41.79 by the Board
upon the same record. The request for rehearing must
address any new ground of rejection and state with
particularity the points believed to have been
misapprehended or overlooked in entering the new
ground of rejection and also state all other grounds
upon which rehearing is sought.

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In accordance with 37 C.F.R. § 41.79(a)(1), the “[p]arties to the
appeal may file a request for rehearing of the decision within one month of
the date of: . . . [t]he original decision of the Board under § 41.77(a).” A
request for rehearing must be in compliance with 37 C.F.R. § 41.79(b).
Comments in opposition to the request and additional requests for rehearing
must be in accordance with 37 C.F.R. § 41.79(c)–(d), respectively. Under
37 C.F.R. § 41.79(e), the times for requesting rehearing under paragraph (a)
of this section, for requesting further rehearing under paragraph (c) of this
section, and for submitting comments under paragraph (b) of this section
may not be extended.
An appeal to the United States Court of Appeals for the Federal
Circuit under 35 U.S.C. §§ 141–144 and 315 and 37 C.F.R. § 1.983 for an
inter partes reexamination proceeding “commenced” on or after November
2, 2002 may not be taken “until all parties’ rights to request rehearing have
been exhausted, at which time the decision of the Board is final and
appealable by any party to the appeal to the Board.” 37 C.F.R. § 41.81. See
also MPEP § 2682 (8th ed., Rev. 8, July 2010).
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).
Requests for extensions of time in this inter partes reexamination
proceeding are governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.
In the event neither party files a request for rehearing within the time
provided in 37 C.F.R. § 41.79, and this decision becomes final and
appealable under 37 C.F.R. § 41.81, a party seeking judicial review must
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timely serve notice on the Director of the United States Patent and
Trademark Office. See 37 C.F.R. §§ 90.1 and 1.983.

AFFIRMED-IN-PART
37 C.F.R. § 41.77

PATENT OWNER:

MORRISON & FOERSTER LLP
755 Page Mill Road
Palo Alto, CA 94304-1018

THIRD PARTY REQUESTER:

PATENT GROUP C/O DLA PIPER US LLP
203 N. Lasalle Street
Suite 1900
Chicago, IL 60601