Ex Parte 6816457 et al

Patent Trial and Appeal Board

Sep 27, 2013

95000500 (P.T.A.B. Sep. 27, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/000,500 08/28/2009 6816457 32821.0009 5893
7590 09/27/2013
DAVID FINK
7519 APACHE PLUME
HOUSTON, TX 77071
EXAMINER
WEAVER, SCOTT LOUIS
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
09/27/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________
JUNIPER NETWORKS, INC.
Requester and Appellant

v.

ABDULLAH ALI BAHATTAB
Patent Owner and Respondent
____________________

Appeal 2013-000385
Reexamination Control 95/000,500
Patent US 6,816,457 B1
Technology Center 3900

____________

Before HOWARD B. BLANKENSHIP, KEVIN F. TURNER, and
DENISE M. POTHIER, Administrative Patent Judges.

BLANKENSHIP, Administrative Patent Judge.

DECISION ON APPEAL
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STATEMENT OF THE CASE
Third Party Requester Juniper Networks, Inc. appeals under 35 U.S.C.
§ 134(c) (2002) from the final decision of the Examiner favorable to the
patentability of claims 1 and 2, which are all the claims in the patent. Oral
hearing was on April 3, 2013.1 We have jurisdiction under 35 U.S.C. § 315
(2002).
We affirm.

Invention
The 6,816,457 (“'457”) patent relates to predictive population of a
routing table cache. Although a “router” may have other designations, such
as packet switch or gateway, for the purposes of the patent a router is
defined as a switch that is capable of receiving one or more packets, each of
which comprises a destination address, and of routing each packet to an
output port based on that destination address. '457 patent col. 2, ll. 43-56.
The invention is based on the recognition that a high hit ratio can be
achieved in a routing table cache by predicting which entries will be needed
in the cache in the future and by populating the cache with those entries
before they are needed. Id. at col. 1, l. 63 - col 2, l. 2. The patent teaches
that “predictive” population of the routing table cache is superior to prior art
“reactive” techniques, such as “least-recently-used” (LRU). Id. at col. 5, l.
56 - col. 6, l. 17. In particular, the invention applies an autoregressive

1 A hearing transcript of the oral hearing (“Hearing Trans.”) has been
entered into record of this reexamination.
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moving average (ARMA) model structure to selected data sets for predictive
population of the cache. Id. at col. 7, l. 29 - col. 8, l. 35.

Claims
Claims 1 and 2 are independent. We reproduce claim 2 below as
representative.2

2. A method comprising:

receiving a temporal succession of packets at an input
port, wherein each of said packets comprises a destination
address;

generating a temporal model based on the occurrence of
said destination addresses;

populating a routing table cache based on said temporal
model and at least one entry that is stored in a routing table; and

forwarding at least one of said packets from said input
port to one of a plurality of output ports based on said entry that
is stored in said routing table cache;

wherein said temporal model is based on the
autoregressive moving average of the occurrence of said
destination addresses.

2 At least the first occurrence of “said routing table cache” in claim 1 lacks
proper antecedent basis in the claim.
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Prior Art
Bremer 6,032,190 Feb. 29, 2000

Kobayashi 6,768,739 B1 Jul. 27, 2004

David C. Feldmeier, “Improving Gateway Performance with a Routing-
Table Cache,” IEEE, Infocom 1988, pp. 298-307 (“Feldmeier”).

E. Besson & P. Brown, “Performance Evaluation of Hierarchical Caching in
High Speed Routers,” IEEE Globecom 1998, pp. 2640-45 (“Besson”).

Huseyin Simitci et al., “A Framework for Adaptive Storage Input/output on
Computational Grids,” published in Lecture Notes in Computer Science,
Vol. 1586, Springer Berlin, 1999 (“Simitci”).

Joseph L. Hellerstein, “An Introduction to Modeling Dynamic Behavior with
Time Series Analysis,” Lecture in Notes in Computer Science, Vol. 729,
Springer-Verlag, 1993, pp. 203-223 (“Hellerstein”).

Arun K. Iyengar et al., “Analysis and Characterization of Large Scale Web
Server access patterns and performance,” World Wide Web 2 (1999), pp.
85-100 (“Iyengar”).

Panjai Tantatsanawong et al, “Modeling and Forecasting of Hourly
Transactions on a WWW and Proxy Cache Server,” IEEE Internet
Workshop, Feb. 1999, pp. 165-174 (“Tantatsanawong”).

Jean-Chrysotome Bolot & Philipp Hoschka, “Performance Engineering of
the World Wide Web: Application to Dimensioning and Cache Design,”
Proceedings of the Fifth International World Wide Web
Conference on Computer Networks and ISDN Systems, Vol. 28,
Issues 7-11, May 1996, pp. 1397-1405 (“Bolot”).

Requester’s Contentions
Requester contends that the Examiner erred in not entering any of 20
proposed rejections under 35 U.S.C. § 103(a) against claims 1 and 2. App.
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Br. 2-4. Requester relies on nine references that Requester groups into two
classes designated as “Router” and “ARMA” references. Requester
proposes to combine each of the four “Router” references with each of the
five “ARMA” references against each of claims 1 and 2. Id.

Router References
Feldmeier
Besson
Kobayashi3
Bremer4

ARMA References
Simitci
Hellerstein
Iyengar
Tantatsanawong
Bolot

ANALYSIS
Analogous Art
A reference qualifies as prior art for an obviousness
determination under § 103 only when it is analogous to the

3 The parties refer to “the '739 patent.”

4 The parties refer to “the '190 patent.”
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claimed invention. “Two separate tests define the scope of
analogous prior art: (1) whether the art is from the same field of
endeavor, regardless of the problem addressed and, (2) if the
reference is not within the field of the inventor's endeavor,
whether the reference still is reasonably pertinent to the
particular problem with which the inventor is involved.”

In re Klein, 647 F.3d 1343, 1348 (Fed. Cir. 2011) (citations omitted).
The Examiner submits that “[w]ith respect to the secondary [ARMA]
references, each reference was indicated as being in a different field of
endeavor, not a similar device, or non-analogous to the '457 patent and the
primary references with which it was proposed to be combined.” Ans. 5.
The Answer does not further discuss the alleged non-analogous nature of the
art. However, the Answer incorporates by reference the Right of Appeal
Notice (RAN). The RAN indicates that the '457 patent’s field of endeavor is
“router cache population management” (RAN 7), and that references such as
Simitci are “not clearly analogous art” and “in a different field of endeavor”
(id. at 9).
Patent Owner in its response does not rely on the doctrine of non-
analogous art. See Respondent Br. 4-5. Moreover, we find no reasoning or
explanation from the Examiner in the Answer or the RAN in support of why
the '457 patent is found to be limited to the narrowly defined field of router
cache population management, such that each of the ARMA references fails
to meet at least the first prong in the inquiry with respect to analogous art.
Rather than making findings in the first instance to confirm or refute the
patent’s alleged field of endeavor, we will presume that all the references to
be applied in this case are analogous art and thus may properly be applied
against the subject patent in a rejection for obviousness under § 103(a).
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The Proposed Rejections
It is undisputed that each Router reference discloses a router in
accordance with the requirements of claim 1, and consistent with the method
of claim 2, except for populating a routing table cache based on the
autoregressive moving average of the destination addresses.5 The Router
references describe various prior art techniques for populating a routing
table cache, such as LRU, which is acknowledged as prior art by the '457
patent (col. 5, l. 56 - col. 6, l. 18).
For purposes of this appeal, Requester relies on the obviousness
rationale that “one of ordinary skill in the art seeking to increase the speed of
each Router reference would have been motivated to modify each Router
reference to take advantage of the ARMA-based model taught by each
ARMA reference.” App. Br. 6. Accordingly, our analysis will be limited to
determining whether the evidence upon which Requester relies provides
sufficient support to establish that the alleged motivation arose from the
prior art, without the benefit of hindsight with respect to the '457 patent.
“The ‘motivation-suggestion-teaching’ requirement protects against the
entry of hindsight into the obviousness analysis, a problem which § 103 was
meant to confront.” In re Kahn, 441 F.3d 977, 986 (Fed. Cir. 2006).
A basic flaw that is common to Requester’s proposed rejections is the
lack of evidence that one of ordinary skill in the art, in seeking to increase

5 The Examiner finds that Bremer “refers to a most frequently used
technique.” RAN 9. Bremer discusses prior art (background) routers that
use routing table caches, but itself uses a hardware based data packet
processing system (e.g., Fig. 5).
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the speed of a router, would have investigated an ARMA-based model for
populating the routing table cache. Requester’s position appears to be that
ARMA-based models are more accurate for populating a cache than the
prior art techniques described by the Router references. The '457 patent is
consistent with, and indeed supports, that view, as it teaches using an
ARMA-based model in lieu of prior art techniques such as LRU.
However, Requester cannot rely on the teachings of the subject patent,
as if part of the prior art, to show obviousness of the claimed subject matter.
Requester submits that it “explained that the more accurate a cache is
populated, the faster the device or system employing the cache will
perform,” citing pages 6 and 11 of the Appeal Brief. Rebuttal Br. 9. We
find no such “explanation” in the Appeal Brief. Requester’s citation to
evidence of a suggestion in the prior art that higher accuracy equates to
increased speed appears to be confined to page 171 of the Tantatsanawong
reference -- “[h]igher accuracy in cache population speeds up the entire
system.” App. Br. 11. Requester does not quote from, or otherwise identify,
the precise disclosure in Tantatsanawong that is thought to support the view
that higher accuracy in cache population “speeds up the entire system” and
thereby, presumably, speeds up population of a routing table cache.
Tantatsanawong does not discuss populating caches in a router, but is
directed to forecasting transactions on World Wide Web (WWW) and
associated proxy cache servers. Tantatsanawong 171-72; Fig. 4 (at 171).
The only mention of an ARMA model in Requester’s indicated section of
the reference refers to an adjustment to the ARMA model, and the statement
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that the “ARMA model has been proven successful for the short-term
prediction of time series.” Id. at 171.
On the other hand, Feldmeier teaches that a way to increase gateway
throughput is to reduce the routing-table lookup time per packet. Feldmeier
298 (Abstract). “Processing time per packet is reduced if average routing-
table access time is reduced, and an economical way to reduce access time is
to use a cache.” Id. at 307. Feldmeier thus provides evidence that one of
ordinary skill in the art seeking to increase the speed of a router would have
investigated ways to decrease average routing table access, with the ultimate
goal of reducing the processing time per packet. Requester has provided
insufficient evidence to support the theory that one of ordinary skill in the art
would have looked to techniques for more accurate cache population without
considering that the critical goal unique to routers is to decrease the
processing time per packet. For example, Tantatsanawong applies an
ARMA-based model as it relates to proxy caching -- buffering recently used
WWW documents. Tantatsanawong 165 (col. 2). One skilled in the art
would recognize that retrieving a WWW document does not compare to the
time requirements in the processing of a packet in a packet-switched
network. The electronic data that make up a WWW document would be
placed into numerous packets for transfer across such a network, with each
packet requiring individual processing in a router. See, e.g., Bremer col. 1,
ll. 11-27 (Internet Protocol data packet traffic).
Our concerns regarding the time constraints in router operation, as
opposed to the other devices and systems to which the ARMA references are
directed, were not allayed by statements at the oral hearing. Patent Owner’s
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representatives reported that “Juniper chose a caching scheme different than
the one that Dr. Bahattab has because that caching scheme is one that Dr.
Bahattab came up with that is too inefficient for the high speed routers that
Juniper has. That is the reason Juniper does not deploy it.” Hearing Trans.
11. “ARMA has been, or Juniper has found that ARMA is too slow for its
own products. But it’s not too slow for other routers in the industry.” Id. at
12. However, the contention that ARMA is “not too slow” for other routers
in the industry is unsupported by substantial evidence in this record.
Further, as the Examiner indicates, Feldmeier teaches that LRU cache
management may be the most effective technique for populating a routing
table cache, at least for caches of 50 slots or less. Feldmeier 307( col. 1).
For large caches, back-to-back caches having LRU and FIFO (first in first
out) implementation may be the most effective. Id. (col. 2). Besson teaches
that the LRU policy is implemented in all high-speed routers, “as it is the
optimal one for identical size of data.” Besson 2641 (col. 1). Feldmeier and
Besson are representative of the conventional wisdom at least as late as
1998, consistent with the '457 patent’s observation that the LRU technique
has a high hit ratio relative to all known routing table cache replacement
techniques in the prior art. '457 patent col. 6, ll. 6-9. We disagree with
Requester to the extent that Feldmeier provides motivation for using an
ARMA model in its disclosure that “[o]bviously, a better cache
implementation would increase performance.” Feldmeier 307 ( col. 1);
Rebuttal Br. 4. Feldmieir goes on to specify how to improve cache
implementation, such as using “a replacement strategy approximating LRU,”
which may be less expensive. Feldmeier 307, col. 1.
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The ARMA References
We address each of the ARMA references in the context of
Requester’s remarks in the Appeal Brief relating to Feldmeier in view of the
ARMA references. However, our reasons for determining that Requester’s
arguments are not persuasive, infra, are substantially the same for the other
proposed rejections, as Requester does not rely on any unique teachings in
any of the Router references in its discussion of the non-entered rejections.

I. Simitci
Simitci discusses ARIMA (Autoregressive Integrated Moving
Average) time series analysis. Simitci § 6.1. Requester submits that
ARIMA is a general class of univariate time-series models, which includes
AR (autoregressive), MA (moving average), and ARMA models as special
cases. App. Br. 7. Requester alleges that each reference that discloses
ARIMA also “teaches” ARMA to one of ordinary skill in the art. Id.
However, Requester does not explain how disclosure of a general class of
models would “teach” any particular special case within the class -- e.g.,
ARMA.
In any event, Requester states that “Simitci teaches that an ‘ARIMA
(Autoregressive Integrated Moving Average) time series analysis can be
used to create quantitative forecasts of future access patterns and trends.’
(Id. at § 6.1.).” App. Br. 7. We agree with Requester. Requester continues,
however, that Simitci discloses that an ARIMA model “would allow for the
cache to be populated ‘based on anticipated [need],’ which is more accurate
than LRU, MRU, or random replacement, which rely on ‘observed need.’”
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[citing § 6.1 of Simitci]. App. Br. 7. We disagree. Simitci discusses time
series analysis as a complement to using artificial neural networks (ANNs)
to classify file access patterns during application execution. Simitci §§ 6,
6.1. Simitci does not compare LRU, MRU, or random replacement
techniques to ARIMA as applied to input/output pattern forecasting, nor to
any other application. See id. § 6.1. In fact, for cache management, the
system that Simitci describes uses LRU, MRU (most recently used), and
random replacement policies. Id. § 3.1.
Finally, Requester submits that Simitci states that “‘We believe
[ARIMA-based] techniques can be profitably applied to task scheduling and
network protocol configuration.’ (Id. at § 7.)” App. Br. 7 (alteration in
brief). We disagree. Simitci specifically states that “[w]e believe they can
be profitably applied to task scheduling and network protocol
configuration.” Simitci § 7. The “they” to which Simitci refers is “the
closed loop and interactive performance steering techniques developed for
PPFS II.” Id.; see also Simitci § 2 (“PPFS II integrates real-time access
pattern classification software . . . and a fuzzy logic decision mechanism . . .
for dynamically identifying access patterns and adaptively choosing file
system policies.”). In contradistinction, the ARIMA time series analysis for
forecasting an application’s input/output patterns is constructed offline. Id.
§ 6.1 (final paragraph); § 7 (second paragraph).

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II. Hellerstein
Requester admits that Hellerstein suggests using ARMA to model
dynamic behavior in information systems, such as that needed for the design
of disk caches. App. Br. 8; Hellerstein 203. Requester submits that
“Hellerstein teaches that temporal models can accurately characterize packet
interarrival times in communication networks.” App. Br. 9. Actually,
Hellerstein discloses that “[a]nother case in which time serial behavior is
important is characterizing packet interarrival times in communications
networks.” Hellerstein 206. Hellerstein cites to a paper (Reference 7),
which is not proposed as evidence in support of a rejection, and which thus
cannot be relied upon in this appeal to demonstrate that one of ordinary skill
in the art would have appreciated that applying an ARMA model to populate
a routing table cache might speed operation of the router. Moreover,
Requester provides no evidence or explanation in support of why the
disclosure that time serial behavior is important in characterizing packet
interarrival times in communications networks would provide motivation for
the ordinary artisan to apply an ARMA model to the process of populating a
routing table cache in order to improve router speed.

III. Iyengar
As Requester acknowledges, Iyengar uses ARMA to model Web
(WWW) server access to improve Web server caches. App. Br. 10.
However, Requester does not identify any teaching that might suggest router
operation would be faster with use of an ARMA model. In fact, Iyengar
discloses a router that connects Web servers and client systems (Iyengar 90,
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Fig. 1). Requester has not identified any hint in the reference that Iyengar
contemplated using the described ARMA model in operation of the router --
assuming that the router contains a cache -- or that applying an ARMA
model to populate a routing table cache would increase the speed of the
router.

IV. Tantatsanawong
Requester submits that Tantatsanawong teaches that “the
performance” of Internet traffic “may be improved” through the use of a
proxy cache. App. Br. 11. Requester submits further that “[l]ike the
routing-table cache in Feldmeier, a proxy cache functions by ‘buffering
recently used WWW documents for the next use.’ (Id. at 165.)” We
disagree. Requester has not shown that conventional routing table caches
functioned by “buffering recently used WWW documents for the next use.”
Further, as noted supra, we are not persuaded that Tantatsanawong teaches
that “higher accuracy” in cache population “speeds up the entire system,” or
more to the point, that an ARMA-based model for populating a routing table
cache would “speeds up” router operation.

V. Bolot
Requester submits that Bolot teaches that Web server performance
“can be increased” through the use of a proxy server or proxy cache. App.
Br. 12. Requester submits further that according to Bolot, a proxy server
returns the locally cached copy of a document named in a URL (Uniform
Resource Locator) from a previous client request if the document is
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requested again. “This is the same type of cache functionality taught by
Feldmeier. (Feldmeier at 298-98 [sic].)” We disagree. Requester has not
shown that the router cache in Feldmeier (or any conventional routing table
cache) functioned by returning a locally cached copy of a document named
in a URL from a previous client request if the document is requested again.
We agree with Requester (App. Br. 12) that Bolot teaches that LRU is not
necessarily the optimal cache-replacement algorithm, but we add that Bolot
compares an LRU algorithm with an algorithm that takes all state variables
into account in its study of designing efficient cache replacement algorithms
for Web proxy servers. Bolot § 3. The relevance to using an ARMA model
in a router has not been established.
Summary/Conclusion
In view of the foregoing, we find that Requester has not demonstrated,
by a preponderance of the evidence, that the subject matter as a whole of
claims 1 and 2 would have been obvious to one of ordinary skill in the art.
We sustain the Examiner’s refusal to enter any of the proposed rejections.
DECISION
The Examiner’s decision favorable to the patentability of claims 1 and
2 is affirmed.
Requests for extensions of time in this proceeding are governed by 37
C.F.R. §§ 1.956 and 41.79(e).

AFFIRMED
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Patent Owner:

David Fink, Esquire
Fink & Johnson
7519 Apache Plume Drive
Houston, TX 77071

Third Party Requester:

Patrick J. Lee, Esquire
Alan M. Fisch, Esquire
Fisch Hoffman Sigler, LLP
5335 Wisconsin Avenue NW
8th Floor
Washington, DC 20015

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