Ex Parte 6751696 et al

Patent Trial and Appeal Board

Oct 11, 2013

95001133 (P.T.A.B. Oct. 11, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,105 11/06/2008 6751696 38512.12 4093
22852 7590 10/11/2013
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
10/11/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,133 12/31/2008 6751696 8963.002.285 1711
22852 7590 10/11/2013
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
10/11/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

MICRON TECHNOLOGY, INC.
Requester, Appellant

v.

RAMBUS, INC.
Patent Owner, Respondent
____________

Appeal 2012-002081
Inter Partes Reexamination Control No. 95/001,105 & 95/001,133
United States Patent 6,751,696 B2
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON REQUEST FOR REHEARING
Appeal 2012-002081
Reexamination Control Nos. 95/001,105 & 95/001,133
Patent 6,751,696 B2

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Rambus seeks relief in its Patent Owner’s Request for Rehearing, see
37 C.F.R. § 41.79, from the Patent Trial and Appeal Board Decision (Dec. 7,
2012) reversing the Examiner’s decision not to maintain the rejections of
claims 1 and 4 of the ‘696 Patent. (See Reh’g Req. 1.) In response to
Rambus’s Rehearing Request, Micron filed Third Party Requestor’s
Comments to Patent Owner’s Request for Rehearing Pursuant to 37 CFR §
41.79.
DISCUSSION
Claim 1 recites “a first operation code in response to a rising edge
transition of the external clock signal.” Claim 1 also recites a delay value
which is stored in response to the first operation code: “a programmable
register to store a value which is representative of an amount of time to
transpire before the memory device outputs data, wherein the memory
device stores the value in the programmable register in response to the first
operation code.”
Focusing on the first operation code, Rambus contends that “the
Board failed to show that the signals sent over the VM Bus that are alleged
to be the first operation code are sampled in response to a rising transition of
an external clock signal.” (Reh’g Req. 3.) Micron responds that, in Bennett,
“a specific combination of logical values of three signal lines controls the
action of setting the configuration register.” (Comments 3.)
Micron relies, inter alia, on the following Bennett passage:
The maintenance processor effectuates the impressing of a
pertinent bit pattern upon the configuration register within each
Versatile Bus Interface Logics by respectively emplacing a
logical Low on signal (L) SCAN/SET ENABLE, a logical Low
Appeal 2012-002081
Reexamination Control Nos. 95/001,105 & 95/001,133
Patent 6,751,696 B2

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on signal (L) SCAN/SET SELECT (L=SET), a logical High on
signal (H) SEL LOOP D, and an appropriate logical High or
Low level of signal (H) SET DATA as a respective logical "1"
or "0" is desired to be set within each bit position of Loop D as
gated by clock φ2.

Id. (quoting Bennett at col. 125, ll. 46-56).
This passage reveals that Bennett discloses using the external clock
φ2 to gate the “SET DATA as a respective logical ‘1’or ‘0.’” (See
Comments 4; Bd. Dec. 25; see, e.g., Bennett, col. 121, ll. 1-5; col. 122, ll.
39-68; col. 125, ll. 49-56; col. 277, ll.35-40.)
However, this SET DATA appears to be, under one theory, what
Micron relies upon for the “value” recited in claim 1, as opposed to the first
operation code. That SET DATA appears to be transmitted serially over one
of the “three signal lines” that Micron mentions in its argument quoted
supra. That is, Micron relies upon stored values, and in particular, the stored
values related to configuration parameter VI, as reading on the recited
“value” in claim 1. (See App. Br. 9 (relying on values 1 or 3).) According
to Bennett, a three bit field of configuration bits, bits 15-17, represents this
stored configuration parameter VI value, which may take on, according to
generic Figure 3, a configuration digit value of from 1 to 5. (See Bennett
Figure 3.)
Bennett further discloses that “[e]ach of eight, three bit fields, within
the first twenty-four bits of the CONFIGURATION REGISTER will be
loaded with a binary code such as will uniquely associate with a
configuration digit value of one through five.” (Bennett, col. 264, ll. 32-36.)
As indicated above, these bits, three of which correspond to the claimed
Appeal 2012-002081
Reexamination Control Nos. 95/001,105 & 95/001,133
Patent 6,751,696 B2

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value of configuration parameter VI (preferably a digit of 1 or 3, see Bennett
Figures 25a-h), are “successively clocked into the CONFIGURATION
REGISTER” over one of the lines Micron mentions. (See id. at ll. 66-67.)
Mr. Murphy, Rambus’s expert, explains that this successive clocking
appears to relate to a serial data line transfer – i.e., one of the data lines
mentioned by Micron as transferring successively the three bits
corresponding to the recited value in claim 1.
Mr. Murphy explains as follows:
In order to configure the configuration register, Bennett does
not teach providing any sort of “operation code,” such as the
alleged operation codes in Figures 31 and 34, over the Versatile
Bus, but instead has the Maintenance Processor use the separate
VM Node Interface to serially shift in the bits that will
eventually fill up the configuration register. This is
accomplished by holding certain control signals on the VM
Node interface at a particular voltage level for an extended
period of time in order to indicate that the bits that are being
serially presented on another signal line during that time
should be shifted through a chain of registers. (Bennett at col.
264, ll.. 57-66; col. 125, ll. 29-37 and 46-56.) Such serial
shifting of bits on such an interface does not correspond to the
storage of a value in a register in response to an operation
code sampled in response to a transition of a clock signal as
required by the claim.

(Murphy Decl. ¶ 134 (emphasis added).)
In other words, Micron relies upon the other two data lines to carry a
code, which Mr. Murphy describes above as “certain control signals . . . at a
particular voltage level,” as reading on the claimed “first operation code.”
However, Micron does not explain how the first operation code is sampled
in response to a rising edge transition of the external clock signal, as claim 1
Appeal 2012-002081
Reexamination Control Nos. 95/001,105 & 95/001,133
Patent 6,751,696 B2

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requires. The logical code, or voltage, on these two data lines, appears to be
impressed on the data line and held there as types of enable signals, as Mr.
Murphy generally explains. (See, e.g., Bennett, col. 121, ll. 1-5; col. 122, ll.
39-68; col. 125, ll. 49-56; col. 277, ll.35-40.) Micron and the Examiner do
not explain, and Bennett does not indicate, that these impressed voltages (or
codes, enable signals, etc.) on the other two signal lines are “sample[d] . . .
in response to a rising edge transition of the external clock signal,” as claim
1 requires.
Possibly to address this sampling feature, in its Rebuttal Brief, Micron
relies on an alternative theory in which the operation code and the value to
be stored are the same: “In other words, the ones and zeros comprising the
code to be stored into the configuration register instructs the receiving
device to perform the storing function.” (Reb. Br. 7.) As to this alternative
theory, Rambus maintains that these bits, which represent the delay value (in
bit field 15-17) according to Micron, do not specify an action.
In other words, Rambus reasons that the operation code must be “one
or more bits to specify a type of action.” (Reh’g Req. 2 (citing Murphy
Decl. at ¶ 132 and Resp. Br. at 7-8).) Micron does not particularly dispute
the definition, but maintains that Bennett meets it: “Each individual bit [of
the value] specifies that a specific value be stored into the configuration
register – either a one or a zero.” (Reb. Br. 8.)
Based on this record, Rambus’s response appears to be more
persuasive. Notwithstanding Micron’s position, a different bit (1 or 0) for
the claimed delay value does not specify a different type of action. Stated
differently, either bit value will be stored regardless of whether it is a one or
Appeal 2012-002081
Reexamination Control Nos. 95/001,105 & 95/001,133
Patent 6,751,696 B2

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a zero; therefore, the bit does not specify a type of action. This makes some
sense in light of the discussion supra; the two enable signals appear to cause
or specify the requisite action (but the record does not show that those two
enable signals are sampled in response to a rising edge transition).
According to the ‘696 Patent: “Access Type [1:3] equal to zero
indicates a control register request and the address field of the packet
indicates the desired control register.” (‘696 Patent, col. 10, ll. 2-4.) This
sentence appears to relate to the claimed first operation code, so that either a
control request or a specific address indicates a desired respective action or
control register in which to store a delay value. In addition, the ‘696 Patent
describes that certain bytes of the same packet that includes the operation
code may also include or represent what appears to be the claimed delay
value. (See id. at ll. 2-8.) However, Micron does not provide supporting
rationale for reading the different recitations of the claimed operation code
and delay value as the same bit or bits.
Micron’s Rebuttal Brief also relies partially on the Examiner’s Right
of Appeal Notice. (Reb. Br. 8 (citing RAN at 65).) The Examiner reasons
that “under the broadest reasonable interpretation of the claims, the term
‘operation code’ is not defined.” (RAN 60-61.) However, Micron does not
appear to contest Rambus’s definition, supported by its expert, Mr. Murphy,
in a material manner. To the contrary, Rambus cites to Exhibit I, to show
that Micron has “argued” in other proceedings for essentially the same
definition, albeit one that includes a request packet. (See Reh’g Req. 2, n. 2
(discussing Ex. I, Joint Claim Construction at 23-24 in a related District
Court proceeding).)
Appeal 2012-002081
Reexamination Control Nos. 95/001,105 & 95/001,133
Patent 6,751,696 B2

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CONCLUSION
Rambus shows that the Board overlooked or misapprehended a
material point in reversing the Examiner’s decision not to reject claims 1 and
4. In light of the showing, Rambus’s remaining contentions are moot.

REHEARING DECISION
We modify the Decision, which reverses the Examiner’s decision not
to reject claims 1 and 4, to reflect an affirmance of the Examiner’s decision
not to reject claims 1 and 4.
This Rehearing Decision, is hereby designated, with respect to the
issues addressed here, “in effect, a new decision, . . . [and] any party may
within one month of the new decision, file a further request for rehearing of
the new decision under this subsection. Such request for rehearing must
comply with paragraph (b) of this subsection.” 37 C.F.R. § 41.77 (d).

GRANTED

Appeal 2012-002081
Reexamination Control Nos. 95/001,105 & 95/001,133
Patent 6,751,696 B2

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PATENT OWNER:

Finnegan, Henderson, Farabow,
Garrett & Dunner, LLP
901 New York Avenue, NW
Washington, DC 20001-4413

THIRD PARTY REQUESTERS:

Novak Druce & Quigg, LLP
(NDQ Reexamination Group)
1000 Louisiana Street
Fifty-third Floor
Houston, TX 77002

David M. O'Dell, Esq.
Haynes & Boone, LLP
IP Section
2323 Victory Avenue
Suite 700
Dallas, TX 75219