Ex Parte 6591353 et al

Patent Trials and Appeals Board

Feb 13, 2013

95001169 - (S) (P.T.A.B. Feb. 13, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,169 04/21/2009 6591353 2805.003REX9 7283
22852 7590 11/10/2015
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/10/2015 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

RAMBUS, INC.
Patent Owner, Appellant

v.

NVIDIA, CORP.
Requester (Withdrawn)
____________

Appeal 2013-000562
Inter Partes Reexamination Control No. 95/001,169
United States Patent 6,591,353 B1
Technology Center 3900
____________

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON REMAND BY THE FEDERAL CIRCUIT
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STATEMENT OF THE CASE
This case returns to the Board upon a remand from the Federal
Circuit. In re Rambus, Inc., 560 F. App’x 1005 (Fed. Cir. 2014) (“Remand
Order”). In the Remand Order, the Federal Circuit remanded the case for the
Board “to reconsider its decision in light of this court’s decision in” Rambus,
Inc. v. Rea, 527 F. App’x 902 (Fed. Cir. 2013) (“Rambus-Rea”) (not for
publication). Id. at 1006. We have jurisdiction under 35 U.S.C. §§ 134(b)
and 306.
After considering Rambus-Rea, we determine that it does not alter the
prior outcome, although guidance there lends support to our earlier outcome
in this case for the reasons explained below. In a split decision, the Rambus-
Rea court reversed the Board’s anticipation rejection of Rambus’s U.S.
Patent No. 7,287,109 (the “’109 patent”) by a prior art Rambus patent, U.S
Patent No. 6,584,037 (“Farmwald”). The patent under reexamination here,
U.S. Patent No. 6,591,353 (the “’353 patent”) is a continuation of the ’109
patent. One of the issues in this reexamination proceeding involves an
obviousness rejection based on another prior art Rambus patent, U.S.
5,319,755 (“Farmwald ‘755”)––Farmwald ’755 is a parent patent of the
prior art Farmwald patent involved in Rambus-Rea.
Rambus-Rea noted that “Farmwald’s parent patent, U.S. Patent No.
5,319,755 (Farmwald ’755), shares the same specification as Farmwald and
was cited by the Examiner during initial examination of the ’109 Patent
application.” Rambus-Rea, 527 F. App’x at 905. Rambus-Rea also made
the following observations about the importance of considering International
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Trade Commission (“ITC”) proceedings and other proceedings at the
USPTO:
Further, the ’109 Patent has been widely litigated in at
least seven causes of action. In at least two of these actions,
Farmwald or Farmwald ’755 were directly in front of the
tribunal. In ITC Investigation No. 337–TA–661, the
Respondents and Staff Attorney advanced similar arguments as
the Board does in the present case, but the Commission
affirmed the ALJ’s conclusion that Farmwald ’755 does not
anticipate the ’109 Patent. Certain Semiconductor Chips
Having Synchronous Dynamic Random Access Memory
[Controllers] and Prods. Containing Same, Inv. No. 337–TA–
661, 2011 WL 6016982 (October 1, 2011)[“’661 Comm’n
Dec.”]. Likewise, in ITC Investigation No. 337–TA–753, the
ALJ held in an Initial Determination that Farmwald does not
anticipate the ’109 Patent. Certain Semiconductor Chips and
Prods. Containing Same, Inv. No. 337–TA–753, 2012 WL
927056 (March 2, 2012) [(“’753 Init. Det.”)].
Notwithstanding the above, the Board found in the
present case that Farmwald anticipates the ’109 Patent. In other
words, a reference that was overcome during initial
examination, distinguished as prior art in the patent
specification, and found not to anticipate by at least two
different tribunals, now—according to the Board—discloses
each and every element of the claims. The result is somewhat
surprising, especially with nothing in the record indicating
whether the Board considered these prior decisions. Upon
comparison of the relevant claims, this court concludes that
Farmwald does not anticipate the ’109 Patent’s claims.
Rambus-Rea, 527 F. App’x at 905–906 (emphasis added).
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The passage reveals at least a suggestion for the Board to record and
consider prior ITC investigations and prosecution history.1 Following this
guidance, we record that we are aware of, and considered, all relevant
proceedings before the USPTO and the ITC to which the parties directed us
and others. We also note that the ITC similarly found, as we find here, that a
patent to Hayes, U.S. Patent No. 5,218,684, anticipates claim 11 of the ’353
patent. ’753 Init. Det. *53, *67–*69. Rambus made similar arguments to
those made here––i.e., arguing that the Hayes DS (data strobe) signal does
not constitute a strobe signal and that the claimed memory device must
constitute a single chip. The ALJ there, citing record evidence there and
findings by the ’353 reexamination Examiner involved here, found
otherwise. Id. at *67–*68.
On the other hand, in another proceeding cited by Rambus-Rea, the
ITC determined that respondents in that case had not shown that the
Farmwald ’037 TrncvrRW signal, the same signal at issue here and

1 As the passage states, the court majority saw “nothing in the record
indicating whether the Board considered” the prior ITC proceedings.
Notwithstanding this admonition, the Board did note on the record twice that
the ’109 patent had been reviewed by the ITC: “Appellant and Requestor
refer to several related judicial and other proceedings including inter partes
and ex parte reexaminations, International Trade Commission proceedings,
and Federal District Court and Circuit Court proceedings in their briefs.”
Rambus, Inc. v. NVIDIA Corp., No. 2011-005255, 2011 WL 3883267, at *1
(BPAI September 1, 2011). The Board also cited and addressed Rambus’s
specific ITC-based arguments in the Board’s rehearing decision. See
Rambus, Inc. v. NVIDIA Corp., No. 2011-005255, 2012 WL 985601, at *8
(BPAI March 21, 2012) (stating that “Rambus’s new arguments and
proffered evidence (see Rehearing Req. 5 (citing, inter alia, ‘ITC’ findings))
fail to show error in the Decision,” and addressing the arguments).
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disclosed in Farmwald ’755, constitutes the claimed strobe signal. See ’661
Comm’n Dec.” at *107. However, in contrast to this proceeding, in the ‘661
Investigation, the ALJ determined that respondents “simply ma[de] . . .
conclusory arguments that consist of a single paragraph. . . . [and] failed to
meet the clear and convincing standard necessary to invalidate both the
Barth I Patents in view of Farmwald based on obviousness.” Id. Further,
although not directly relevant here, based on Farmwald ’037 in combination
with prior art not before us, the ITC found obvious asserted claims in the
’353 patent and other similar claims in other related patents. See ’753 Init.
Det. at *117–*119 (by “clear and convincing evidence”).
We find based on different and additional evidence (and a different
evidentiary standard) than that at the ITC, that the Farmwald ’755
TrncvrRW signal at least suggests, if not constitutes, a strobe signal as set
forth in the claims. Primarily, the ITC does not appear to have considered
(in the depth involved here) the findings about what the TrncvrRW signal
does––including the fact that Farmwald ’755 specifically discloses that the
TrncvrRW signal is bussed to all devices on the transceiver bus, including
memory devices and memory sticks (also known as primary bus units).
Compare findings and analysis below, with ’753 Init. Det. at *69 (citing the
’661 ITC proceeding as determining that Farmwald ‘037 did not anticipate
the “Barth patents”––i.e., the ’109 and ’353 patents); ’661 Comm’n Dec. at
*40, *48, *90–91, *107 (discussing Farmwald’s TrncvrRW signal, but
noting the cursory allegation of obviousness by respondents). In addition, in
discussing anticipation (which is not involved here), the ITC pointed to
preliminary findings by the original prosecution examiner at the USPTO and
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noted that because Farmwald was considered there, “proving invalidity is
particularly heavy.” See id. at *90.
The Remanded Decision
PTAB2013-000562
Prior to the remand from the Federal Circuit, this reexamination
proceeding returned to the Board after a prior remand to the Examiner by the
Board and the consequent Examiner’s determination under 37 C.F.R. §
41.77(d) (April 19, 2012), which responds to the Board’s rejections
designated as new grounds in the Board’s previous inter partes Decision on
Appeal, NVIDIA, Corp. v. Rambus, Inc., 2011-010623 (BPAI Jan. 24, 2012)
(“’623 Bd. Dec.”) involving the ’353 patent.
The instant Decision effectively replaces, but refers to and
incorporates by reference, the remanded Decision, Rambus, Inc. v. NVIDIA,
Corp., 2013-000562 (PTAB Feb. 13, 2013) (“’562 Bd. Dec.”). As we did in
the previous ’562 Decision, we also hereby incorporate and sustain the
earlier Decision, the ’623 Decision, to which the Board added new grounds
of rejection (thereby giving rise to appeal number PTAB 2013-000562).
The instant Decision, bearing the same appeal number as the remanded ’562
Decision, primarily stands on its own, but refers back to the earlier ’562 and
’623 Decisions where appropriate. In the ’623 Decision, the Board, in a
bifurcated decision, affirmed the Examiner’s decision to maintain the
rejection of claims 1, 5, 7, 11, 14, 19, and 23 cross-appealed by Rambus, and
reversed the Examiner’s decision not to reject claims 1–26 appealed by
Third-Party Requester NVIDIA. See ’623 Bd. Dec. 45. As to the reversal,
pursuant to 37 C.F.R. § 41.77(b), the ’623 Decision reversed the portion of
the Examiner’s Answer (which incorporates by reference the Examiner’s
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Right of Appeal Notice) in which the Examiner decided not to maintain
NVIDIA’s proposed rejections, and the Board designated the reversal “a
new ground of rejection.” See ’623 Bd. Dec. 45 n.12.2
In response to the ’623 Decision and prior to the Federal Circuit
remand, Rambus elected the 37 C.F.R. § 41.77(b)(1) option of reopening
prosecution before the Examiner to address the new grounds of rejections
(originally proposed by now-withdrawn requester NVIDA Corp) and
presented new evidence to rebut the “new ground[s] of rejection” by the
Board as required under 37 C.F.R. § 41.77 (b)(1) & (d). See Rambus’s
Request to Reopen Prosecution (Feb. 24, 2012) (“Reopen Req.”). Prior to
Rambus’s Reopen Request and after the ’623 Decision, NVIDIA, citing a
settlement with Rambus, withdrew from the reexamination proceeding. See
Notice of Withdrawal of Third-Party Requester’s Appeal and Other Papers
(Feb. 17, 2012); Notice of Non-Participation in Inter Partes Reexamination
(Feb. 8, 2012).
Under 37 C.F.R. § 41.77(d), the prior ’623 Decision is “binding upon
the examiner unless an amendment or new evidence not previously of record
is made which, in the opinion of the examiner, overcomes the new ground of
rejection stated in the [Board’s ’623] decision.” Further pursuant to

2 The rejections were designated as “new ground[s]” under 37 CFR
§ 41.77(b) because the Examiner decided not to adopt or maintain them as
originally proposed by NVIDIA, and the Board reversed the Examiner,
primarily relying on Requester’s showing (adding some facts and analysis
pursuant to the new grounds). See ’623 Bd. Dec. 26–27 (listing NVIDIA’s
originally proposed rejections).
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37 C.F.R. § 41.77(d), the Examiner must consider Rambus’s Reopen
Request and “issue a determination that the rejection is maintained or has
been overcome.”
Pursuant to 37 C.F.R. § 41.77(d), the Examiner determined that
Rambus’s Reopen Request did not overcome the “new ground[s]” of
rejections by the Board. In the Examiner’s Determination (Apr. 19, 2012)
(“Ex. Det.”), the Examiner considered Rambus’s newly submitted evidence
as discussed further below (which includes a Third Supplemental
Declaration by Rambus’s expert Robert J. Murphy and other extrinsic
evidence including publications by one of NVIDIA’s experts). See Reopen
Req. 2; Ex. Det. 2–4.
In addition to the originally affirmed anticipation rejection of claims
1, 5, 7, 11, 14, 19, and 23 based on Hayes, U.S. Patent No. 5,218,684 (June
8, 1993), the following previously instituted “new grounds” of rejection
listed in the ’623 Decision were addressed in the Examiner’s Determination,
sustained by the prior ’562 Decision, and also remain at issue:
Claims 2, 6, 10, 17, 25, and 26 as obvious under 35 U.S.C. § 103(a)
based on Hayes and Bennett et al., U.S. Patent 4,734,909 (Mar. 29, 1988)
(“Bennett”).
Claims 3, 4, 12, 13, 21, and 22 as obvious under 35 U.S.C. § 103(a)
based on Hayes, Bennett, and Inagaki, JP 57-210495 (Dec. 24, 1982).
Claims 12 and 13 as obvious under 35 U.S.C. § 103(a) based on
Hayes and Inagaki.
Claims 2–10, 12–14, 16, 17, and 20–26 as obvious under 35 U.S.C.
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§ 103(a) based on Hayes and Ohshima et al., High Speed DRAMs with
Innovative Architectures, ECC-7:8 IEICE TRANS. ELECTRON. 1303, 1303–
15 (1994) (“Ohshima”).
Claims 1–14, 16, 17, and 19–26 as obvious under 35 U.S.C. § 103(a)
based on Kushiyama et al., A 500-Megabyte/s Data-Rate 4.5M DRAM, 28:4
IEEE J. OF SOLID-STATE CIRCUITS 490, 490–498 (1993), Hayes, and Lu et
al., The Future of DRAMs, 1988 IEEE INTER. SOLID-STATE CIR. CONF.
(ISSCC), DIGEST TECH. PAPERS, 98–99 (1988) (“Lu”).
Claims 1–4, 6–9, 11–13, 15, 16, 18–22, and 24–26 as obvious under
35 U.S.C. § 103(a) based on Farmwald et al., U.S. 5,319,755 (June 7, 1994)
(“Farmwald ’755”) and Lu.
Claims 1–4, 6–9, 11–13, 15, 16, 18–22, and 24–26 as obvious under
35 U.S.C. § 103(a) based on Farmwald ’755 and iRAM, MEMORY
COMPONENTS HANDBOOK (Intel. Corp., 1985) (chapters 1 and 3) (“iRAM”).
See ’623 Bd. Dec. 27.

Exemplary Claims
Exemplary claims of the ’353 patent under reexamination follow:
1. A method of operation in a memory device that
includes a plurality of memory cells, the method comprising:
receiving a command to sample data;
deferring sampling a first portion of the data until an
external strobe signal is detected; and
sampling the first portion of the data from an external
signal line in response to detecting the external strobe signal.
2. The method of claim 1, wherein the first portion of the
data is sampled synchronously with respect to an external clock
signal.
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11. A method of controlling a memory device that
includes a plurality of memory cells, the method comprising:
issuing a first write command to the memory device, the
memory device being configured to defer sampling data that
corresponds to the first write command until a strobe signal is
detected;
delaying for a first time period after issuing the write
command; and
after delaying for the first time period, issuing the strobe
signal to the memory device to initiate sampling of a first
portion of the data by the memory device.
19. A memory device having a plurality of memory
cells, the memory device comprising:
a plurality of input receiver circuits to receive a write
command and sample data that corresponds to the write
command in response to detecting a strobe signal that is
delayed relative to the write command by a first time period.
Another New Ground
As noted above, pursuant to the remand by the Federal Circuit, this
Decision replaces the earlier ’562 Decision. To afford a fair opportunity for
Rambus to respond to any new rationale and facts herein, this Decision
constitutes a new ground under 37 CFR § 41.77(b). In the earlier ’562
Decision, under § 41.77(f) and the new grounds of rejection issued in the
’623 Decision, we “reconsidered the matter and issued a new decision.”
Accordingly, “[t]he new decision [i.e., this instant Decision] . . .
incorporate[s] the earlier [’623 D]ecision, except for those portions
specifically withdrawn.” See 37 CFR § 41.77(f). Only portions (if any) of
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the ’623 Decision (or the ’562 Decision) that conflict with anything herein
are withdrawn.3
Bifurcated Proceeding
Aside from the previous new grounds of rejection listed above
instituted prior to the Federal Circuit remand, as the Examiner reasoned,
Rambus improperly also sought review before the Examiner in the
bifurcated portion of the requested review, which involved the Examiner’s
anticipation rejection of claims 1, 5, 7, 11, 14, 19, and 23 based on Hayes,
which Rambus cross-appealed and which the Board affirmed in the ‘623
Decision. See Ex. Det. 4–5; Reopen Req. 3–14; ’623 Bd. Dec. 7–15.
Reopening prosecution under 37 CFR § 41.77(b) is only “one of the . . . two
[possible] options with respect to the new ground of rejection.” (Emphasis
added). The affirmed rejection was not part of any “new ground of
rejection” under the rule and the Examiner properly refused to consider
Rambus’s request for review of the affirmed rejection (based on Hayes). See
Ex. Det. 4–5. In any event, we considered Rambus’s Reopen Request
arguments against the affirmed rejection to be in the nature of a rehearing
request and proper under the rule for our consideration. See ’623 Bd. Dec.
7–15.
Strobe Signal and Sampling
A primary point of contention involves the “strobe signal” element
recited in the independent claims. Claim 1 recites “sampling the first portion

3 The Examiner’s Determination was adopted and incorporated by reference.
Rambus did not file “comments in response to the [E]xaminer’s
[D]etermination” as allowed under 37 CFR § 41.77(e) to rebut or show error
in the Examiner’s Determination with respect to the new grounds.
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of the data from an external signal line in response to detecting the external
strobe signal.” Claim 19 similarly recites “sample data . . . in response to
detecting a strobe signal.” Claim 11 recites “issuing the write command;
and after delaying for the first time period, issuing the strobe signal to the
memory device to initiate sampling of a first portion of the data by the
memory device.”
The context of the claims at issue employs sampling as writing data
(from an unclaimed bus communicating with an unclaimed controller for
example) to a memory device using the strobe signal to initiate the transfer
(sampling) of data to the memory device. ’353 patent, col. 11, ll. 27–34; col.
22, ll. 55. This comports with the ITC’s analysis. See ’661 Comm’n Dec at
*65, *74, *90–*92. Rambus does not explicitly define the terms. The ITC
determined that the strobe signal, in the context of claim 11, “means a timing
signal to initiate sampling of a first portion of the data by the memory
device.” Id. at *74. The ITC also determined that it means “a timing signal
or signal that initiates sampling and/or indicates when the memory device is
to begin a specified operation, e.g. read, write or transfer.” See id.
In the ’753 Initial Determination (in a determination of obviousness),
the ALJ determined that the claimed “strobe signal” is a “timing signal that
initiates the capture of data off of a bus,” because it “indicat[es] to the
target memory device that data is on the bus.” ’753 Init. Det. at *119
(emphasis added). In other words, in the context of the claims, according to
the ALJ’s rationale, indicating to the target memory device that data is on a
bus is a way of initiating, or causing, sampling by the target memory device
of that data. See id.

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The ’353 patent Specification does not disclose any examples of
initiating sampling in the context of preparing a memory device for sampling
data off a bus. Rather, the ’353 patent Specification generally discloses
“sampling” in the context of transferring data in a way opposite to what is
claimed––i.e., from the memory device to the bus: “According to one
embodiment, the data transfer control information includes data transfer start
information (‘a strobe signal’) sent from the controller to indicate when the
DRAM is to begin sending data . . . .” ’353 patent, col. 8, ll. 59–63.
The ’353 patent Specification does not disclose clearly what governs
the number of clock cycles that transpire between a strobe signal and the
transfer of data from a memory device to a bus. The ’353 patent
Specification shows examples wherein the actual transfer to the data bus
from the memory device begins to occur at least six clock cycles after the
strobe signal is sent. Id. at col. 11, ll. 27–30 (after the strobe at clock cycle
17, “[a]t clock cycle 23 the DRAM begins transferring data beginning at the
address specified in the command control information”); col. 21, ll. 39–46
(in response to strobe at clock cycle 22, data retrieval begins at clock cycle
23, then the DRAM “begins sending the data over [the bus] lines at clock
cycle 28); col. 22, ll. 27–33 (strobe at clock cycle 66, retrieval at clock cycle
66, then the DRAM “begins sending the data over [bus] lines at clock cycle
72”).
These examples show two variations of what “begins” or “initiates”
means in the context of reading data from the memory device: 1) the strobe
initiates the timing data of data retrieval from the memory core (and
thereafter, subsequent data transmission from the memory device to the
bus), or 2) the strobe only initiates the data transmission from the memory
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device to the bus (after a previous command control signal initiates the core
retrieval process). Compare ’353 patent, col. 22, ll. 50–52 (“[t]he timing of
the strobe signal indicates to the DRAM when the DRAM is to begin
retrieving and sending data”) (emphasis added), with ’353 patent, col. 11, ll.
27–34 (a previous command control signal prior to the strobe signal begins
the memory core retrieval process, then responsive to the strobe signal, “the
DRAM begins transferring data beginning at the address specified in the
command control information”).
Rambus has the duty to make the argued claim terms clear and does
not do so here. The ’353 patent Specification simply does not provide
guidance as to what “initiate sampling” means in the context of transferring
data to the memory device. Rambus does not point the Board or the Federal
Circuit to a specific example wherein the ’353 patent Specification involves
“sampling the first portion of the data from an external signal line in
response to detecting the external strobe signal,” as recited in claim 1, or
similarly, with respect to the other claims at issue.
In an illuminating finding and arguments before the ITC, Rambus
alleged that the Hayes DS is not a strobe. The ITC found to the contrary,
finding that Hayes anticipates claim 11 of the ’353 patent, including the
strobe element “by clear and convincing evidence”:
Rambus argues that the data strobe (DS) disclosed in Hayes is
not the claimed “strobe signal” because it merely identifies the
type of information on the bus and does not initiate sampling of
data by the memory device. . . . The evidence shows that Hayes
discloses a bus master that “asserts DS, indicating that the data
is valid on DAL [31:0].” Rambus relied on a similar disclosure
for its infringement analysis, namely that the DQS signal “is the
signal that is used to tell the receiver that data is valid on the
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bus, so not [sic] you can clock those data into . . . its registers.”
. . . . Rambus cannot construe “strobe signal” in two different
ways to prove infringement and avoid invalidity.
’753 Init. Dec. at *69 (citations omitted).
In other words, Rambus itself, according to the ITC, and contrary to
the arguments Rambus makes here, interprets the phrase in claim 11,
“issuing the strobe signal to the memory device to initiate sampling of a first
portion of the data by the memory device,” as broad enough to capture
infringers that use a strobe signal to tell a memory device receiver that data
is valid on the bus. As explained above, this is not inconsistent with the
’353 patent Specification, which is devoid of a specific example regarding
sampling as writing data to a memory device.
Rambus’s Federal Circuit Appeal Brief (filed Nov. 4, 2013––prior to
the remand), states as follows:
Focusing on the claimed “strobe signal,” the specification
states that “the data transfer control information includes data
transfer start information (a ‘strobe signal’) sent from the
controller to indicate when the DRAM is to begin sending data”
in a read operation and when to sample data in a write
operation. [‘353 patent] 8:60–63. The ‘353 patent also states
that “the data transfer control information which controls the
timing of the data transfer ... is sent separately from the
command control information to which it corresponds.” [Id. at]
10:27–30. Thus, the claimed signal itself indicates when the
DRAM is to begin sampling data . . . .
See Rambus Fed. Cir. App. Br. 5–6.
Rambus’s Federal Circuit Appeal Brief fails to clarify how the
“claimed signal itself indicates when the DRAM is to begin sampling data.”
Id. at 6. It does not clarify how the DRAM knows when to begin sampling,
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or what the DRAM does in response to the strobe signal. If the disclosed
examples that transfer data opposite to what is claimed shed any light,
depending on the context, different parts of the DRAM (e.g., the core or
external interface to the bus) may prepare for data transfer––in the core, by
accessing columns or rows without actually sampling any data, etc., or in the
interface, perhaps preparing in some other manner to sample the data––with
sampling occurring in each case sometime after sending and receiving the
strobe signal. Again, no specific example is provided.
Further, Rambus itself points out that “Rambus does not dispute that,
as a general matter, the claims do not exclude other control signals. Thus,
the strobe signal is not necessarily the sole control signal.” See Patent
Owner Rebuttal Brief 15 (Oct. 29, 2010) (“P.O. Reb. Br.”) (emphasis
added). Rambus also notes no sampling occurs until the synchronous clock
signal transpires for one or more cycles after the strobe signal, which is
consistent with the Specification. See id. at n.7. Rambus similarly states
that “Rambus does not contend that sampling must occur immediately after
receipt of the strobe signal.” Id. at 15.
In another place, Rambus treats “causes” and “initiates” as the same:
“The PTAB’s interpretation ignores the requirement that the strobe signal
causes or initiates the sampling and for that reason is thus unreasonably
broad.” Rambus Fed. Cir. App. Br. 12; see also id. at 8 (similar argument).
This still does not explain what exactly the DRAM does or explain what
“causes or initiates” in terms of what the DRAM does when it receives the
strobe and then data from the bus (i.e., reads or samples the data). Again,
the Specification does not provide any clear examples. See In re Morris,
127 F.3d 1048, 1056 (Fed. Cir. 1997) (“It is the applicants’ burden to
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precisely define the invention, not the PTO’s.”); In re Baxter Travenol
Labs., 952 F.2d 388, 391 (Fed. Cir. 1991) (“It is not the function of this
court to examine the claims in greater detail than argued by an appellant . . .
.”).
Rambus also states that a “strobe signal” in the ‘353 patent means
“‘data transfer start information.’” See Reopen Req. 8 (quoting ‘353 patent
at col. 8, ll. 60–63). Rambus fails to explain what this means or how it
corresponds to its other argument that the term involves causation. See id.
It is not clear in context if Rambus implies that strobe signal “includes”
some type of other “information” about when to start apart from its status as
a control timing trigger. Further, the ’353 patent refers to this start
information in the context of “[a]ccording to one embodiment,” which
applies specifically to sending data from the memory device, not sampling
data by the memory device as the claims require. See ’353 patent, col. 8, ll.
59–60.
Accordingly, we interpret the claims in the manner similar to the ITC
and in light of the Specification. As indicated above, there is no dispute,
given Rambus’s arguments, that the ’353 patent does not preclude other
control signals in conjunction with the strobe signal to begin or cause
sampling data (in the context of reading data from the memory device):
“The DRAM does not wait for the strobe signal to begin retrieving the data
from the DRAM core.” ’353 patent, col. 9, ll. 22–24.
Therefore, under a plain and ordinary meaning, in light of the
Specification and arguments Rambus made here and before the ITC, we
determine that skilled artisans would have recognized, that “sampling . . . in
response to . . . the external strobe signal” (claim 1) means “reading data by
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the memory device, partly because, and shortly after, a signal informs the
memory device that data is readily available for reading,” and “issuing the
strobe signal to the memory device to initiate sampling” (claim 11) means
“sending a signal to the memory device to inform it that data is readily
available for reading such that it reads the data shortly thereafter.” In both
cases, the signal constitutes a “but-for” proximate cause of sampling that
occurs shortly thereafter in terms of a number of clock cycles.
Hayes –Anticipation - Rehearing
NVIDIA argued, and the Examiner and the Board found, that the
Hayes slave memory device as represented in the figure below anticipates
claims 1, 5, 7, 11, 14, 19 and 23 of the ’353 patent. See ’623 Bd. Dec. 7–26.
Rambus’s arguments focus on claim 1 which is hereby selected to be
representative of claims 1, 7, 11, and 19. For the most part, notwithstanding
the new evidence proffered, the arguments restate or repackage similar
arguments made in the original appeal without adding sufficient or probative
evidence that shows that the ’623 Decision overlooks or misapprehends the
teachings of Hayes as applied to the claims at issue.

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Hayes’s Figure 2, as annotated by NVIDIA, appears next:

Annotated Figure 2 shows Hayes’s slave memory device. See
NVIDA App. Br. 7 (addressed further in the underlying ’623 Decision). As
the figure shows, the DS is a “DATA STROBE” issued to the memory
device.
Rambus argues, relying on its expert declarant, Mr. Murphy, that the
Hayes DS signal is not an external strobe signal as recited in claim 1. See
Reopen Req. 6–8 (citing Murphy 3rd Supp. Decl. ¶¶ 5–9). The ’623
Decision explains that the DS signal, a “data strobe” signal, constitutes a
strobe signal that “tells the slave memory device in Hayes that the data is
valid on the bus so that the slave memory device knows when to sample
(read) it.” ’623 Bd. Dec. 21. The ’623 Decision reasons that claim 1 does
not require an immediate response to the strobe signal. Id. at 22.
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As the ’623 Decision and the ITC similarly finds, Hayes states that
“‘[d]uring a write cycle, the bus master asserts DS to indicate that DAL
[31:0] contains valid write data. The bus master then deasserts DS to
indicate that it is about to remove the write data from DAL [31:0].’” ’623
Bd. Dec. 9 (quoting Hayes, col. 7, ll. 56–65). The Decision also relies on
Hayes which states that for a write cycle,
[t]he bus master . . . drives data onto DAL 31:0] and asserts
DS [data strobe col. 7, 1. 56], indicating that the data is valid on
DAL [31:0]. If no error occurs, the slave device reads the data
. . . . If an error occurs, external logic asserts ERR, which aborts
the bus cycle.
Hayes, col. 9, ll. 58–63 (emphases added); see ’623 Bd. Dec. 9 (quoting
same).
In general then, there is no real dispute over the fact that the Hayes
slave memory device defers sampling until shortly after it detects the DS,
and that without the DS, the Hayes memory device would not sample data.
Accordingly, and for reasons explained further below, the DS in Hayes
constitutes a “but-for” causation signal that initiates or causes the sampling.
Mr. Murphy’s testimony and Rambus’s arguments do not rebut these
facts or other facts. As an example, Murphy testifies that “multiple signals .
. . are asserted when sampling is alleged to occur in Hayes” and this shows
that none of those signals “initiate sampling.” Murphy 3rd Supp. Decl. ¶ 8.4
As explained above, Rambus agrees that the ’353 patent does not preclude

4 Such arguments and new evidence technically are not proper in a request
for rehearing, but we address it to avoid procedural quagmires and expedite
the proceeding.
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other control signals in conjunction with the strobe signal to begin sampling
data: “The DRAM does not wait for the strobe signal to begin retrieving the
data from the DRAM core.” ’353 patent, col. 9, ll. 22–24.
In its Federal Circuit Appeal Brief, Rambus alleged that “the PTAB
did not find that the strobe causes or initiates the sampling.” Rambus Fed.
Cir. App. Br. 8. That allegation is not correct. To the contrary, we
specifically found that “the Board shows a causal relationship, contrary to
Rambus’s argument that the Board ‘confuses coincidence with causation.’”
’562 Bd. Dec. 12–13 (emphasis added) (citing Hayes, and noting that
“Rambus also does not point to any normal external signal to the memory
device which occurs after the DS control signal and before sampling in
Hayes.”) Rambus does not clarify if it interprets “initiates” and “causes” as
the same or in the alternative. In any case, the ITC made similar findings
that Hayes’s DS initiates sampling. See ’753 Init. Det. at *69; see also ’562
Bd. Dec. 9, 12–13 (discussing Hayes, referring to incorporated facts found in
’623 Bd. Dec. and finding initiation and causation of sampling by the DS).
Rambus argues that “[m]erely because DS happens to be asserted
when valid data is present and the alleged sampling in Hayes also happens to
occur when valid data is present does not mean that DS causes the alleged
sampling.” Reopen Req. 7. To the contrary, without the DS which occurs
before the sampling, sampling would not occur––we noted earlier in finding
causation that “Rambus does not challenge the Board’s finding that ‘the bus
master asserts DS when data is valid on the bus, the slave then reads the
data.’” See ’562 Bd. Dec. 12–13 (citing Reopen Req. 7; quoting ’623 Bd.
Dec. 20); Hayes, col. 9, ll. 58–65. As such, we find, as discussed further
below, and consistent with all of our previous findings and the Examiner’s,
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that the Hayes DS satisfies the strobe signal limitation. See Right of Appeal
Notice (“RAN”) 8–10 (discussing the strobe limitation), 10 (finding “[t]he
DS signal itself indicates . . . start reading” and “[t]he DS signal . . .
functions to let the memory know[] when to start to read/write data”);
Hayes, col. 9, ll. 37–65; see also Parris Decl. ¶ 11 (discussing a similar
TrncvrRW signal and explaining why indicating valid data to a slave
indicates when to sample the data), ¶ 16 (in Hayes, “the assertion of DS
indicates . . . valid write data”).
Rambus essentially contends that probing for an error condition
subsequent to the DS breaks a chain of causation, because Hayes does not
state “what initiates sampling after the error check is completed.” P.O. Reb.
Br. 15 (citing Hayes, col. 9, ll. 60–64). This contention fails to acknowledge
that Rambus states that “Rambus does not dispute that, as a general matter,
the claims do not exclude other control signals. Thus, the strobe signal is
not necessarily the sole control signal.” Id. (emphasis added). Rambus
notes that, in fact, no sampling occurs until the synchronous clock signal.
See id. at n.7. Rambus also specifically states that “Rambus does not
contend that sampling must occur immediately after receipt of the strobe
signal.” Id. at 15.
In other words, the claims do not preclude waiting for an error check
to occur after the strobe (DS)––assuming for the sake of argument that an
error check rises to the level of another control signal––another control
signal that Rambus agrees the claims do not preclude. Moreover, Hayes
does not disclose another control signal after the DS––Hayes for example,
does not disclose waiting for a clear error signal to be sent in order to start or
continue sampling. To the contrary, as noted above, Hayes states “[i]f no
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error occurs, the slave device reads the data.” Hayes, col. 9, ll. 60–61
(emphasis added). As noted above, Hayes’s system sends an abort ERR
signal if an error does occur––this implies it sends no signal if no error
occurs. See id. at col. 9, ll. 58–63; see RAN 8–10 (finding that the error
signal does not preclude the DS from satisfying the rejected claims).
As indicated above, Rambus agrees that claim 1 and the ’353 patent
disclosure do not preclude a delay after the DS (e.g., waiting until several
cycles of an external clock signal) and do not preclude other subsequent
control. See P.O. Reb. Br. 15; see also ’623 Bd. Dec. 22 (Rambus
“corroborates” this understanding and “describes a similar delay between the
data and the strobe.”) (citing P.O. Cr. App. Br. 10; Req. Resp. Br. 12).
Nevertheless, in its Federal Circuit Brief, Rambus quoted Rambus-Rea as
finding that the strobe “causes the DRAM to execute the operation
immediately (with a minimal inherent delay).” Fed. Cir. App Br. 12
(quoting Rambus-Rea, 527 F. App’x at 904) (emphasis by Rambus).
Despite emphasizing (by underlining), this immediate or “minimal inherent”
delay, Rambus did not actually argue for that requirement in its Federal
Circuit brief or otherwise, failed to quantify the delay, failed to urge an
immediate response to the strobe, and failed to dispute the Board’s finding
that nothing about the strobe requires an immediate response, or precludes
delays or other control signals. (Rambus-Rea‘s characterization of the strobe
signal constitutes dicta––the strobe signal was not claimed and was not at
issue––rather, the “non-strobe” embodiment was at issue.)5

5 Similar to our findings above, in order to facilitate a comparison to, and a
discussion about, the non-strobe embodiment involved in Rambus-Rea, we

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In response to the ’623 Decision, Mr. Murphy also avers that other
signals in Hayes enable the data transceivers 57 and that the RAM control
logic 62 receives the DS signals but the “‘memory devices’ represented by
the 256Kbit DRAM chips 64” do not receive the DS signal. See Murphy 3rd
Supp. Decl. ¶¶ 9–10. This testimony is immaterial. The ’623 Decision does
not rely on a single DRAM chip in the slave memory board as the recited
memory device. Rather, as indicated in the annotated Figure 2 supra, the
Board relies on the whole memory/slave board in Hayes which includes the
RAM control logic 62 and which therefore receives the DS as claim 1
requires.
Mr. Murphy also explains that “RAM control logic 62 is not
connected to any other device that receives data on DAL [31:0]” and also
opines that the error signal which might occur after the DS in Hayes shows
that DS does not satisfy the strobe signal recited in the claims. See Murphy
3rd Supp. Decl. ¶¶ 9–10. Rambus makes similar arguments, relying on Mr.
Murphy. See Reopen Req. 6–10. (However, Rambus did not repeat these
arguments in its Federal Circuit Brief.)
As Mr. Murphy points out, the transceivers become enabled during
the data transfer process, but this simply agrees with the Board’s finding that
the external data lines DAL[31 :0] and DATA <31 :0> lines on the memory

stated in our related decision that the disclosed “strobe signal causes the
transfer to occur several clock cycles after the strobe signal.” Rambus, Inc.
v. NVIDIA Corp., No. 2011-005255, 2011 WL 3883267, at *2 (BPAI
September 1, 2011) (citing the ‘109 patent, col. 9, ll. 41–51 (discussing
latency), Fig. 12 (noting that operations 0 and 3 show clock cycle lags
between the strobe and data).)

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board become connected directly together through the enabled transceivers
57 on the memory board in Figure 7. See ’623 Bd. Dec. 24 n.6 (citing Parris
Declaration). As NVIDIA’s expert Parris testifies, “[t]owards the end of a
write cycle, when data is being transmitted to the slave device, the DATA
TRANSCEIVER 57 connects DAL[31 :0] directly to DATA <31 :0>.”
Parris Decl. ¶ 15. Murphy’s new testimony and Parris’s testimony coalesce
on that point.
Rambus’s assertion that the “RAM control logic 62, which receives
the DS signal, is not connected to the data and address [control] lines
DAL[31:0] or even to the device [transceiver 57] that is connected to
DAL[31:0]” (see Reopen Req. 9), is not material given the finding that the
data lines external to and on the bus are connected via the transceiver prior
to a data transfer. The enabled transceiver 57 directly connects the DRAM
chips to the external DAL[31:0], and therefore, the DS signal does
“necessarily indicate whether valid data is on the separate data lines
DATA<31:00>,” contrary to Rambus’s argument, see id., because the same
data is on both connected lines––according to the un-rebutted findings based
on Parris’s testimony, Murphy’s testimony, and Hayes, and as outlined in in
the ’623 Decision as mentioned supra.
In other words, the DRAM chips sample the same data from DAL[31
:0] and data lines<31:00> through the enabled transceivers 57. The assertion
of DS at the RAM control logic 62 input 62 which controls the DRAM chips
initiates sampling by the DRAM chips of the data lines DAL[31 :0] and
connected data lines<31:00>. Rambus’s arguments and evidence do not
rebut or even address with particularity the Board’s summary finding: “In
sum, the bus master asserts DS when data is valid on the bus, the slave then
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reads the data (absent an abnormal abort . . .), and then the bus master
deasserts DS when data is about to be removed from the bus. (H2.)” ’623
Bd. Dec. 20 (emphasis added, citing “H2”––i.e., facts found from Hayes).
Rambus also does not rebut the underlying related finding that the slave
memory device 15 responds to DS as the one-way DS (DATA STROBE)
signal, in Figure 2 shows.
Rambus also states that the claimed memory device excludes an
external bus controller. See Reopen Req. 10–11. But as Rambus also notes,
the disclosed memory device is a slave device and has “some internal
‘control logic.’” Id. at 11 (citing Figs. 6, 20 of the ’353 patent). Similarly,
in Hayes, the memory controller 12 and other masters 10, 11 are external to
the slave memory device 15, but the slave memory board includes some
RAM control logic on the board. See Hayes, Figs. 1, 7. In a related Rambus
appeal, the Federal Circuit held that contrary to Rambus’s similar
arguments, the term “memory device” is not limited to a single chip and
includes a memory board and some control logic.6
Rambus also states that a “strobe signal” in the ‘353 patent means
“‘data transfer start information.’” See Reopen Req. 8 (quoting ’353 patent
at col. 8, ll. 60–63). As noted above, that disclosure is merely “[a]ccording
to one embodiment,” ’353 patent, col. 8, ll. 60–63, but even if the claims
require it, the Hayes DS includes “start information” by indicating valid data
right before the memory device reads the data. Moreover, the passage in the

6 See In re Rambus Inc., 694 F.3d 42 (Fed. Cir. 2012) (holding that the
claim term “memory device” in a related Rambus patent includes a memory
board and is not limited to a single chip contrary to Rambus’s similar
arguments otherwise).
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’353 patent relied upon by Rambus specifically describes “indicat[ing] when
the DRAM is to begin sending data” id. at col. 8, ll. 62–63 (emphasis
added), but it does not refer to when the DRAM begins sampling (receiving)
data. Rambus fails to explain how this limited disclosure of “start
information” associated with the strobe signal and data transfers shows that
the Board’s interpretation of the Hayes DS signal, which starts and
constitutes a “but-for” cause of the sampling process, is inconsistent with the
’353 Patent Specification, as the ITC similarly found.
According to the ’353 patent, as discussed above, in one embodiment
the DRAM begins to send data in what amounts to two different phases over
several clock cycles after the strobe signal: the DRAM first accesses a
column in the DRAM, and then it sends the accessed data from the column
onto an external bus. See ’353 patent, col. 21, ll. 13–21. In another
embodiment, “[t]he DRAM does not wait for the strobe signal to begin
retrieving the data from the DRAM core.” Id. at col. 9, ll. 22–24. Such
unclear time distinctions for sending data by a memory device, and the lack
of specific examples in disclosure describing sampling in the context of
receiving data by a memory device as called for in the claims, do not define
any clear distinction over Hayes, which samples data in response to the DS
signal as set forth above.
Rambus’s arguments that Hayes does not anticipate claims 5, 14, and
23 based on the recited “terminate signal” in those claims lack a citation to
new evidence and also fail to show that the ’623 Decision overlooks or
misapprehends a material consideration. See ’623 Bd. Dec. 23–26; Reopen
Req. 13–14.
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Based on the foregoing discussion, the ’623 Decision does require a
modification of the anticipation rejection of claims 1, 5, 7, 11, 14, 19, and 23
based on Hayes.
Hayes and Bennett – Claims 2, 6, 10, 17, 25, and 26
Rambus does not direct attention to a specific claim. Claim 2, taken
to be representative, depends from claim 1 and further requires the “data [to
be] sampled synchronously with respect to an external clock.” On remand
by the Board, “[t]he [E]xaminer does not find the patent owner’s evidence
sufficient to overcome the Board’s decision.” Ex. Det. 5. The Examiner’s
findings and rationale are adopted and incorporated by reference and
supported by the record.
As explained in the ’623 Decision and under In re Rambus (supra
note 6), the Hayes memory device satisfies the claim 1 memory device. See
’623 Bd. Dec. 28–29. The combination of Bennett and Hayes renders
obvious claim 2 even if it requires a single chip memory device as discussed
further below. Bennett teaches a memory device receiving data
synchronously with an external clock from a master, and Hayes teaches
sending signals from a bus master to a slave memory device as depicted
supra, in Figure 2.
Rambus contests the Board’s and the Examiner’s finding that Bennett
discloses a synchronous single chip memory device and that the combination
with Hayes would have been obvious. See Reopen Req. 14–21. The
contentions are addressed below after a summary of Bennett’s teachings.
Bennett’s Teachings
B1. Bennett’s “paramount object” is to provide communication
between “very large scale integrated (VLSI) circuit elements” col. 12,
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ll. 14–18 —i.e., “VLSIC chips” col. 9, ll. 35–40. Bennett discloses
combining Versatile Bus Interfaces (VBI) and VLSIC “upon the same chip
substrate as the VLSI User Device” col. 12, ll. 29–32 (emphasis added), with
such a user device including “interfaces intended to be built with a CPU,
IOC, Memory, or similar User device for signal or data exchange” (col. 35,
ll. 59–62 (emphasis added)). See also Bennett, col. 14, ll. 19–24 (describing
“interface to the user devices (usually upon the same chip substrate)”.
Bennett’s Figure 1 represents a single chip User Device, which
includes memory, as noted supra: “Each Versatile Bus Interface Logics, for
example Versatile Bus Interface Logics 102a, interfaces a User module, for
example VLSI Circuit User Device 106a which is pictorially represented in
shadow line within FIG. 1 as existing on the same VLSIC chip substrate as
Versatile Bus Interface Logics 102a.” Id. at col. 36, ll. 19–24 (emphasis
added).
Bennett’s chips have up to 120 pins as a practical limit. Id. at col. 8,
ll. 60–63; col. 9, ll. 60–61. Bennett also discloses different memory types as
“Fast Memory” or “Large Memory” with the memory having address widths
of 16, 24, or 32, and one fast memory embodiment having 37 pins. Id. at
col. 92, ll. 15–56; Fig. 32. One large memory has at least 16 pins to access
232 addresses by employing two 16-bit address words over successive clock
cycles. Id. at col. 95, ll. 59–60; Fig. 36.
B2. Figure 38 shows “memories device” 3802c and 3802d connected
to a “Versatile Bus.” Id. at col. 97, ll. 8–10. In the next paragraph, Bennett
refers to “VSLI chips hav[ing] access to all Versatile Bus lines and,
therefore, the Versatile Bus protocols.” Id. at col. 97, ll. 20–22.
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Bennett elsewhere refers to “memory devices” including, but not
limited to, a ROM: “Not all memory devices can perform all operations; for
example, read only memory (ROM) cannot execute the write operations.”
Id. at col. 90, l. 66–col. 91, l. 2. Bennett then refers to “[s]ample memory
operations . . . defined in the following paragraphs” (col. 91, ll. 4–5), and
thereafter describes “relatively small fast memories, and . . . larger and
relatively slower memories” (col. 92, ll. 13–14).
Bennett also refers to “VLSIC chip devices” (col. 90, ll. 38–41), and
in the next section, Section “4.1, Sample Memory Operations,” states that
“[m]any, if not most, applications of VLSIC technology are likely to include
memory devices.” Id. at col. 90, ll. 42–44. Bennett generally discusses
these chip devices as employing the interconnection protocol standards
outlined generally in Section 3 and more specifically discusses memory
devices in Section 4, including embodiments or configurations involved in
Figures 31–36. See id. at col. 90, ll. 36–41. For example, as discussed in
Section 4 of Bennett, Figures 32 and 33 represent fast memory read or write
operations, with Figures 32 and 33 respectively signifying “DATA”
transmission on 16 and 8 pins. Other pins are used for arbitration and slave
ID. See id. at col. 93, l.12–col. 94, l. 56.
Bennett also refers to the Section 3 figures as representing chips:
“Section 3 provided for the electrical connection of many chips on one bus .
. . . Each chip recognizes the existence of the transactions . . . .” Id. at col.
90, ll. 27–30.
B3. In addition to chips, Bennett also discusses memory cards in
Section 2, “Description of the Prior Art” (see id. at col. 5, l. 52 et seq.), and
states that “the functionality of VLSIC chips is often similar to that of cards
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today” but that “VLSIC technology promises much higher performance than
that of cards,” even though cards hold more memory and chips have higher
development costs. Id. at col. 9, ll. 43–56. In the next passage, Bennett
discusses creating larger chips to accommodate a greater numbers of pins.
Id. at col. 9, l. 66–col. 10, l. 29.
B4. Bennett describes a “third physical objective”––the VBI
(versatile bus interface) “should occupy a reasonable VLSI circuit substrate
area” using fast and efficient CMOS technology as the preferred
embodiment. Id. at col. 13, ll. 18–23. Typically, only about 20 VLSIC
devices will be interconnected. As a “first logical object,” the VBI logics
“should offer a fixed format, simply controlled, powerfully featured
interface to the user devices (usually upon the same chip substrate)” yet with
certain options for use. Id. at col. 14, ll. 20–30.
Bennett contemplates simple devices with “as few as three pins”
(Bennett, col. 12, l. 61), or “pass[ing] but a single bit of data from a single
master device to a single slave device . . . [or more bits and devices]. The
versatility is from the trivial to the profound.” Id. at col. 15, ll. 26, 42–50.
Figure 32, a “sample fast memory,” has “an address field arbitrarily sized at
four bits.” Id. at col. 93, ll. 12, 23. Generally, large memories are slower
than, and have more address pins, than fast memories. Id. at col. 94, ll. 26–
33. Bennett mentions that for large memories, “[a]ddress width may be
configured to 16, 24 or 32 bits to match the requirements.” Id. at col. 94, ll.
35–36. In another section, Bennett describes a fast memory which may have
16 bit words, and if so, “at a 40 nanosecond pace may either have to be very
wide or very fast or both.” Id. at col. 89, ll. 30–32. “The technology is
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projected to drive signals from chip to chip in 20 to 40 nanoseconds, with
internal gate delays of 1 to 2 nanoseconds.” Id. at col. 9, ll. 57–60.
B5. Bennett discloses synchronous clocked communication between
bused VLSIC chips over 16 data lines at 25 MHz, and notes that
synchronous communication is more efficient than asynchronous
communication. Id. at col. 13, ll. 3–17; col. 66, l. 9–col 67, l. 18; col. 101,
ll. 50–54 (“all communication . . . is synchronously referenced”); col. 101, ll.
51–54. Bennett also states that the clock signals “are normally
synchronous.” Id. at col. 274, l. 62.
B6. As noted supra, Bennett contemplates simple systems having “a
single slave memory.” Id. at col. 57, l. 57. Bennett explains that “the
number of [device] locations strongly affects complexity.” Id. at col. 8, ll.
30–31. Bennett distinguishes between slaves and masters: slaves “only
respond to information on the interconnect,” masters “control the
interconnect”; thus, slaves are subordinate to masters. Id. at col. 8, ll. 30–41.
Analysis
Rambus’s arguments do not focus on any particular claim. Claim 2 is
selected to be representative. The ’623 Decision reasons, based in part on
findings by the Examiner and evidentiary showings by Requester, including
testimony by Mr. Parris, that incorporating interface logic, such as strobe DS
logic and synchronous control logic, into a single DRAM chip or memory
device, to sample data synchronously, based on teachings in Hayes and
Bennett, would have been obvious. See ’623 Bd. Dec. 28–29.
As NVIDIA persuasively explains, Hayes describes time-
multiplexed clock data transfers between a master and slave
during different clock cycles [see Hayes col. 19, ll. 45–46], and
Bennett teaches benefits to providing a synchronized interface
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in a memory device using an external clock. (See Req. App. Br.
6-9; H6.)
Id. at 29; see also id. at 10 (citing, inter alia, facts found in Hayes
designated and listed as “H6”).
Rambus’s new evidence does not rebut these findings or rationale.
Bennett, like Hayes, teaches transmitting time multiplexed signals to slave
memory devices, and Bennett teaches synchronous slave memory devices
ranging from the trivial to the complex. See Bennett, col. 93, l. 64–col. 94, l.
5; supra B4, B5 (synchronous operation in Bennett), B6; RAN 41–43; Parris
Decl. ¶¶ 17–22 (discussing fast operation in Bennett and adding logic chip
on-chip to increase speed, contrary to Mr. Murphy’s testimony); ’623 Bd.
Dec. 28–29 (citing same and similar evidence).
Rambus asserts that Bennett does not teach a single chip memory
device. Claim 2 does not require a single chip, it requires synchronous
operation. Assuming arguendo that claim 2 requires a single chip, or a
single chip alters the obviousness analysis related to synchronous operation,
Rambus also asserts that Bennett only teaches “that the VBI can be placed
on the same VLSIC chip under certain circumstances, [but] it teaches away
from doing so when the chip is relatively simple, like a memory device.”
See Reopen Req. 15. Contrary to this argument, Bennett contemplates
simple memory devices, for example, the “pass[ing of] but a single bit of
data from a single master device to a single slave device . . . . The versatility
is from the trivial to the profound.” Supra B4 (emphases added). In any
event, even Bennett’s slave memory card, like Hayes’s slave memory board,
satisfies the broadly recited memory device in the claims as noted supra.
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Rambus also asserts that Bennett teaches away from memory devices
with an integrated interface (a VBI), see Reopen Req. 20, but Mr. Murphy’s
testimony does not support Rambus. “The same circuitry supports
everything from 37-path [i.e., pin] embodiments to 3-path [pin]
embodiments, the only difference being that portions of the interface may be
disabled.” Murphy 3rd Supp. Decl. ¶ 18. This testimony suggests that if
circuitry on a memory device can be “disabled,” skilled artisans would have
known that some of it could be excluded from a simple or trivial 3-pin
memory device to save the cost of putting it on a simple device and then
disabling it. Claim 2 also does not preclude complex circuitry whether
disabled or not.
In Hynix II, Judge Whyte in made extensive factual findings and
“concludes that the Manufacturers have carried their burden of producing
evidence that Bennett discloses a memory device, and that Rambus failed to
rebut this showing.” Hynix II, 628 F.Supp.2d at 1131.7 Judge Whyte found
that the Bennett inventors “were aware of memory cards and referred to
them as such when they chose” and “disparaged the . . . ‘many cards [that]
can be placed on the bus.’” Id. (quoting Bennett at col. 37, ll. 26–28). Judge
Whyte also found that the Bennett inventors turned away from such memory
cards and toward “VLSIC devices, including memory devices” which the
court referred to as “such memory chips.” Hynix II, 628 F.Supp.2d at 1131.

7 Rambus, Inc. v. Hynix Semiconductor, Inc. 628 F.Supp.2d 1114, 1132–38
(N.D. Cal. 2008) (Judge R. H. Whyte ruling on summary judgment and
anticipation by Bennett of similar claims 27 and 43 in the US 6,314,051
patent which was also involved in the Board’s BPAI 2012-000169 original
and rehearing decisions).
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As indicated in the description of Bennett supra, Bennett refers to
“VLSIC chip devices” and states that “[m]any, if not most, applications of
VLSIC technology are likely to include memory devices.” Bennett, col. 90,
ll. 42–44; supra B2. Bennett’s “paramount object” is to provide flexible,
versatile, and configurable communication between “very large scale
integrated (VLSI) circuit elements” col. 12, ll. 14–25–– i.e., “VLSIC chips”
col. 9, ll. 35–40. See supra B1. The term VLSIC (very large scale
integrated circuit) in Bennett, and conventionally, signifies a single chip
device. See Rambus Inc. v. Infineon Tech. AG, 318 F.3d 1081, 1085–86,
1091 (Fed. Cir. 2003) (defining Rambus’s claim term, “integrated circuit
device,” as a “circuit constructed on a single monolithic substrate,
commonly called a ‘chip’”) (relying on trade dictionaries, citations omitted).
Bennett states that a VLSIC chip “cannot currently provide for as much
memory as can be placed on a card,” Bennett, col. 9, ll. 47–48, but “VLSIC
technology promises much higher performance than that of cards,” id. at col.
9, ll. 45–47, and “[t]he [VLSIC] technology is projected to drive signals
from chip to chip in 20 to 40 nanoseconds,” col. 9, ll. 58–60. See B4.
Rambus also argues that “extrinsic evidence also demonstrates that
‘memory device’ is a single chip that does not include a memory controller.”
Reopen Req. 11. This argument is not clear. In any event, as the Federal
Circuit held, the term memory device does not preclude some control
functionality in a memory device.8

8 See note 6 supra; In re Rambus Inc., 694 F.3d at 42 (holding that the claim
term “memory device” in a related Rambus patent can signify but is not
limited to a single memory chip and includes a memory board).
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Rambus also alleges that asynchronous RAS and CAS signals
“perform completely different functions” in asynchronous systems like that
of Hayes as compared to synchronous systems like those from Bennett, and
thus, this shows the unobviousness of modifying Hayes’s memory slave
devices into either a synchronous memory board device or a synchronous
memory single chip device. See Reopen Req. 17 (discussing NVIDIA’s
expert Parris’s Declaration). But in Hayes, the CAS and RAS signals
transfer within Hayes’s slave memory device––a memory board device. See
Hayes, Fig. 7 (showing internal portions of slave/memory board with RAS
and CAS lines connecting RAM control logic 62 to the DRAM chips).
Moreover, to the processor chip in the Hayes external bus master, the
memory board looks just like a single slave RAM chip. “An important
feature of the present invention is that to the local bus 17 master [i.e.,
processer 10 or chip 16, Hayes, col. 14, ll. 3-4)], there is no distinction
between on-board RAM and off-board RAM.” Hayes, col. 14, ll. 29–31.
Therefore, contrary to Rambus’s arguments, the RAS and CAS signals on
the memory board slave device do not overly complicate rendering such a
device into a single slave chip device or render unobvious sending a
synchronous signal to either one––especially since, as noted supra, Hayes’s
system sends time multiplexed signals from a master to a slave (which look
the same to the bus master whether the slave is a board or a chip) as
similarly occurs in Bennett.
Further, since Bennett similarly discloses memory boards and
memory chips according to the record and Rambus, Bennett suggests the
obviousness of synchronizing either one of these memory devices, including
a memory device such as Hayes’s memory board––i.e., regardless of the
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functionality of the RAS or CAS signals thereon. See supra B5; see also Ex.
Det. 7–8 (addressing Rambus’s arguments about RAS and CAS signals and
relying on the Parris testimony showing the “shift in the art from
asynchronous to synchronous systems” to increase speed).
In sum, Rambus’s contentions that rely on Mr. Murphy’s new
testimony add little or nothing material to Mr. Murphy’s prior testimony as
the Examiner finds. See Ex. Det. 5–6, 9 (finding that Murphy’s Third
Supplemental Declaration to be cumulative to prior testimony). Rambus’s
further reliance on other evidence fails to show unobviousness.
Rambus asserts that evidence of record shows distinctions between
asynchronous and synchronous devices and logic. Reopen Req. 16–18
(citing, e.g., Exs. A, E). Rambus’s assertions do not overcome the Board’s
and Examiner’s finding that skilled artisans were modifying asynchronous
systems and transforming them into synchronous systems while keeping
some of, or modifying, the logic in asynchronous systems, as the Mr. Parris
testifies and as the Examiner finds in reliance thereon. See Reopen Req. 18–
19; Ex. Det. 6–14.
Rambus cites to a textbook authored by “Dr. Jacob,” which describes
a history of DRAMs. Reopen Req. 17.9 According to this textbook, in the
mid-1970’s, “[o]ther early DRAMs were sometimes clocked . . . by a

9 Brian Davis et al., The New Dram Interfaces: SDRAM, RDRAM and
Variants, Proc. The third International Symposium on High Performance
Computing (2000) (Reopen Req., Ex. A). Rambus refers to this source as
“Dr. Jacob”––one of the authors and “nVidia’s ITC expert.” See Reopen.
Req. 17.
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periodic clock signal” (i.e., apparently, synchronously) and then the
technology moved toward asynchronous devices. See Ex. A, Ch. 12, 461,
§ 12.2.2. The textbook explains that asynchronous DRAM devices were
“more of a hindrance than an asset” and that “computer manufacturers
pushed to place a synchronous interface on the DRAM device.” See id. at
466. (It is not clear when this “push” occurred or who the manufactures
were.)
In any event, according to the textbook, a central difference between
RAS and CAS in synchronous and asynchronous DRAMs is that the latter
involves controlling “latches that are internal to the DRAM device” while
the former involves
signals [which] deliver . . . commands . . . acted upon by the
control logic of the SDRAM device at the falling edge of the
clock signal. In this manner, the operation of the state machine
in the DRAM device moved from the memory controller into
the DRAM device, enabling features such as programmability
and multi-bank operation.
Id.
Rambus’s citations to Dr. Jacob’s textbook do rebut the findings of
record or reveal an insurmountable or appreciable technical challenge in
accommodating any functional difference between synchronous and
asynchronous RAS and CAS signals. Rambus’s assertions regarding alleged
problems with synchronous logic circuits and “truth table[s]” (discussed in a
textbook by Betty Prince) also does not help to rebut the record findings or
show appreciable technical challenges to skilled artisans attempting to
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modify internal DRAM circuits to handle desired logic. See Reopen Req. 18
(citing Ex. E).10
Mr. Parris contradicts Rambus’s assertions and describes modifying,
in a “straight forward” manner, i.e., “well within the ability of one of
ordinary skill in the art,” such “previously asynchronous DRAM [‘RAS’ and
‘CAS’] signals” to be “on-chip,” generally describes “incorporat[ing]
asynchronous functionality on previous asynchronous memory systems into
synchronous memory systems,” and further notes that the “logic circuitry
[including latches, registers, and counters] was typically [modified to be] . . .
synchronous with the [external] clock”. Parris Decl. ¶ 9.
Rambus also argues that the Board does not identify a reason for
modifying Hayes’s traditional asynchronous CAS and RAS signals to
include Bennett’s clocking scheme. But as the Examiner recognizes, the
Board did identify reasons, including the industry push toward integration
and synchronization to create smaller and faster memory devices. See Ex.
Det. 7 (citing ’623 Bd. Dec. 29 which cites Parris Decl. ¶¶ 18–20).
Rambus’s cited evidence fail to rebut Mr. Parris who also testifies as
follows: “To the contrary [of Murphy’s testimony and Rambus’s
arguments], adding logic on-chip with the memory device increases
processing speed for multiple reasons, including reducing propagation
delays and allowing the memory device to by physically closer to other
devices driving the bus.” Parris Decl. ¶ 19.

10 Betty Prince, HIGH PERFORMANCE MEMORIES, NEW ARCHITECTURE
DRAMS AND SRAMS EVOLUTION AND FUNCTION (1996) (Reopen Req., Ex.
E).

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In addition, Hayes also discloses at least partial synchronization––
bank select strobes on the memory board device are “synchronized with the
processor timing by ARR RASIN (Array Row Address Strobe In)” during a
memory board transaction. Hayes, col. 23, ll. 38–41. The evidence shows
that synchronizing signals with an external clock would not have required an
unobvious or insurmountable modification of the traditional RAS, CAS, or
DS signals in Hayes, contrary to Rambus’s arguments which lack sufficient
factual supporting evidence. See Reopen Req. 16–18.
Other alleged structural features in SDRAMs (synchronous DRAMs)
supposedly showing unobviousness according to Rambus, such as
programmable registers and multiple internal banks, fail to support Rambus,
because these added SDRAM features are neither needed to modify Hayes
nor to satisfy the claims. See Reopen Req. 19–20. Rambus does not assert
that it invented these SDRAM features, that synchronous memory devices
require them, or that the claims require them, so it is not clear how the
features show unobviousness. Bennett discloses synchronous memory chips
that either have or do not have these specific SDRAM features––showing
the obviousness of using generic synchronous memory chips encompassed
by the claims.
Based on the foregoing discussion, Rambus’s new evidence and
arguments do not show unobviousness or error in the ‘623 Decision as the
Examiner finds and reasons.
Hayes with Bennett and Inagaki – Claims 3, 4, 12, 13, 21, and 22
Rambus does not direct attention to a specific claim. Claim 3 is
selected as representative. Claim 3 depends from claim 2 and additionally
requires sampling first and second data portions on odd and even phases of
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the external clock signal. The record supports the Examiner’s findings and
rationale which are hereby adopted and incorporated by reference. See Ex.
Det. 10–14. Rambus’s new evidence does not undermine the ’623 Decision.
See ’623 Bd. Dec. 29–31. As the Decision explains and as noted supra,
Hayes uses a clock to drive time multiplexed signals to a memory device.
Bennett also uses a clock to drive time multiplexed signals and to
synchronize memory devices. Inagaki merely teaches using both clock
phases, i.e., the rising and falling edges of an external clock, to double the
clock speed in memory devices. See id.
As the Examiner recognizes, contrary to Rambus’s characterization,
Bennett’s system is not being modified by the proposed combination, but
rather, Bennett is employed to suggest using an external clock to
synchronize a Hayes memory device (whether as a memory board device or
modified to be a single chip memory device). See ’623 Bd. Dec. 28–29
(citing IP Req. 19–24, Req. Reb. Br. 4 n. 7). As such, as the Examiner
recognizes, Rambus’s argument and Mr. Murphy’s testimony that Bennett’s
system would have been rendered inoperable or that Bennett’s principle of
operation would have been destroyed via the proposed prior art combination
are not germane to the proposed rejection. See Ex. Det. 12–13; Reopen Req.
24–25.11

11 Even if the argument somehow is germane to obviousness here, Bennett, a
U.S. patent, is presumed to be enabling. The Board addressed Rambus’s
arguments about Bennett’s alleged inoperability in a related decision,
finding to the contrary. See Rambus Inc. v. Micron Tech. Inc., PTAB 2012-
001976, slip op. at 19–30 (PTAB Dec. 10, 2012) (Rambus’s appeal
dismissed by Board Order (Aug. 14, 2015) after remand by Federal Circuit).
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Contrary to related arguments by Rambus that Bennett’s system
would not have employed a faster clock, see Reopen Req. 24–25, Bennett’s
system is not being modified as noted, and in any event, contemplates faster
speeds including doubled speeds: “The technology is projected to drive
signals from chip to chip in 20 to 40 nanoseconds, with internal gate delays
of 1 to 2 nanoseconds.” B4; Ex. Det. 12 (also quoting this Bennett
sentence). This fact and related facts, including a universal desire for speed
and industry drives toward integration, all suggest the obviousness of using a
both edges of a clock to gain clock speed in Hayes as modified by Bennett,
according to Inagaki’s teachings. As the ’623 Decision also explains, in
addition to increasing speed using both the rising and falling clock edges,
Inagaki also suggests using a relatively slower clock’s dual edges as a mere
substitute for a faster clock which uses only the rising edges. Using dual
edges can also allow for a decreased number of signal lines since twice the
data can be pushed over half the lines using both clock edges as Inagaki
teaches. See ’623 Bd. Dec. 29–31.
Based on the foregoing discussion, Rambus’s new evidence does not
show unobviousness and does not upset the ’623 Decision as the Examiner
finds and reasons.
Hayes with Inagaki – Claims 12 and 13
Claim 12, like claim 3 discussed supra, requires sampling data on
both clock edges. Rambus does not direct attention to either claim 12 or 13.
Claim 12 is selected as representative.
The Examiner’s findings and rationale are supported and adopted and
incorporated herein by reference. See Ex. Det. 10. Rambus maintains that
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the prior art combination does not render obvious a synchronous memory
device using a data strobe and a periodic clock. See Reopen Req. 26.
Hayes’s DS satisfies the data strobe signal as discussed supra, and
Hayes and Inagaki each disclose a clock, contrary to Rambus’s arguments.
As the Decision explains, and which Rambus does not address, claims 12
and 13 depend from claim 1, and unlike claim 2, do not recite synchronous
operation. Inagaki’s clock samples data during odd and even phases of a
clock, as claim 12 requires: “‘[S]ince one bit is output on each half-cycle,
the operating speed is twice that of the conventional speed.’” See ’623 Bd.
Dec. 30 (quoting Inagaki at 4). Rambus also does not provide new evidence
to upset the ’623 Decision. See Reopen Req. 26.
Assuming, arguendo, that the claims implicitly require synchronous
operation, Inagaki characterizes the clock operation as synchronous: For
example, “[c]lock φ1 is generated synchronously with the external clock φ.”
Inagaki 5 (discussing Figure10). As the Examiner also notes, the Parris
declaration and other references of record show that such synchronous
operation was known and the industry was moving towards it. See Ex. Det.
14–15. Using dual edges of a clock (synchronously or not) would have been
obvious to increase speed as Inagaki teaches.12

12 Inagaki is a subject of Rambus, Inc. v. Rea, 731 F.3d 1248 (Fed. Cir.
2013) (affirming the Board’s holding that Inagaki anticipates some claims in
U.S. Patent No. 6,260,097 drawn to double data rate or dual edge
synchronous clock operation, but remanding for obviousness on other claims
primarily to address evidence of nonobviousness and due process concerns).
Rambus did not appeal the Board’s subsequent decision on remand finding
obviousness regarding combining Inagaki’s double data rate clocking
scheme with prior art memory devices. See Rambus, Inc. v. Lee, Appeal

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Based on the foregoing discussion, Rambus’s arguments, lacking in
new evidence, do not show unobviousness and do not upset the ’623
Decision as the Examiner finds and reasons.
Hayes with Ohshima – Claims 2–10, 12–14, 16, 17, and 20–26
Rambus does not direct its arguments to any single claim. Claim 2
requires synchronous operation and is selected to be representative of the
above-listed group based on Rambus’s arguments. The Decision largely
relies on and refers to NVIDIA’s inter partes request and Brief for the
rejection of these claims. See ’623 Bd. Dec. 32–33. As an example,
NVIDIA relies on Ohshima to teach that intervening circuits obviously
could have been added on-chip in a simple chip interface. NVIDIA also
relies on Ohshima’s synchronous chip teachings and other features to
increase speed in a DRAM. See, e.g., NVIDIA App. Br. Exhibit 14 (claim
chart at 1.2, 2.0); App. Br. 13; Inter Partes Reexam Request 30–35 (“I.P.
Request”). NVIDIA’s inter partes request reasons that Ohshima teaches that
combining logic on chip reduces the number of chips and complexity. See
I.P. Request 30. Rambus does not rebut these relied upon findings or
rationale.
Responding to Rambus’s Reopen Request, the Examiner finds that
Rambus’s “new evidence. . . . repeats the same comments” previously
offered by Mr. Murphy. Ex. Det. 16. The Examiner reasons that
incorporating the Hayes RAM control DS circuitry into a single chip
synchronous memory device according to Ohshima’s teachings would have

2012-000171 (PTAB Sept. 2, 2014) (appeal dismissed by Board Order (Nov.
19, 2014)).
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been obvious and that the claims do not require incorporating all the RAM
logic into a single chip as Rambus’s arguments imply. See Ex. Det. 15–16
(addressing Reopen Req. 27–28 and Murphy 3rd Supp. Decl. at ¶¶ 28–29 and
citing the “RAN (Feb. 26, 2010)”). Murphy’s Third Supplemental
Declaration addresses the obviousness of incorporating all the Hayes DS
RAM logic into a single chip and thus fails to address the Board’s Decision.
See ’623 Bd. Dec. 32–33. The thrust of Rambus’s position reduces skilled
artisans to automatons who would blindly incorporate all of Hayes’s RAM
control logic that controls multiple chips into a single chip. To the contrary,
as a matter of routine skill, skilled artisans would have eliminated any
unnecessary circuitry to create a single, simple DRAM chip having the
necessary interface control to control that DRAM to transfer data as
Ohshima shows.
Such a combination involving integration would have been obvious
for creating faster and smaller components as Parris declares as noted supra.
See also DyStar Textilfarben GmbH & Co. Dutschland KG v. C.H. Patrick
Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) (“[A]n implicit motivation to
combine exists . . . when the ‘improvement’ is technology-independent and
the combination of references results in a product or process that is more
desirable, for example because it is stronger, cheaper, cleaner, faster, lighter,
smaller, more durable, or more efficient.”) Contrary to Rambus’s arguments
(Reopen Req. 23), DyStar’s motivation is not limited to “technology-
independent” improvements. Rambus’s arguments illogically would mean
that the memory device industry or any single industry would not desire
speed increases.
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Ohshima teaches using “newly developed high speed DRAMs . . .
and their innovative circuit techniques” to solve memory bottleneck
problems. See Ohshima 1303 (“Summary”). Ohshima also discusses using
the “Rambus DRAM” for the same or similar purpose of increasing speed.
See id. Rambus does not assert that Ohshima is not prior art in this
reexamination proceeding. In several other proceedings before the Board,
Rambus has asserted that their claimed devices have been highly successful
to solve speed and memory bottleneck problems. Using these synchronous
DRAMs and similar DRAMs to modify a single DRAM of Hayes while
incorporating the Hayes DS logic to tell the DRAM that data is valid would
have been obvious: As noted, Parris bolsters the obviousness of such
integration and testifies that asynchronous systems were migrating to
synchronous memory devices and designers were incorporating memory
logic into such integrated devices to increase speed.
Based on the foregoing discussion, Rambus’s new evidence and
arguments do not disturb the ’623 Decision as the Examiner determined.
Kushiyama with Hayes and Lu – Claims 1–14, 16, 17, and 19–26
Rambus does not direct its arguments to any single claim. Claim 1 is
selected to be representative of the above-listed claims based on Rambus’s
arguments. As Rambus notes, the Examiner finds that Lu teaches
incorporating logic circuits into memory, and finds that it would have been
obvious to incorporate some of the Hayes RAM control logic, such as the
DS signal circuitry, into a DRAM of Kushiyama. See Reopen Req. 28–29.
As the ’623 Decision explains,
NVIDIA reasons that integrating the DS logic of Hayes into the
Kushiyama chips would have been obvious where Lu teaches
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incorporating on-chip logic to make DRAMs more intelligent
and to optimize performance at the system level. (Req. App.
Br. 14-15.) Mr. Par[r]is corroborates this point and notes that
chip designers were employing asynchronous circuits on-chip,
including some strobe signals, like RAS and CAS, and that
moving such circuits on-chip increase speed.
’623 Bd. Dec. 33 (citing Parris Decl. ¶¶ 9, 19).
In response to the Board’s finding, Rambus maintains that the Board
“provides no indication of how the DS signal from Hayes’s asynchronous
system would have been incorporated into Kushiyama’s synchronous system
or why such incorporation would have been beneficial.” Reopen Req. 28–
29. The record, discussed further above and below, indicates that skilled
artisans would have been able to make such a change, and the DS signal
serves the stated purpose in Hayes of telling the memory device that data is
valid and thereby ready to be sampled, rendering its use in other memory
devices to signal sampling obvious. See Ex. Det. 17; accord Parris Decl.
¶ 11 (discussing a similar TrncvrRW signal and explaining why indicating
valid data to a slave indicates when to sample); ¶ 24 (discussing
Kushiyama).
The record reflects that the skill level here in memory systems was
advanced at the time of the invention. Hence, while Mr. Murphy testifies
that such integration would be “non-trivial” and “the disadvantage of cost
and establishing a common architecture may outweigh the advantages of
new features,” see Murphy 3rd Supp. Decl. ¶ 31, based on this record, skilled
artisans could or would have seized the known universal and stated
advantages (size, speed, durability, etc.) to overcome cost and any other non-
trivial factors.
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Rambus similarly reasons that artisans would not have incorporated
asynchronous features into synchronous systems and that Lu does not
“unequivocally teach integration of logic onto DRAMs.” Reopen Req. 29
(citing Murphy 3rd Supp. Decl. at ¶¶ 31–32). Lu discusses trade-offs and
implicit in trade-offs is a weighing process by skilled artisans. Lu explicitly
states that “for some systems new functions, better performance, and size
reduction can be achieved by integrating more logic circuits on DRAM
chips.” Lu 98. Lu indicates that “high bandwidth[,] capacity” and “cost,
reliability and packaging” must all be considered. Id. at 99. Higher cost
does not mandate unobviousness. Faster, smaller, and more durable
packages constitute universal motivators under DyStar. Integrating logic on-
chip creates fewer chips and faster chips based on propagation distance and
simplifies external wiring (reliability) and packaging. As Lu states,
ASIC DRAMs, adding logic functions on-chip with the
memory, provide high density and high performance . . . [since]
[d]ata processing executed within one chip eliminates interface
loss in speed and power consumption, which has been existing
inevitably in combination of standard DRAMs with basic
common functions and logic parts.
Id.
Based on the foregoing discussion, Rambus’s new evidence and
arguments do not upset the ‘623 Decision as the Examiner finds.
Farmwald ’755 with either Lu or iRAM
Claims 1–4, 6–9, 11–13, 15, 16, 18–22, and 24–26
Rambus primarily focuses on independent claim 11, selected to be
representative based on the arguments presented, even though independent
claims 1 and 19 are broader than claim 11. Similar to its arguments with
respect to Hayes, Rambus argues that the TrncvrRW signal disclosed in
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Farmwald ’755 does not “cause the memory devices to sample data” as
required by the “strobe signal” recited in the independent claims. Reopen
Req. 31.
One pertinent disclosure in Farmwald ’755 that refutes this argument
follows:
Persons skilled in the art will recognize that a more
sophisticated transceiver can control transmissions to and from
primary bus units. An additional control line, TrncvrRW can be
bused to all devices on the transceiver bus, using that line in
conjunction with the Addr-Valid line to indicate to all devices
on the transceiver bus that the information on the data lines is:
1) a request packet, 2) valid data to a slave, 3) valid data from a
slave, or 4) invalid data (or idle bus). Using this extra control
line obviates the need for the transceivers to keep track of when
data needs to be forwarded from its primary bus to the
transceiver bus—all transceivers send all data from their
primary bus to the transceiver bus whenever the control signal
indicates the condition 2) above.

Farmwald ’755, col. 21, ll. 35–49 (emphasis added); see also ’623 Bd. Dec.
36–37 (quoting and discussing the passage).) Directly below the above-
quoted passage, Farmwald ’755 states that “[e]ach controller seeking to
write to a slave should drive both AddrValid and TrncvrRW high, indicating
valid data for a slave is present on the data lines. Each transceiver device
will then transmit all data from the transceiver bus lines to each primary bus
unit.” Farmwald ’755, col. 21, ll. 56–60.
These passages reveal that the TrncvrRW signal causes or initiates
sampling as claim 11 requires. That signal generally indicates “to all
devices on the transceiver bus” that there is “valid data to a slave.” Id. at
col. 21, ll. 37–43 (emphasis added). In the memory stick embodiment, this
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valid indication causes “[e]ach transceiver device [to] transmit all data from
the [main] transceiver bus lines to” the bus and memory devices on the
memory stick (primary bus unit). Farmwald ’755, col. 20, ll. 62–63; col. 21,
ll. 56–60; Fig. 9.13 As the passage supra reveals, the TrncvrRW “extra
control line obviates the need for the transceivers to keep track of when data
needs to be forwarded.” As described, the TrncvrRW functions as a strobe
at least relative to the memory stick.
Rambus’s central contention is that “NVIDIA . . . mischaracterizes
Farmwald ’755 by claiming ‘all devices on the bus receive the TrncvrRW
signal,” Rambus Resp. Br. 26, and similarly that “there is no reason one
would have modified a memory device to receive a signal that is specific to
a transceiver.” Rambus Resp. Br. 24; see also Reopen Req. 31 (similar
argument); Ex. Det. 19–24 (Examiner responding to argument and finding
and determining otherwise). In essence, Rambus originally maintained that
Farmwald ’755 did not disclose or render obvious sending a TrncvrRW
strobe signal to a single chip memory device, because according to Rambus,
the disclosed system only sends it to a memory stick. See ’623 Bd. Dec. 38–
44. 14

13 The memory stick, also called a primary bus unit, includes a transceiver
device 19 and one or more memory chip devices. See Reopen Req. 30
(annotating Fig. 9 of the ’755 patent and showing the memory stick and
external transceiver bus); ’623 Bd. Dec. 35 (FW6), 40. See also infra note
14.
14 We hesitate to refer to a memory stick as the claimed memory device,
notwithstanding that a memory device is not limited to a single chip. In re
Rambus (see note 6), the Court indicated that a portion of the Board’s
underlying analysis in that case was “incorrect” for “equating the multichip

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Contrary to this argument, as the Examiner found in agreement with
the Board, in addition to disclosing sending TrncvrRW signals to “all
devices on the transceiver bus,” Farmwald ’755, col. 21, ll. 37–38,
Farmwald ’755 specifically states that “persons skilled in the art will
recognize how to implement systems which have . . . memory devices on the
transceiver bus as well as on primary bus units,” id. at col. 21, ll. 4–7; Ex.
Det. 19–20) (emphasis added). Hence, a memory device on that bus

‘memory stick’ with a’ memory device,’” but the court held that “this does
not mean that a memory device must contain only one chip.” Rambus, 694
F.3d at 47 (emphasis added). The court held that a “‘memory device’ is a
broad term which has been used consistently in the ’918 patent and in the
family of patents related to it to encompass a device having one or more
chips.” Id. at 48 (emphasis added). Hence, while the court found that “a
memory device and memory stick are [not equated or not] the same,” see id.
at 47, because a memory device includes multiple chips and includes the
prior art “iAPX Manual’s memory module, which contains several chips and
a controller that provides the logic for those chips to function” (id. at 50), it
appears that the generic term “memory device” also may include the two
disclosed species in the ’918 patent––i.e., the memory stick device and a
memory chip device––even though they are not “the same” species.
Alternatively, perhaps the court carved out an exception from the broad
reach of the term “memory device” so that it somehow includes everything
from a broad prior art memory board to a narrow single chip memory device
except the intermediate memory stick that the ’918 patent discloses. See id.
at 47 (“the specification could not be clearer that the disclosed invention can
be practiced with either a memory device or with a memory stick.”) If so,
the court did not have benefit of the explicit finding by the Board in the ’623
Decision, concession by Rambus here, and further discussion, that the
TrncvrRW signal is bussed to all memory devices on the transceiver bus
(i.e., to memory stick devices and memory chip devices on that bus). (See
’623 Bd. Dec. 39.) The ITC also did not have before it arguments and
evidence regarding these findings.

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receives the TrncvrRW and in general, teachings for a memory stick apply to
a memory chip device and vice versa: Farmwald ’755 also states that “[i]n
general, each teaching of this invention which refers to a memory device can
be practiced using a transceiver device and one more memory devices on an
attached [memory stick].” Id. at col. 21, ll. 7–10.
Rambus fails to address or rebut the finding that the TrncvrRW causes
or initiates sampling with respect to a memory stick or a memory device.
See id. at col. 21, ll. 1–49; supra notes 13, 14. Similar to its arguments
addressed above, Rambus argues that the ‘353 patent disclosure implies a
“‘data transfer start information’” requirement in claim 11, but Rambus does
not explain how that disclosure distinguishes over the ’755 Farmwald
TrncvrRW signal. See Reopen Req. 31 (quoting ’353 patent, col. 8, l. 61).
As noted above in the claim construction and discussion of Hayes, that
disclosure pertains to “sending” data from a memory device, not writing data
to it, as the claims require, and also, only describes “one embodiment.” ’353
patent, col. 8, ll. 59–63. Moreover, the TrncvrRW signal contains “data
transfer start information,” because it indicates valid data to a slave after
which the memory stick or chip device begins to sample the data.
Mr. Parris’s testimony supports the Board and directly contradicts
Rambus: “[T]he TrncvrRW signal does indeed indicate when the memory
device is to begin sampling write data.” Parris Decl. ¶ 11 (explaining, inter
alia, that “[t]he slave should not, and will not, begin sampling write data
until the data is valid.”). Rambus fails to present persuasive evidence
rebutting Parris’s testimony or the evidence in Farmwald ’755 relied upon
by the Board and the Examiner.
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Mr. Murphy testifies, and Rambus argues, that because the
“TrncvrRW signal indicates whether a transceiver should forward data,” the
signal would not be sent to a memory device “since the memory device does
not make the forwarding decisions that are made by a transceiver.” Murphy
3rd Supp. Decl. ¶ 35.15 Rambus similarly argues that “the purpose of the
TrncvrRW signal is to allow the transceiver to decide whether to forward
data from the transceiver bus to the primary bus.” Reopen Req. 31. This
testimony and argument simply address the memory stick embodiment
wherein Farmwald ’755 discloses sending the data to a single chip memory
device on the memory stick after determining that data on a bus is valid. See
Farmwald ’755, col. 21, ll. 6–7, 37–39. It does not dispute the finding or
reasoning that such a forwarding decision amounts to a strobe signal
response––i.e., it causes the transceiver or memory chip interface to forward
(i.e., sample) data.
The arguments and testimony also do not address the alternative
rationale that even if Farmwald ’755 does not disclose with sufficient
specificity the embodiment wherein a DRAM chip makes a forwarding
decision upon receiving the TrncvrRW, it would have been obvious to

15 The ITC appears to have relied on somewhat similar, but more limited,
evidence and arguments presented there, according to a brief summary of its
findings. See ’661 Comm’n. Det. at *46–*48 (finding that the transceiver
uses the TrncvrRW signal to make forwarding decisions, citing agreement
by the USPTO examiner during initial prosecution, noting that the ALJ
focused on anticipation arguments, and concluding that respondents had not
shown obviousness where “no asserted prior art explicitly discloses “‘strobe
signal”DDD/‘FFF‘FFFsignal’DDD’ limitations” of the asserted Barth I
claims.”).
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modify the chip interface to handle the same transceiver forwarding
function, especially where Farmwald ’755 discloses sending the TrncvrRW
signal to the DRAM chip––a memory device on the transceiver bus, and, as
quoted above, discloses that skilled artisans would have applied applicable
teachings regarding the memory device to the memory chip and vice versa.
Farmwald ’755, col. 21, ll. 1–10. In other words, even if the TrncvrRW
signal somehow does not constitute a strobe signal, using it as such a signal
to tell a memory device (like a memory stick or a memory chip) to start
sampling would have been obvious, because the ’755 Farmwald patent
discloses that the TrncvrRW signal indicates to devices on the transceiver
bus that valid data causes transmission of data through the transceiver.
Farmwald ’755, col. 21, ll. 57–60.
Rambus concedes part of the point–– that the TrncvrRW signal “‘can
be bused to all devices on the transceiver bus.’ Nothing in the specification
suggests that the TrncvrRW signal is also sent to devices on the primary
bus.” Reopen Req. 33 n.10 (quoting Farmwald ’755 at col. 21, ll. 37–39).
Rambus’s second quoted sentence sets up a straw man. The primary bus on
the memory stick has nothing to do with the rejection at issue. All devices,
including single chip memory devices and memory stick devices, disclosed
in the ’755 patent as residing on the external transceiver bus, receive the
TrncvrRW signal. As the ’623 Decision explains, and as Rambus depicts
(see Reopen Req. 30), the transceiver bus is the bus external to the memory
stick (and that bus has memory sticks and other memory devices attached to
it). See supra notes 13, 14.
Rambus similarly concedes the point that the TrncvrRW signal goes
to all memory devices in another argument. “Because it [the TrncvrRW
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signal] does not indicate to which memory device data being transmitted is
intended to be written and is provided to all devices on the transceiver bus,
TrncvrRW cannot be considered to indicate to a memory device to initiate
sampling.” Reopen Req. 31 (emphasis added). Rambus appears to be taking
the position that each “memory device” disclosed in its ’755 Farmwald
patent cannot determine from the TrncvrRW signal that it is being addressed
by a controller for a data transfer. The Board does not assert that the
TrncvrRW signal includes address information, and the claims do not
require that. Perhaps Rambus implies that the TrncvrRW signal goes to all
slave memory devices on the transceiver bus as a broadcast signal. See, e.g.,
’353 patent, col. 16, l. 49 et seq. (discussing broadcast data). If so, claims 1,
11, and 19 do not preclude all the memory devices on the ’755 Farmwald
transceiver bus from sampling the data on the bus in response to the
TrncvrRW strobe signal. The claims also do not preclude a single memory
device system in which that memory device would be addressed.
Assuming for the sake of argument that Farmwald ’755 only discloses
that the TrncvrRW goes to a transceiver chip on a memory stick to indicate
valid data to that slave memory stick device and cause it to sample data, as
the Decision and the Examiner explain at length, the prior art combination,
which includes Farmwald ’755 with either of Lu or iRAM, renders obvious
modifying the stick by integrating some of its simple forwarding
functionality into a single chip memory device having a transceiver
interface. An obvious purpose would have been that receiving a TrncvrRW
strobe signal in a smaller and faster device such as a single chip would have
informed the fast chip when to sample data since the TrncvrRW signal tells
all slave memory devices that there is “2) valid data to a slave” (quoted
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supra from ’755 Farmwald). See Ex. Det. 22–24; ’623 Bd. Dec. 38–45. As
an example of further rationale for creating a single chip out of two chips,
aside from the beneficial reduction in chip number, the Board reasons that
Farmwald ’755 specifically teaches that “‘each teaching of this invention
which refers to a memory device can be practiced using a [memory stick –
i.e., a] transceiver device and one or more memory devices.’” ’623 Bd. Dec.
36, 40 (citing FW7 facts and quoting ’755 Farmwald at col. 21, ll. 7–10).
Rambus’s Federal Circuit Appeal Brief argues that “it would be
nonsensical to incorporate a transceiver or hub into one of the peripheral or
slave devices” because that modification would “prevent the transceiver/hub
from performing its sole purpose –– to act as a bridge which enables many
devices to plug into a single port or node.” Rambus Fed. Cir. App. Br. 23–
24. This argument reduces to the argument that Farmwald ’755 does not
disclose a purpose for using a single memory chip (which is not on a
memory stick) and memory sticks (which include at least one memory chip).
In other words, transferring a single forwarding function from a memory
stick transceiver interface to a single chip interface does not mean that the
rejection proposes getting rid of all memory sticks. See ’623 Bd. Dec. 41
(discussing obviousness of sending “the TrncvrRW signal to a single chip”).
It also ignores the abundant evidence on this record that chip designers were
beneficially employing various asynchronous circuits and functions on-chip,
including some strobe signals. See RAN 44–45; Parris Decl. ¶¶ 9, 19; Lu
98; iRAM 1, 3-432 (integrating control logic into single chips), 3-433 (“[a]
sensible alternative is to integrate the memory controller circuits into
memory” to provide “optimized timing”); ’623 Bd. Dec. 33–45 (citing and
relying on similar facts and discussing rationale.
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The Examiner’s responses to Rambus, which rely on the ’623
Decision, persuasively rebut Rambus’s remaining arguments, add additional
supporting facts and rationale, and are adopted and incorporated by
reference as indicated at the outset. See Ex. Det. 18–24. For example, Mr.
Murphy opines that combining a DRAM with a transceiver would make the
DRAM chip bigger and hence slower than a normal DRAM chip, thereby
defeating one rationale for obviousness. See Murphy 3rd Supp. Decl. ¶ 36.
However, that rebuttal compares the wrong devices, two chips, instead of a
chip and a memory stick. A single chip memory integrated with a single
function of a beneficial transceiver interface would be smaller and faster
than the Farmwald ’755 multi-chip memory stick. A memory stick is “quite
simple in function,” ’755 Farmwald col. 21, l. 18, and encompasses as few
as two chips, a memory chip, and a transceiver chip which functions as a
simple interface to the bus for the memory chip, further suggesting
integration thereof. See Farmwald ’755, col. 2, ll. 18–24; Ex. Det. 23–24;
’623 Bd. Dec. 41–45.
Pursuant to the foregoing discussion, Rambus’s evidence and
arguments do not support altering the ‘623 Decision and the Examiner’s
Determination that claims 1–4, 6–9, 11–13, 15, 16, 18–22, and 24–26 based
on Farmwald ’755 and Lu or iRAM would have been obvious.
Claim 26
Regarding rejections previously instituted as new grounds by the
Board, Rambus presents new arguments directed to claim 26 in its Federal
Circuit Appeal Brief. Rambus Fed. Cir. App. Br. 24–27. Rambus relies on
arguments that we do not find presented to the Board in Rambus’s
Respondent Brief (June 28, 2010) or to the Examiner in Rambus’s Reopen
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Request. See Rambus Fed. App. Br. 25–27; Ex. Det. (Examiner addressing
Rambus’s Reopen Request); Rambus Resp. Br. 12–28.
Accordingly, we find and determine that Rambus waived these
arguments.16 See In re Watts, 354 F.3d 1362, 1367 (Fed. Cir. 2004) (“Just as
it is important that the PTO in general be barred from raising new arguments
on appeal to justify or support a decision of the Board, it is important that
the applicant challenging a decision not be permitted to raise arguments on
appeal that were not presented to the Board.”) (footnote omitted); In re
Lovin, 652 F.3d 1349 (Fed. Cir. 2011) (applicant waived arguments at the
Board by not presenting substantive separate patentability arguments for
dependent claims).
Under the contingency that our reviewing court determines that
Rambus did not waive these arguments directed to claim 26, we address
them. Rambus argued in its Federal Circuit Appeal Brief that the “PTAB”
erroneously combines two embodiments from Farmwald ’755 to show the
obviousness of delaying a strobe, such as the TrncvrRW, relative to a write
signal, by at least two clock cycles. See Rambus Fed. Cir. App. Br. 26.

16 To the extent the Board did not discuss each claim explicitly in its ’562
Decision that instituted new grounds of rejection, the Board relied on
Requester’s prior showing of record, including its Request for Inter Partes
Reexamination Request, as establishing a prima facie case that Rambus had
not rebutted (and thereafter did not address in its Request to Reopen or in
Comments that it declined to file in response to the Examiner’s
Determination). See MPEP 2681(I) (37 C.F.R. § 41.77(b) “is not intended
as an instruction to the Board to revisit every patentable claim in every
proceeding,” but rather to act “on either the same grounds or on different
grounds from those applied against the rejected clams.”).
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Requester relied on Farmwald ’755’s disclosure that suggests a delay
of a number of eight clock cycles between strobe signals and read or write
signals in general. See I.P. Request 59 (citing Farmwald ’755, col. 10, l. 33).
As noted above, Farmwald ’755 states that teachings for memory devices
and memory sticks may apply mutually. Farmwald ’755, col. 21, ll. 3–10.
Farmwald ’755 also teaches that a request packet includes a write signal, the
TrncvrRW signal employs an additional control line used by a controller or
master, which inspects a data packet for a valid data determination, and that
delays for access times of one, two, or more clock cycles may be required to
be implemented for transceiver data transfers and possible for other data
transfers. See id. at col. 21, ll. 18–67. Even if somehow these general
teachings of a delay between a strobe (or TrncvrRW) and a write signal do
not apply explicitly to the similar TrncvrRW signal embodiment, a delay
between the strobe or TrncvrRW and write signals would have been obvious
to allow access to the data bus by other devices and data and to signify when
to sample/forward data across a device interface. See I.P. Request 59, Ex. P
(discussing claim 26); Farmwald ’755, 7, ll. 4–21. Also, Farmwald ’755
discloses using two signals, 1) a read or write signal in a request packet, and
2) a strobe or TrncvrRW to signify valid data on a bus, thereby suggesting a
delay of some number of clock cycles between the two. See Farmwald ’755,
21:37–43, 60–65.
Similar remarks apply to the Hayes and Kushiyama based rejections.
Rambus relies on arguments that we do find presented to the Board in
Rambus’s Respondent Brief (June 28, 2010) or to the Examiner in Rambus’s
Reopen Request. See Rambus Fed. App. Br. 25–27; Ex. Det. (Examiner
addressing Rambus’s arguments in Reopen Request); Rambus Resp. Br. 12–
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28. Consequently, we find that Rambus also waived these arguments.
Under the contingency that our reviewing court determines otherwise, we
address them. The arguments isolate selected portions of Requester’s
showings adopted by the Board, and fail to address the totality of that
showing. For example, Requester relies on the combination of Hayes’s
implicit delay between a write and the DS, and supplements that with
Bennett’s teaching of providing latency of up to ten cycles, whereas Rambus
focuses on Figure 26 of Bennett. See I.P. Request 24, Ex. L; Rambus Fed.
App. Br. 25.
Similarly, Rambus does not address adequately Requester’s reliance
on the combination of Kushiyama and Hayes as set forth with respect to
claims 1, 19, and 26. See I.P. Request, 36–38, 41 (describing a delay
between a request packet and sending data, a read or write operation within a
request packet in Kushiyama, and a DS after a write in Hayes); I.P. Request,
Ex. N. Requester alternatively relies on a reading for claim 26 (which
depends from claim 19) that combines the delay between the Hayes write
command and DS, wherein the delay in Hayes includes placing data on the
lines, and Kushiyama explicitly shows that placing data on bus lines would
span several clock cycles (according to Kushiyama’s data packets at Figure
3 (six clock cycles)). See I.P. Request 41–42; Kushiyama 492, col. 1.
Similarly, Rambus does not address Figure 15a of Ohshima (which
is similar to Kushiyama, Fig. 3A) that Requester relies upon, and relying on
Figures 3b–d, counts a delay between the end of a request packet and write
signal as one clock cycle––incorrectly assuming that the write command
must occur at the end of a request packet. See Rambus Fed. App. Br. 26–27.
Rambus’s arguments also allege without explanation why relying on delays
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in page hits are improper. See id. As Requester contends, Figure 15a of
Ohshima shows an 8 clock cycle delay between a request packet and data,
and Requester relies partly upon that to suggest the claimed delays. See,
e.g., I.P. Request, 27, 34–35, 41–43, Ex. M (discussing claims 1, 19, 26); see
also Ex. P (claim element 1.1); Ohshima, Fig. 15a.)
CONCLUSION
Rambus v. Rea, 527 F. App’x 902 (Fed. Cir. 2013) (“Rambus-Rea”)
supports the prior Decision, BPAI 2013-000562, which this Decision
replaces.
The incorporated Decision, BPAI 2011-010623, does not require a
modification with respect to the underlying holding affirming claims 1, 5, 7,
11, 14, 19, and 23 as anticipated based on Hayes.
The prior Decision, BPAI 2013-000562, does not require a
modification with respect to the underlying holding that claims 1–26 would
have been obvious under the previously entered new grounds of rejection
(listed supra).
Requests for extensions of time, if available in this inter partes
reexamination proceeding, are governed by 37 C.F.R. § 1.956. See
37 C.F.R. §§ 41.77 and 41.79.
This decision contains new grounds of rejection pursuant to 37 C.F.R.
§ 41.77(b) which provides that “[a]ny decision which includes a new ground
of rejection pursuant to this paragraph shall not be considered final for
judicial review.” Correspondingly, no portion of the decision is final for
purposes of judicial review. For further guidance on new grounds of
rejection see 37 C.F.R. § 41.77(b)-(g). The decision may become final after
it has returned to the Board. 37 C.F.R. § 41.77(f).
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37 C.F.R. § 41.77(b) also provides that the Patent Owner, WITHIN
ONE MONTH FROM THE DATE OF THE DECISION, must exercise one
of the following two options with respect to the new grounds of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. The owner may file a response requesting
reopening of prosecution before the examiner. Such a response must be
either an amendment of the claims so rejected or new evidence relating to
the claims so rejected, or both.
(2) Request rehearing. The owner may request that the proceeding be
reheard under § 41.79 by the Board upon the same record.
Any request to reopen prosecution before the Examiner under
37 C.F.R. § 41.77(b)(1) shall be limited in scope to the “claims so rejected.”
Accordingly, a request to reopen prosecution is limited to issues raised by
the new ground(s) of rejection entered by the Board. A request to reopen
prosecution that includes issues other than those raised by the new ground(s)
is unlikely to be granted. Furthermore, should the Patent Owner seek to
substitute claims, there is a presumption that only one substitute claim would
be needed to replace a cancelled claim.
Compliance with the page limits pursuant to 37 C.F.R. § 1.943(b), for
all patent owner responses, is required.
The Examiner, after the Board’s entry of a patent owner response and
requester comments, will issue a determination under 37 C.F.R. § 41.77(d)
as to whether the Board’s rejection is maintained or has been overcome.
The proceeding will then be returned to the Board together with any
comments and reply submitted by the owner and/or requester under
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37 C.F.R. § 41.77(e) for reconsideration and issuance of a new decision by
the Board as provided by 37 C.F.R. § 41.77(f).

DECISION AFFIRMED

PATENT OWNER:

FINNEGAN, HENDERSON, FARABOW,
GARRETT & DUNNER LLP
901 New York Avenue, NW
Washington, DC 20001-4413

THIRD PARTY REQUESTOR:

HAYNES AND BOONE, LLP IP SECTION
2323 Victory Avenue
Dallas, TX 75219