Ex Parte 6584037 et al

Board of Patent Appeals and Interferences

Aug 16, 2012

95001108 (B.P.A.I. Aug. 16, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,154 03/03/2009 6,584,037 8963.002.RXUS00 7630
22852 7590 08/16/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
08/16/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,108 11/07/2008 6584037 38512.15 6309
22852 7590 08/16/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
08/16/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Inter Partes
RAMBUS, INC.
Patent Owner

v.

SAMSUNG ELECTRONICS, CO., LTD. and
MICRON TECHNOLOGY INC.
Requestors
____________

Appeal 2012-000142
Reexamination Control Nos. 95/001,108 & 95/001,154
United States Patent 6,584,037 B2
Technology Center 3900
____________

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON (RAMBUS’S) REQUEST FOR REHEARING
Appeal 2012-000142
Reexamination Control 95/001,108 & 95/001,154
Patent 6,584,037 B2

Rambus seeks relief in its Patent Owner’s Request for Rehearing, see
37 C.F.R. § 41.79, from the Decision of the Board of Patent Appeals and
Interferences reversing the Examiner’s decision not to maintain the
obviousness rejection of claim 34.1 In Response, Micron filed Third Party
Requestor’s Comments to Patent Owner’s Request for Rehearing Opposing
Rambus’s Request (“Micron’s Opposing Comments”). Requester Samsung
has not filed a brief in this proceeding.
In a rehearing request, appellants have the burden to “state with
particularity the points believed to have been misapprehended or overlooked
by the Board.” 37 C.F.R. § 41.52 (a)(1). Rambus has not made the requisite
showing. Micron’s Opposing Comments persuasively address Rambus’s
contentions not specifically addressed below.
1.) Rejection - Bennett in view of Bowater or Wicklund
Rambus maintains that the Board overlooked its contention that the
combination does not suggest a synchronous DRAM memory device
because the Board “failed to address the noticeable absence of any reference
to DRAM[s]” in Bennett. (Reh’g Req. 1.) Rambus’s argument improperly
focuses on what Bennett does not disclose instead of the combined
teachings. The Decision finds that “Bennett discloses synchronous memory
chips” and that employing a notoriously well-known DRAM memory chip
in place of Bennett’s generic memory chip would have been obvious. (See
Bd. Dec. 8 (citing relevant factual findings and incorporating by reference,
Micron Reply Br. 9-16 (discussing, inter alia, Bennett’s synchronous
memory chips and obviousness).)

1 Decided January 27, 2012 after an oral hearing on January 18, 2012 which
was transcribed (“BPAI Tr.”) and made of record.
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Rambus’s counsel acknowledged that Bennett discloses a
synchronous system – but Rambus “do[es] [not] believe that Bennett
discloses a synchronous memory chip.” (See BPAI Tr. 24.)2 Rambus’s
contentions fail to show that the Board overlooked evidence or arguments
which would upset the conclusion that it would have been obvious to
employ a “DRAM . . . the most popular form of memory chip[] at the time
of the invention,” as a substitute for Bennett’s generic synchronous memory
chip. (See Bd. Dec. 8.)
Rambus also contradicts itself by stating that Bennett’s disclosure of a
“memories device” only signifies a memory card and does not also include a
single chip. (See Reh’g Req. n. 3.) Rambus has repeatedly made the
opposite argument, arguing that skilled artisans would have understood that
the term “memory device” is limited to a single chip. See e.g., In re Rambus
Inc., 2011-1247, slip. op. at 10, 12 (Fed. Cir. Aug. 18, 2012) (Holding that a
memory device is not limited to a single chip even though “Rambus urges us

2 The Board previously decided that Bennett discloses a synchronous
memory device chip. See e.g., BPAI 2011-009664 at 14-18 (2012)
(concluding obviousness with respect to a similar issue involving claims
directed to a read operation based, inter alia, on Bennett, Wicklund or
Bowater); BPAI 2012-001638 at 3--22 (2012) (relying, in part, on a District
Court December 15, 2008 Order Granting in Part and Denying in Part
Rambus’s Motion to Strike; Denying Motion for Summary Judgment No. 1
of Invalidity; and Striking Motion for Summary Judgment No. 2 of
Invalidity, Hynix Semiconductor Inc. v. Rambus Inc., No. 00-2905, Rambus
Inc. v. Hynix Semiconductor Inc., No. 05-334, Rambus Inc. v. Samsung
Electronics Co., Ltd., No 05-2298 RMW, and Rambus Inc. V. Micron
Technology, Inc., No. 06-244 (N.D. Cal.) (stayed, Judge R. Whyte) (attached
as Ex. O-3 to the Rambus’s respondent brief in the 2012-001638
reexamination).

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to conclude that a skilled artisan would interpret ‘memory device’ as a single
chip component.”). Rambus’s current argument also contradicts its expert,
Mr. Murphy, in this proceeding. (See Murphy Decl. I at ¶ 55 (attached to
Rambus Resp. Br.) (testifying that the “term ‘memory device’ would have
been readily understood . . . to be . . . a ‘chip’).) And as Micron points out,
Bennett describes how its “VLSIC device,” i.e., the memory device,
“replaces” the “two or three printed circuit (PC) cards” described as prior art
in Bennett and which Rambus contends to be the large memory device
disclosed in Bennett. (See Micron Reb. Br. 10 (emphasis by Micron,
quoting Bennett at col. 6, ll. 35-64).)
Rambus also points to a disclosure in Bennett of “up to 232 addresses
of 32 bit words” as showing that a disclosed large memory is a circuit board.
(Rambus Reh’g Req. 2; Bennett, col. 95, ll. 58-59.) But Bennett describes
replacing prior art circuit boards with chips, as just discussed, and of course,
the phrase “up to” in Bennett signifies a range which includes fewer
addresses and bits. (Accord Micron Reb. Br. 11.) Bennett also discloses
“16, 24, or 32 bits” (col. 94, col. 35-36) as the Decision finds (Bd. Dec. 6,
B1) - contrary to Rambus’s related allegation “that it is not clear how the
Board arrived at 16, 24, or 32 pins” (Reh’g Req. 3, n.4). In other words,
Bennett is forward looking and contemplates a range of address space and
associated pin numbers in future chips, including memory chips, with
specific reference to fewer pin numbers – assuming for the sake of argument
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the claim scope has anything to do with a set number of pins or address
space.3
Rambus also argues that an operation code requires one or more bits
and explains that CAS and RAS signals are not operation codes or bits. (See
Rambus Reh’g Req. 4.) But this has little, if anything, to do with the
Decision which relies on Bennett’s “read-modify-write” signal signifying
multiple functions in a single operation code, as modified to include the
prior art known precharge signal as disclosed in the ‘037 patent admissions,
Wicklund, or Bowater, thereby constituting, based on the combined
teachings, the claimed operation code. (See Bd. Dec. 6 (B4); Bd. Dec. 9
(citing the Examiner’s RAN at 41 and the prior art – i.e., D, F1, F2, W2-
W4).)
Rambus’s contention that Bennett’s operation codes and the clock
would be provided to the Versatile Bus Interface “VBI” (see Reh’g Req. 4-5,
n.4) does not show that the Board overlooked a material fact or point. The
argument constitutes another version of Rambus’s single chip argument.
The Board implicitly finds, relying on Micron’s discussion of Bennett and
the Board’s independent review of Bennett, that Bennett’s “VLSIC memory
chips[] each hav[e] an integrated Versatile Bus Interface” (see Micron Reb.
Br. 11), - i.e., a VBI integrated on a single chip memory device. Similarly,
the Examiner specifically finds “that memory devices that receive[] a clock

3 As other examples, Bennett contemplates “as few as three pins.” (Bennett,
col. 12, l. 61), or “pass[ing] but a single bit of data from a single master
device to a single slave device . . . [or more bits and devices]. The
versatility is from the trivial to the profound.” (Col. 15, ll. 26, 42-50.)
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were well known in the art such as with [the] Bennett reference.” (See RAN
69.)
Rambus maintains that the Board overlooked evidence about
“sampling the data in response to the operation code, after a delay time
transpires.” (Reh’g Req. 5.) Rambus’s Responsive Brief, with respect to
the delay value element, also reduces to Rambus’s single chip argument in
another form as Micron points out. (See Micron Reb. Br. 13.) That is,
Rambus argues that “Bennett’s large memory . . . as described above would
be understood as a combination of the VBI and multiple memory devices.”
(Rambus Resp. Br. 14.) The Decision addresses this single chip argument as
noted above.
Rambus similarly maintains that the Board’s statement that “‘on
remand, the Examiner has the discretion to sort out any remaining
contentions and make specific findings” shows that the Board overlooked
“Rambus’s [other] evidence regarding other features of claim 34.” (Rambus
Reh’g Req. 5 (quoting Bd. Dec. at 12).) But Rambus does not explain what
“other features” were in contention, or how the Board overlooked “any
remaining contentions” at issue on appeal. As Rambus acknowledges, the
Board “refer[red] to Rambus’s and Micron’s arguments regarding delay,
external clock signal, and other elements of claim 34.” (Rambus Reh’g
Req. 5.) In other words, the Board determined that Rambus’s arguments,
weighed against Micron’s responses and the Examiner’s findings, failed to
show Examiner error as to these other claim elements on this record.
(Compare Bd. Dec. 4 (adopting the Examiner’s RAN findings supporting
the Decision) with Bd. Dec. 12 (finding the Examiner erred with respect to
“the conclusion that it not have been obvious to employ a well-known
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precharge single in a write op code signal, when such a precharge normally
followed a write in the prior art systems.”).) And the Decision states in
summary that “Micron’s responses are persuasive where the Examiner does
not disagree with Micron’s contentions as to any remaining claim terms and
focuses on reasons discussed supra.” (Bd. Dec. 12.)
Rambus maintains that the Board overlooked evidence concerning the
obviousness rejections based on Bennett and either of Wicklund or Bowater.
(See Rambus Reh’g Req. 7-12.) As Micron generally contends, Rambus’s
“contentions … are essentially expressing disagreement with the merits of
the Board’s decision and are not directed to a matter overlooked or
misapprehended by the Board in its decision.” (Micron’s Opposing
Comments 5.)
Rambus argues that the Board erroneously equated a refresh with a
precharge operation. (Rambus Reh’g Req. 9.) But the Decision points out
that “the Examiner . . . Micron . . . and Rambus describe Wicklund’s system
as precharging – in other words, refreshing and precharging are interpreted
to be the same or similar function for purposes of this appeal.” (Bd. Dec. 7,
note 6 (emphasis added).) In other words, the Decision only implies that the
two prior art operations are related, for purposes of the appeal, based on
statements and findings by the Examiner, Rambus, and Micron. The Board
recognized a difference, and at oral hearing, specifically pointed out that
“Wicklund doesn’t mention precharge. I think he just mentions refresh.”
(BPAI Tr. 7.) The Decision also presents a “DRAM” definition showing
that refreshing in DRAMs involves using transistor switches to top off
“capacitors” that store the dynamic charge -further supporting the fact that
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the Board was well aware that precharging any transistors (or other circuitry)
and refreshing the storage capacitors are not exactly the same. (Bd. Dec. 4.)
Evidence submitted by Rambus in a related proceeding corroborates
the understanding that precharging of the sense circuits typically occurs with
refreshing of the underlying memory “capacitors” (or reading from or
writing to such capacitors).4 Wicklund similarly describes refreshing the
capacitor charges in a DRAM (col. 1, ll. 39-46) and describes how
“performing a read or write operation on a row will refresh all the cells on
that row . . . so … that the read or write cycle will take the place of a refresh
cycle”- which may be controlled by a CPU in one embodiment (col. 3, ll. 48-
54).
And Rambus states that “[a]ccording to Wicklund . . . . [a]fter the data
is input or output, the row is then closed and the internal circuitry is
precharged.” (Rambus Resp. Br. 15.) The Decision similarly notes that
Wicklund’s row closing causes “precharging of the DRAM circuits.” (Bd.
Dec. 9 n.9.) In other words, refresh, like reading or writing, typically
requires or includes precharging the circuits in DRAMs. Prior art systems
typically precharged after a read or write operations as part of closing the
row being accessed so that quick subsequent access could occur. (See Bd.

4 See e.g., Hynix Semiconductor et al. v. Rambus Inc., No. C-00-20905,
March 29, 2006 Transcript of Proceedings, David Taylor testifying at 1615
(N.D. Cal.) (stayed, Judge R. Whyte) (attached as Ex. E-14 to Rambus’s
respondent brief in a related BPAI 2012-001639 reexamination proceeding).
Mr. Taylor testifies that the basic operation of DRAMs requires refreshing
and/or reading the data because the “dynamic” information bleeds off, and
that the circuitry must be precharged in order to refresh or read –
precharging enables the circuits in the DRAM for subsequent reads.

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Dec. 5, F1, F2 (discussing “conventional” operations as admitted in the ‘037
patent); BPAI Tr. 17-19 (Rambus’s counsel describing typical operations);
Rambus Resp. Br. 15 (discussed supra).)
Most importantly, the thrust of the Decision has little to do with
equating precharge and refresh. The thrust of the Decision is that it was
widely known, and admitted by Rambus in the ‘037 patent and elsewhere,
that “prior art systems typically precharge DRAMs in the non-page (normal)
mode after a read or a write operation.” (Bd. Dec. 9.) Rambus’s counsel
corroborated these conventional operations at the oral hearing, stating that
“typically in normal mode, you do precharge after the normal mode access.”
(BPAI Tr. 19.) Rambus similarly explains that “[i]n conventional DRAMs,
precharging would occur by deasserting the /RAS signal, which could occur
after one or many read and/or write operations.” (Rambus Reh’g Req. 6.)
“In other words, [as the Decision finds], Micron's contention that prior art
systems typically precharge DRAMs in the non-page (normal) mode after a
read or write operation (Micron App. Br. 7-9) is not in dispute.” (Bd.
Dec. 9.)
Given this lack of a dispute about the precharge signal typically
following a normal write signal, Rambus’s central argument is that since
prior art controller’s issued two separate signals, that a precharge signal was
not “automatic” (Rambus Reh’g Req. 6) and this somehow shows the
unobviousness of “‘coupling’” the two separate signals together into a single
operation code (see id. at 7.) But the Decision simply describes the two
separate signals as coupled in the prior art, because one follows the other in
the normal read or write mode. As such, putting the two related signals into
the same operation code would have been obvious, since Bennett puts other
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Patent 6,584,037 B2

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related instructions in the same operation code such as the read-modify-write
operation code. (See Bd. Dec. 6 (B4 describing Bennett’s “read-modify-
write code signifying multiple functions”), Bd. Dec. 9-10 (relying on
Bennett’s operation code- i.e., the read-modify-write and citing RAN 41
(similar).)
Rambus now contends that there were more than two known modes;
i.e., more than just page and normal modes. (Reh’g Req. 8.) But Rambus
relies on its own patent to allege four known modes, including, in addition to
the known normal modes and page modes, a “precharge after page mode
access” or “save after normal access.” (See id.) It is not clear from the ‘037
patent whether or not these latter two modes were known modes or modes
disclosed by the inventors of the ‘037 patent. The relied upon passage reads
as follows: “Typical settings are ‘precharge after normal access’ and ‘save
after page mode access’ but ‘precharge after page mode access’ or save after
normal access’ are allowed.” (“037 patent, col. 10, ll. 50-53.)
A fair reading, in light of the prior art of record, implies that “the
[t]ypical” page and normal modes were known, while the other two modes
were not. But even if there were four known modes, this does not show the
unobviousness of putting a normal mode write signal and a precharge signal
into a single operation code. Further, contrary to Rambus’s arguments, the
Decision specifically describes and does not overlook the precharge after
page mode access mode disclosed in the ‘037 patent. (See Bd. Dec. 5, F2.)
Rambus’s allegation of a requirement for a controller’s knowledge of
“page boundaries” in large systems (Rambus Reh’g Req. 12) also fails to
show that the Board overlooked a material point related to the obviousness
of sending the precharge in an instruction for a write. A controller, CPU
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(see, e.g., Wicklund discussed supra), requestor, or other user in Bennett (or
as modified by Wicklund, Bowater, or other known prior art) which requests
a normal mode write would “know” what it requested and send the
precharge request either sometime thereafter as occurred in the prior art, or,
as proposed in the rejection, send it with the op code where Bennett suggests
multiple instructions in a single code. Further, claim 34 does not require a
page mode so that arguments directed thereto are outside the claim scope. A
requestor issuing a simple instruction involving a normal read and precharge
would not have been required to be aware of such page boundaries which
might occur in a page mode but do not occur in the normal mode. Assuming
for the sake of argument that claim 34 requires a page mode, Rambus’s
arguments fail to demonstrate that a requestor issuing a request to a memory
device would not know the page boundaries. (See Micron Reb. Br. 16.)
Rambus’s allegation of a requirement for “additional logic” “by a
controller that directly controls the asynchronous DRAMs” on a large
memory board similarly constitutes another form of the single chip argument
and fails to address the combination. (See Rambus Reh’g Req. 13.) As
discussed supra, Bennett discloses a synchronous memory chip and DRAMs
were notoriously well-known memory chips. The argument does not explain
why ordinarily skilled artisans would have been unable to modify Bennett’s
remote requestor with such additional logic as required to include another
(precharge) instruction in Bennett’s op code for requesting a write to
Bennett’s synchronous memory chip - as modified to be a DRAM as the
combination suggests. (See Micron’s Reb. Br. 13 (stating “the real dispute
here is whether it would have been obvious . . . to utilize Bennett’s
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synchronous operation codes to provide precharge information to Bennett’s
memory devices); accord id. at 14-15.)
Rambus’s remaining arguments fail to show that the Board
overlooked a material point warranting a modification of the Decision.
2.) Priority
Rambus argues that the Board did not address Rambus’s argument
that the Board does not have authority to address written description issues.
(Rambus Reh’g Req. 16.) The argument is not relevant because the Board
decided a priority issue. (Bd. Dec. 14-18.) Also, the Board decided the
priority issue in Rambus’s favor as Rambus acknowledges. (See id.;
Rambus Reh’g Req. 16.)
3.) Standing
Rambus maintains that the Board overlooked Rambus’s argument that
Micron lacks standing to argue rejections proposed by Samsung. (Rambus
Reh’g Req. 15-16.) To the contrary, the Board relied upon a petition
decision which concluded that Micron does have standing in a related
reexamination involving the same parties. (See Bd. Dec. 15 n.12.)5 Also,
even if Micron lacks standing, the Board has discretion to enter new grounds
of rejection regardless of the source for the rejection. See 37 C.F.R.

5 Moreover, Micron’s Opposing Comments at 6 also direct attention to the
similar Decision on Petitions (July 6, 2011) in this proceeding, which ruled
against Rambus on this issue, reasoning that “the Office has addressed this
issue on several occasions in the past few months and decided that Micron,
in its briefs, was permitted to address the rejections and proposed rejections
that were before the Office at the time of the Right of Appeal Notice.” (Pet.
Dec. 5-6.)
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§ 41.77(b) (denominating a reversal of a refusal to reject as a new ground of
rejection even if based on the “Board[’s] . . . knowledge of any grounds not
raised in the appeal”).
4.) Secondary Considerations.
Rambus contends that the Board overlooked Rambus’s proffered
evidence and arguments related to secondary considerations of
nonobviousness. (Rambus Reh’g Req. 13.) Rambus acknowledges that part
of the Board’s rationale for deciding that the evidence failed to establish a
nexus was that any success “‘likely flow[ s] from a variety of several
unclaimed features touted here or in other Rambus proceedings or patents,
such as an internal DLL (delay locked loop), eight data lines, small DRAM
sizes, multiplexed buses, packetized control, identification control
mechanisms, doubly terminated clocks, and time access schemes.’” (Id.
(quoting Bd. Dec. 14).)
Rambus responds by stating that “Rambus did not rely on or address
the unclaimed features . . . and the evidence it presented was directed to
claimed features.” (Rambus Reh’g Req. 14.) Rambus’s response fails to
show that the Board overlooked or misapprehended the nexus requirement.
Rambus does not dispute that the unclaimed features likely contributed to
any touted success. And Rambus’s evidence does not demonstrate that any
success was due solely to the claimed features, or to claimed features that
were not already known in the prior art. For example, Rambus’s contention
that Samsung took five-year licenses for synchronous DRAM devices fails
to address what other unclaimed features the licenses involve. (See Rambus
Reh’g Req. 15.) Singe chip synchronous memory devices were well known
as Bennett discloses, as were DRAMs as Wicklund and other prior art
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discloses. And Rambus does not direct attention to any material specifics or
to a copy of the licenses.
While Rambus argues that claim 34 solves a memory bottleneck
problem (see id. at 14-15), claim 34 reads on a variety of memory devices,
including slow devices, since claim 34 does not recite speed (as a functional
limitation) and does not recite other circuitry necessary to obtain such
speed.6 Therefore, as the Decision reasons, the record suggests that the
proffered evidence is not commensurate with the claim scope, and also,
lacks a nexus, as due to a whole host of other unclaimed features, including
a multiplexed bus, helping to gain the touted “‘high speed’” from a single
DRAM. (See Bd. Dec. 14 (quoting Rambus Inc. v. Infineon Technologies
AG, 318 F.3d 1081, 1095 (Fed. Cir. 2003)).)
5.) Summary
Rambus fails to show that the Board overlooked arguments or
evidence warranting affirmance of the Examiner’s decision not to reject
claim 34 based on Bennett, and either of Wicklund or Bowater.

REHEARING DECISION
DENIED
ak

6 Rambus alleges pervasive skepticism “‘over a 500 megabit per second
DRAM data rate’” and “about many of the specific features of the
technology” as showing “‘strong evidence of nonobviousness.’” (See
Rambus Resp. Br. 19 (citations omitted).) Assuming for the sake of
argument that uncorroborated statements by the inventors show skepticism
by others (but see Micron Reb. Br. 16 (arguing a lack of objective
evidence)), as noted, claim 34 does not require the 500 MHz speed touted or
“many of the specific features” – whatever they may be.
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Third Party Requesters:

Haynes and Boone, LLP
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Novak, Druce & Quigg, LLP
(NDQ Reexamination Group)
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