Ex Parte 6452863 et al

Patent Trial and Appeal Board

Oct 23, 2012

95001124 (P.T.A.B. Oct. 23, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,124 11/24/2008 6452863 896.002.863 5356
22852 7590 10/23/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
10/23/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/000,250 06/28/2007 6452863 38512.8 4189
22852 7590 10/23/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
10/23/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD

RAMBUS INC.
Patent Owner, Appellant and Respondent

v.

MICRON TECHNOLOGY, INC.
Requester, Respondent and Cross-Appellant

and

SAMSUNG ELECTRONICS, INC.
Requester
____________

Appeal 2012-001917
Inter Partes Reexamination Control No. 95/000,250 & 95/001,124
United States Patent 6,452,863 B2
Technology Center 3900
____________

Before HOWARD B. BLANKENSHIP, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2012-001917
Reexamination Control Nos. 95/000,250 & 95/001,124
Patent 6,425,863 B2

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This merged proceeding arose out of separate requests by Micron
(95/001,124) and Samsung Electronics Ltd. (95/000,250) for inter partes
reexaminations of U.S. patent 6,425,863 B2 to Farmwald et al., Method of
Operating A Memory Device Having A Variable Data Input Length (issued
Sept. 27, 2002 and claiming priority to Apr. 18, 1990 per application no.
07/510,898) assigned to Rambus.
Samsung has not filed a Brief in this proceeding. Appellant, Patent
Owner Rambus, appeals in its (Replacement) Appeal Brief (Mar. 4, 2011)
from the Examiner’s decision to reject claims 1-28. (Rambus App. Br. ix.)
Cross-Appellant, Requestor Micron, appeals from the Examiner’s decision
in the (Second) Right of Appeal Notice (Sept. 3, 2010)(“RAN”) not to reject
claims 14-16 on certain grounds proposed by Micron and on other grounds
proposed by requester Samsung. (Micron Cr. App. Br. 3-4.) The Examiner’s
Answer relies on the RAN, incorporating it by reference.
We have jurisdiction under 35 U.S.C §§ 6, 134, and 315.
We AFFIRM the Examiner’s decision to reject claims 1-28 and do not
reach Micron’s Cross Appeal Brief in furtherance of the special dispatch
mandate for inter partes reexamination proceedings under 35 U.S.C § 303.
Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching
obviousness after finding anticipation).

STATEMENT OF THE CASE
Rambus and Micron refer to several related judicial and other
proceedings including inter partes and ex parte reexaminations,
International Trade Commission proceedings, and Federal District Court and
Circuit Court proceedings in their briefs and inter partes requests. An oral
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hearing of this appeal transpired on July 11, 2012 and was subsequently
transcribed.
Appellant Rambus appeals the Examiner’s decision to reject the
claims as follows:
Claims 1-20 and 24-28 under 35 U.S.C. 102(b) as anticipated based
on the iAPX Manual1 or Budde2 (see RAN 51, 73);
Claim 21 under 35 U.S.C. 103(a) as obvious based on the iAPX
Manual or Budde, and Lofgren3 (see RAN 94, 111);
Claim 22 under 35 U.S.C. 103(a) as obvious based on the iAPX
Manual or Budde, and Inagaki4 (see RAN 98, 113); and
Claim 23 under 35 U.S.C. 103(a) as obvious based on the iAPX
Manual or Budde, Inagaki, and Lofgren (see RAN 103, 114).

Claims 1, 14, 21, 22, and 23 of the ‘863 patent follow:
1. A method of controlling a memory device by a memory controller,
wherein the memory device includes a plurality of memory cells, the method
of controlling the memory device comprises:
providing first block size information to the memory device, wherein
the memory device is capable of processing the first block size information,
wherein the first block size information is provided by the memory
controller and is representative of a first amount of data to be input
by the memory device; and

1 iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982)
2 Budde et al., U.S. 4,480,307 (Oct. 30, 1984).
3 Lofgren et al., G.B. 2,197,553 A (May 18, 1988).
4 Inagaki, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an
English language translation of record).
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issuing a first operation code to the memory device, wherein in
response to the first operation code, the memory device inputs the first
amount of data.
14. A method of operation in a synchronous memory device, wherein the
memory device includes a plurality of memory cells, the method of
operation of the memory device comprises:
receiving first block size information from a memory controller,
wherein the memory device is capable of processing the first block size
information, wherein the first block size information represents a first
amount of data to be input by the memory device in response to an operation
code;
receiving the operation code, from the memory controller,
synchronously with respect to an external clock signal; and
inputting the first amount of data in response to the operation code.
21. The method of claim 14 further including generating an internal clock
signal, using a delay locked loop and the external clock signal wherein the
first amount of data is input synchronously with respect to the internal clock
signal.
22. The method of claim 14 further including generating first and second
internal clock signals using clock generation circuitry and the external clock
signal, wherein the first amount of data is input synchronously with respect
to the first and second internal clock signals.
23. The method of claim 22 wherein the first and second internal clock
signals are generated by a delay lock loop.

Appeal 2012-001917
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Patent 6,425,863 B2

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ANALYSIS
I. Anticipation – iAPX Manual

Rambus does not present separate patentability arguments for claims
1-20 and 24-28 rejected as anticipated by the iAPX Manual. Rambus argues
that “a ‘memory device’ is a chip and does not encompass a memory module
including a memory controller and a collection of memory devices.”
(Rambus App. Br. 8.) While Rambus provides separate section headings for
claims 10 and “14-20 and 24-28” (Rambus App. Br. 14), Rambus’s
arguments there also reduce to the single chip argument alluded to in the
previous sentence. As such, claim 1 is selected to represent claims 1-20 and
24-28.
The Federal Circuit recently decided against Rambus regarding the
same issue involving a similar claim – claim 18 discussed further below. In
re Rambus Inc., App. No. 2011-1247 (Fed. Cir. Aug. 17, 2012) (holding that
the claimed memory device is not limited to a single chip so that the iAPX
Manual anticipates the sole claim at issue there). As Micron points out, with
respect to the claims rejected as anticipated, each of Rambus’s arguments
essentially reduce to the single chip argument (see Micron Resp. Br. 4, 13-
14) dismissed by In re Rambus as incorrect.
Rambus also argues here, in an oblique fashion, that the bus interface
unit (BIU) of the iAPX Manual is not a memory controller. Rambus points
out that the iAPX Manual “states that ‘the BIU performs as an intelligent
switch [and the] MCU acts as an intelligent memory controller.’” (Rambus
App. Br. 13 (quoting iAPX 1-1).) Rambus also argues that “neither the bus
interface units nor the memory control units provide the alleged block size
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information or operation codes to the memory devices in the storage array.”
(App. Br. 13 (emphasis added).) This argument reduces to the incorrect
assertion that the iAPX MCU (memory control unit) is not part of the iAPX
memory module which reads on the claimed memory device – as In re
Rambus held.
As In re Rambus also decided, the iAPX BIU reads on the “bus
controller” recited in claim 18 at issue there, which follows:
18. A method of operation of a synchronous memory device, wherein the
memory device includes a plurality of memory cells, the method of
operation of the memory device comprises:
receiving an external clock signal;
receiving first block size information from a bus controller, wherein
the first block size information defines a first amount of data to be output by
the memory device onto a bus in response to a read request;
receiving a first read request from the bus controller; and
outputting the first amount of data corresponding to the first block
size information, in response to the first read request, onto the bus
synchronously with respect to the external clock signal.5

(Farmwald et al., U.S. 6,034,918 (Mar. 7, 2000) claim 18 (emphasis added).)

Comparing claim 18 in In re Rambus and claim 1 here reveals that
claim 18 recites a “receiving first block size information from a bus
controller” while claim 1 recites “receiving first block size information from
a memory controller.” (Emphasis added.) Claims 1 and 18 respectively
require write and read operations, but little distinction exists in terms of the
claimed functions recited in the two controllers; they both send block size
information. (Claim 18 also requires receiving a read request from the bus

5 This claim is also discussed in Rambus Inc. v. Infineon Technologies AG,
318 F.3d 1081, 1091-1092 (Fed. Cir. 2003).
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controller, but claim 1 does not specify whence the read operation code
emanates, while claim 14 requires it to emanate from the memory
controller.)
The Examiner notes that Rambus had not made any specific
arguments about why the iAPX BIU could not constitute the claimed
memory controller since it satisfies the claimed function of (implicitly)
sending or transferring block size information. (See RAN 71.)6 Rambus
does not direct attention to any difference between the “memory controller”
recited in claim 1 or the “bus controller” determined by In re Rambus to read
on the BIU in the iAPX Manual. As In re Rambus reasons,
it is the bus controller (i.e., the ‘BIU’) of the iAPX that is akin
to the BIU that Rambus distinguished during prosecution . . . .
There is no suggestion that the BIU of the iAPX is within the
memory module, rather it is clearly outside of the memory
module, thus satisfying the requirement that the memory
module receive a request from a bus controller.

See In re Rambus, slip op. at 16 (emphasis added).7

6 It appears that Rambus, for the first time and on appeal (i.e., after the
Examiner’s RAN), references the BIU as an “intelligent switch,” but
Rambus does not explain in a clear fashion why such an “intelligent switch”
does not satisfy the memory controller recited in the claims. (See Rambus
App.Br. 13.) Instead, as indicated, Rambus devotes the bulk of its brief to
various permeations of the single chip argument. For example, after
referring to the BIU as an “intelligent switch,” Rambus argues that the MCU
is an “intelligent memory controller” and as such, cannot form part a
memory device, i.e., according to Rambus, only a single chip (e.g., a single
chip in the iAPX storage array) constitutes a memory device. (See, e.g.,
Rambus App. Br. 13.) In re Rambus rejected that single chip argument as
noted.
7 See also Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1084-
1086, 1091-1092 (Fed. Cir. 2003)(also addressing, inter alia, claim 18 in the
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The Board reasoned similarly in the underlying decision that Rambus
appealed in In re Rambus:
In other words, unlike the BIU and array in Jackson, but like
the memory device in the ‘918 patent, the iAPX memory
module is confined to its own area, and receives commands
from an external processor (i.e., the BIU . . .).
See BPAI 2010-011178 decision at 28 (emphasis added).
Rambus’s statement that the iAPX does not disclose sending block
size information in an operation code to a memory device similarly focuses
on the incorrect single chip argument- i.e., it is premised on the incorrect
assumption that the iAPX Manual’s memory module is not a memory
device. (See App. Br. 13-14.)8
Rambus’s contention that the BIU is an “intelligent switch” also
overlooks the fact that the BIU is part of the master processor module in the
iAPX system which singly or together function as the memory controller
recited in the claims: “Each processor and its associated BIUs form a
module.” (iAPX 1-3; Fig. 1-2.) “The master processor and its associated
BIUs generate memory bus requests.” (iAPX 1-8.) “The BIU is also
responsible for arbitrating the usage of the memory bus.” (iAPX 1-3.) The

‘918 patent, and finding that the written descriptions of each of four related
Rambus patents, 5,954,804; 5,953,263; 6,034,918; and 6,032,214, are
substantially identical to the written description of the 07/510,898
application to which they, and the ‘863 patent here, all claim continuity).
8 For example. Rambus argues that “the alleged operation code is not
provided to or received by the [single chip] DRAMs, as they only receive
conventional [operations].” (App. Br. 14.) Rambus continues the argument
as follows: “Thus under the correct construction of “memory device,” it is
undisputed that iAPX does not disclose providing ‘block size information’
or ‘issuing an operation code’ to a [single chip] memory device, as recited in
claim 1.” (App. Br. 14.)
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BIU also checks for error by using parity checking and stops memory
requests if errors occur. (See iAPX 1-7, 1-8.) For example, “[n]o
information (control, address, or data) can leave a GDP confinement area
without first being checked for correctness by one of the BIUs in the
module.” (iAPX 1-7.) The BIU also “accepts the access request from an
iAPX 432 processor and, based on the physical address, it decides which
memory control bus(es) will be used to control the access.” (iAPX 1-3.)
Micron points to this master processor module as satisfying the
memory controller limitation in the claims: “[T]he processor module of
iAPX (which includes the BIU and a processor) (see iAPX at 1-3) comprises
a memory controller in the context of the ‘863 patent.” (Micron Resp. Br.
14.) The Examiner similarly finds that “[t]he BIU accepts the access
requests from an iAPX processor and, based on the physical address, it
describes which memory buses will be used.” (See 95/000,250 Office
Action 18 (July 3, 2008).) The Examiner, like Micron, also refers to “other
controllers external to[] the memory module and those controllers is [sic:
are] equivalent to the claimed memory controller since those controllers
such as the BIU control the memory by issuing requests and control signals
to the memory device (e.g., block size and read/write requests are sent).”
(RAN 71 (emphasis added).)
The record supports the Examiner’s finding and Micron’s contention
that the iAPX processor module, which includes the BIU and a processor
(see iAPX 1-3), performs memory control functions, and the BIU and the
processor singly or together perform several memory control functions
identified by Rambus. For example, Rambus argued to the Federal Circuit
in In re Rambus that “[a] person of ordinary skill would understand a
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memory controller to perform functions such as ‘fault tolerance, error
checking, bus arbitration, and address queuing.’” (Rambus’s In re Rambus
Appeal Brief at 25.) Rambus makes a similar argument here about memory
controllers: “The memory control unit also performs functions that are
associated with controllers, not memory devices, such as fault tolerance,
error checking, bus arbitration, and request queing.” (Rambus App. Br. 12.)
As discussed supra, the iAPX BIU performs error checking,
arbitration, and at least some manner of “address queuing,” since the BIU
selects an address to which to send requests. Rambus has not directed the
Board in this proceeding to limitations in the ‘863 patent defining or limiting
the claimed “memory controller” here and distinguishing it from the claimed
“bus controller” involved in the ‘918 patent and in In re Rambus (the patents
date back to a common application, 07/510,898 – see supra note 7).
Presumably, a bus controller and a memory controller, defined (if at all) by
the common ‘898 application, refer to the same device.
Rambus does not specifically rely on the ‘863 patent specification for
any distinction between a bus and memory controller, and presents the
Board with the following unsupported definition of a memory controller:
“Consistent with the understanding of one of ordinary skill in the art,
Rambus has construed a ‘memory controller’ to be ‘an integrated circuit
device that includes circuitry to direct the actions of one or more memory
devices.’” (Rambus App. Br. 13.)9 Since, based on the foregoing

9 Rambus’s proposed definition to the Federal Circuit in In re Rambus
(quoted supra) does not include the “integrated circuit device” limitation.
According to Infineon, 318 F.3d at 1090, an “integrated circuit device” is
limited to a single chip (based on its ordinary and customary meaning
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discussion, the iAPX BIU “directs actions” of one or more memory modules
in the iAPX system (and In re Rambus held that such a memory module
constitutes a memory device), the iAPX BIU satisfies the claimed memory
controller under at least one of Rambus’s proposed definitions (assuming
arguendo that Rambus’s proffered definition limits or defines the term).
Bus access requests at least pass through the BIU from its associated
processor in the module. Claim 1 recites “wherein the first block size
information is provided by the memory controller” while claim 14 recites
“receiving first block size information from a memory controller.” Neither
claim specifically requires the memory controller to issue the block size
information. But even if they do so implicitly, the BIU and its associated
processor are all part of the same processor module, and assuming for the
sake of argument that the BIU does not satisfy the claimed memory
controller, as Micron and the Examiner point out, the iAPX processor
module which includes the BIU does control memory functions as discussed
supra. (See also iAPX Figure 1-2; Micron Resp. Br. 14.)
Rambus responds to Micron in its Rebuttal Brief by simply providing
generic denials, but Rambus fails to provide any significant argument
distinguishing the iAPX memory processor module or its associated BIU
from the claimed memory controller. (See Rambus Reb. Br. 6.) Rambus
attempts to incorrectly shift the burden to Micron to show error and define
Rambus’s claimed invention.

according to a trade dictionary). But under the recent logic and holding in In
re Rambus, absent a more specific claim recitation, since the claimed
“memory device” is not limited to a single chip, neither is the claimed
“memory controller.”
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Under In re Rambus and the arguments presented, Rambus has
presented no principled reason to the Board for distinguishing the claims
here from the holding under In re Rambus. Based on the foregoing
discussion, the iAPX Manual anticipates claims 1-20 and 24-28. As such, it
is unnecessary to reach the cumulative rejection involving Budde. Cf. In re
Gleave, 560 F.3d 1331, 1338 (Fed. Cir. 2009) (not reaching obviousness
after finding anticipation).

Claim 21 – iAPX and Lofgren
Micron’s analysis and responses to Rambus’s arguments persuasively
show that the Examiner did not err in the rejection of claim 21 which
depends from claim 14. (See Micron Resp. Br. 15-19.) Micron’s analysis
and responses and the Examiner’s findings (RAN 94-98) are adopted and
incorporated herein by reference.
Rambus argues that the Examiner equates a delay lock look (DLL)
with a PLL (phase lock loop) but also finds that they are different, and that
somehow, these findings show that “the Examiner does not show that
Logfren discloses a delay lock loop” or meets the Examiner’s definition of a
delay lock loop. (Rambus App. Br. 17.) This argument does not distinguish
the delay circuit of Lofgren. As discussed in a related appeal, BPAI 2011-
008431, Rambus’s experts have stated that a DLL and PLL can be used for
the same or similar purposes. In light of the ‘863 patent, including its Figure
12, and past statements by Rambus, Lofgren discloses or at least suggests a
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delay locked loop as required by claim 21.10 Micron also points out that
Rambus referred to Figure 12 in its related patents to show support for a
DLL and a PLL and provides persuasive rationale as to why, in light of the
‘863 patent, Lofgren teaches a DLL as set forth in claim 21. (See Micron
Resp. Br. 16.)
As Micron also points out, Lofgren also discloses creating precise
internal integrated circuit delays which are delayed by one clock cycle
relative to a previous clock cycle. (Resp. Br. 15-16.) The Examiner makes
similar findings, reasoning that iAPX requires precise delays to output data
and that Lofgren’s system supplies such delays. (See RAN 97.) Micron
points out that the iAPX memory device MCU outputs and inputs different
data and/or signals at different bus interfaces, including the MACD bus
based on an external clock, thereby suggesting a reason for using precise
delays relative to the external clock. As Micron reasons, it would have been
obvious to employ Lofgren’s DLL to ensure precise clocking for the various
data inputs and outputs at different interfaces in the iAPX memory module,
where Lofgren teaches precise delays in integrated circuits of an integer
number of clock cycles. (See Micron Resp. Br. 16-18.)

10 The examiner also found in that related case that combining Lofgren and
the iAPX system would have been obvious with Lofgren essentially teaching
an accurate timer using a delay line. The Board noted that Rambus
essentially equated and/or advanced substantial similarities between PLLs
and DLLs, and agreed with the examiner that combining Lofgren with the
iAPX Manual would have been obvious. See BPAI 2011-008431 at 30-32.
The prior ‘8431 Board decision and reasoning related to Lofgren is adopted
and incorporated herein by reference.

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Rambus argues in rebuttal that skilled artisans “would have
understood that the delay lines of Lofgren are used to achieve time
separation between the external signals used to control the DRAMs.”
(Rambus Reb. Br. 9.) Rambus also asserts that Lofgren is directed to
external control of memory devices, and that even if “the alleged DLL of
Lofgren were placed on the memory control unit of the iAPX system and
used to generate control signals applied to the asynchronous DRAMs, it
would still be unrelated to the alleged ‘memory device’ receiving data over
the MACD bus.” (Rambus Reb. Br. 9.)
This rebuttal argument is another form of the single chip argument
and does not account for the fact that the iAPX MCU and DRAMS
constitute the memory device of the claims as In re Rambus holds. In other
words, Micron’s and the Examiner’s rationale is premised on the memory
device MCU inputting data from the MACD bus; i.e., inputting data from
the bus to the claimed memory device (which includes the MCU and its
DRAMs). (Accord iAPX at BIU-20; MCU-41.)
While Rambus also argues that the iAPX system runs too slow to
obtain the benefits of a DLL (Rambus App. Br. 20), faster speeds would
have been available at the time of the invention as Micron argues. (See
Micron Resp. Br. 18; note 13 infra.) Also, Rambus agrees that Lofgren
performs precise delays and such delays are used to control various DRAM
signals and to account for voltage and temperature variations. (See Rambus
App. Br. 18-19.) This supports the Examiner’s and Micron’s rationale that
the iAPX memory device could have benefitted from such precise delays
even with slower or faster speeds. (See Micron Resp. Br. 18.)
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Rambus’s argument that Lofgren teaches external clock signal control
is not clear. (See Rambus App. Br. 19.) Claim 21 does not specifically
relate the recited term “internal” to the claimed memory device. As such,
any “internal” signal could be satisfied by implementing a DLL internal to
another chip. But even if “internal” refers to a memory device, Micron
persuasively shows that the iAPX memory device receives external clock
signals and reasons that using such a reference as an external reference to
generate internal delay signals within the memory device would have been
obvious in order to generate precise timing signals in the iAPX memory
device, thereby overcoming sensitivity to voltage and temperature changes
in integrated circuits as Lofgren suggests. (See Micron Resp. Br. 17-18.)
Based on the foregoing discussion, Rambus fails to show error in the
rejection of claim 21 based on iAPX and Lofgren. As such, the Budde based
rejection is not reached. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir.
2009) (not reaching obviousness after finding anticipation).

Claim 22 – iAPX and Inagaki
Claim 22 depends from claim 14, and requires “generating first and
second internal clock signals using clock generation circuitry and the
external clock signal, wherein the first amount of data is input
synchronously with respect to the first and second internal clock signals.”
The Examiner finds and concludes that the combined teachings of iAPX and
Inagaki render the claimed feature obvious. (See RAN 99-103.)

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Inagaki’s Teachings
I1. Inagaki discloses a method for increasing data rates in block
access memory. As background, Inagaki teaches that conventional methods
to increase data transfer rates in RAMs involved increasing the data bus
width, which adds cost of packaging and pin count, or to increase the clock
rate. (Inagaki 2.) Inagaki’s solution is to use dual edges of a clock as
quoted as follows.
I2. “The rise and fall of external clock φ are detected, and clocks φ1
and φ2 are generated. Clocks φ1 and φ2 drive shift pulses of the shift
register. . . . In this way, since one bit is output on each half-cycle, the
operating speed is twice that of the conventional speed.” (Id. at 4.)
I3 “[T]he present invention presents block access memory that
transfers data with a speed that is twice the conventional speed, by
performing I/O [input/output] of data on every half-cycle of the external
clock that drives the I/O shift register.” (Id. at 3.)
I4. Inagaki refers to “an internal timing generator circuit that controls
the memory cells, read circuit, row and column decoders, data input buffer,
I/O shift register, and data output buffer, wherein; the I/O shift register
performs data input or output every half-cycle based on an external clock.”
(Id. at 3.)
I5. Inagaki also specifically refers to synchronous operation: “Clock
φ1 is generated synchronously with the external clock φ.” (Id. at 5.)
Discussion
Rambus maintains that using Inagaki’s clocking scheme in the iAPX
system would not have been obvious because Inagaki uses shift registers and
a non-periodic pulse, as opposed to a clock, and the iAPX system uses dual
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edges of two clocks for other specific functions. (See App. Br. 21-26.)
Rambus’s arguments reduce to the unpersuasive assertion that the two
systems must be bodily incorporated. See In re Sneed, 710 F.2d 1544, 1550
(Fed. Cir. 1983) (“[I]t is not necessary that the inventions of the references
be physically combinable to render obvious the invention under review.”); In
re Nievelt, 482 F.2d 965, 968 (CCPA 1973) (“Combining the teachings of
references does not involve an ability to combine their specific structures”).
And Inagaki refers to an “external clock” repeatedly and the clock is
periodic at least while it operates (I2-I4): “The rise and fall of external clock
φ are detected, and clocks φ1 and φ2 are generated. . . . . In this way, since
one bit is output on each half-cycle, the operating speed is twice that of the
conventional speed.” (Inagaki at 4.) Inagaki’s system performs “data input
or output every half-cycle based on an external clock.” (Id. at 2; accord I2-
I4).) Inagaki’s numerous external clock references point skilled artisans to
and embrace the well-known computer clock – in other words, the same type
of external computer clock generically claimed in the ‘863 patent.11 See In
re Paulson, 30 F.3d 1475, 1480-81 (Fed. Cir. 1994) (“a prior art reference
must be ‘considered together with the knowledge of one of ordinary skill in
the pertinent art’,” and where the skill level was “‘quite advanced’ . . . ‘one

11 clock . . . A source of accurately timed pulses, used for synchronization in
a digital computer . . . .” McGraw-Hill Dictionary of Scientific and
Technical Terms 387 (Fifth Ed. 1994). This reference indicates that clock
signals and clock pulses are the same: i.e., “clock signals. See Clock
pulses.” Id. “[C]lock pulses. . . . Electronic pulses which are emitted
periodically, usually by a crystal device, to synchronize the operation of
circuits in a computer. Also known as clock signals.” Id.

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of ordinary skill certainly was capable of providing the circuitry necessary to
make the device operable for use as a computer’”) (citations omitted).
Rambus’s prosecution history argument (see Rambus App. Br. 22
(citing, without attaching to the Brief, a March 21, 2002 amendment at 7, n.2
in the prosecution of App. No. 09/969,489)) that Rambus distinguished the
type of clocks involved in Inagaki fails to address the combined teachings
involving the iAPX periodic clocks or the notion that skilled artisans, see
Paulsen, 30 F.3d at 1480-81, would have recognized that Inagaki teaches
periodic external and internal clocks based on the ordinary use of the term
and the Inagaki’s synchronous clock operation. (See I5; note 11).12
Micron relies on the combination, including the iAPX external clocks,
to suggest using the rising and falling edges of a clock. The iAPX system
employs dual edges of two different periodic clocks (i.e., CLKA, CLKB) as
Rambus acknowledges (App. Br. 24-25), and Inagaki teaches using dual
edges of a single clock in order to increase speed or reduce the number of
data paths in a memory device. (I1-I3.) For example, Inagaki discloses

12 Rambus’s prosecution history arguments are also not persuasive to
distinguish Inagaki’s clock for another reason. That is, while Rambus did
argue, inter alia, that “‘the external clock signal’ [as claimed] is a periodic
signal used to orchestrate timing events (e.g., a read operation),” Rambus
did not specifically and clearly argue that the CAS and RAS input clock
signals in the prior art were not periodic – while Rambus appears to have
made that argument with respect to another “asynchronous strobe signal.”
(See 09/969,489 amendment at 7, n.2.) But even if Rambus did make that
argument in a clear fashion, Rambus made numerous other arguments, and
the prior examiner did not rely on any such distinction and provides different
reasons for allowance, including “timing of the output drivers” or “precharge
information in the operation code.” (See Notice of Allowance 2 in App. No.
09/969489.)
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“performing I/O [input/output] of data on every half-cycle of the external
clock that drives the I/O shift register.” (I3.) As the Examiner finds, in
Inagaki’s system “[t]he two internal clocks allow for the input/output of data
to be received/output at twice the data rate as the external clock. (RAN
100.) “[I]f a technique has been used to improve one device, and a person
of ordinary skill would recognize that it would improve similar devices in
the same way, using the technique is obvious unless its application is beyond
his or her skill.’” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417
(2007)(citation omitted).
As the Examiner reasons, skilled artisans would have recognized that
Inagaki teaches that data bus systems, like that of iAPX, could have
benefitted by outputting data onto bus lines by using the rising and falling
edges of a clock to double the normal data transfer speed. (See I1-I3; RAN
99-102.) Rambus alleges that Inagaki’s shift registers render unobvious
using dual edge clocks in the iAPX system for data transfer to the MCU, but
the iAPX system already employs dual clock edges as Rambus also
acknowledges. (See Rambus App. Br. 25.) Therefore, contrary to Rambus’s
assertions, skilled artisans would have understood how to implement the
known feature of using both clock edges on data to maximize speed whether
shift registers were employed or not. The fact that iAPX system uses both
rising and falling edges of the clock for other purposes means that skilled
artisans would have recognized that the iAPX system contains circuitry
available to send/receive data on both edges without a shift register. (See
RAN 100.)
Rambus’s allegation that Inagaki’s “combinatorial logic” limits speed
also lacks merit. (Rambus App. Br. 26.) Inagaki’s system increases the
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20
speed over prior art systems and Rambus does not direct attention to where
Inagaki describes any such logic, let alone logic which slows down Inagaki’s
system. (See I1-I4.) If by “logic,” Rambus refers to logic associated with a
shift register, such logic is not required to implement dual pulse edges as the
iAPX Manual teaches as discussed supra.
Rambus further argues that clocks φ1 and φ2 are aperiodic shift pulses
instead of internal clocks. (Rambus App. Br. 24.) To the contrary, Inagaki’s
“clocks φ1 and φ2 drive shift pulses” and are generated by the rising and
falling edges of an external clock. (I2.) They form part of the “internal
timing generator circuit that controls the memory cells, read circuit, row and
column decoders, data input buffer, I/O shift register, and data output
buffer.” (See I4.)
Rambus also argues that the iAPX system’s buffer directional control
somehow precludes data transfers on both edges of CLKB. (See App. Br.
25.) But claim 22 does not require two-way traffic implicit in the argument,
or even a buffer, so the argument is not commensurate in scope with the
claim. Alternatively, skilled artisans would have recognized that buffer
directional control could have been provided with other CLKA or CLKB
edges or even with other bused signals. Rambus has not demonstrated that
skilled artisans would have been unable to modify the combined system to
increase the speed as Inagaki teaches.
Inagaki’s teachings, and the iAPX use of dual edges, also evidence a
reasonable expectation of success in using dual clock edges on data for
increased speed. Increased speed and compactness by reducing bus width
and corresponding pin number while saving cost (see I1) constitute universal
motivators. Dystar Textilfarben GmBH & Co. Dutschland KG v. C.H.
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Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir. 2006) (“[A]n implicit
motivation to combine exists … when the ‘improvement’ is technology-
independent and the combination of references results in a product or
process that is more desirable, for example because it is stronger, cheaper,
cleaner, faster, lighter, smaller, more durable, or more efficient.”) Such a
reasonable expectation of success outweighs Rambus’s allegations about
changing the principle of operation or rendering the iAPX system inoperable
for its intended purpose. (See App. Br. 24-25.)
The Federal Circuit recently rejected a similar inoperability argument
by noting that any claimed “difference does not affect the operability of
Mouttet’s [i.e., the applicant’s] broadly claimed device—a programmable
arithmetic processor.” In re Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012)
(citations omitted) (also reasoning that physical incorporation is not required
to support obviousness).
The principle of operation of Applicant’s broadly claimed memory
device here involves synchronously outputting data using first and second
internal clock signals. The iAPX principle involves the ability to transfer
data to and from a memory module using clock signals, depending on the
data. Hence, using one or two external clocks does not undermine the broad
principle of transferring data. In other words, the iAPX principle of
transferring data “is not unique to its . . . [dual clocking] operation.” See
Mouttet, 686 F.3d at 1332. Also, the Court has recognized that “the
interaction of multiple components means that changing one component
often requires the others to be modified as well.” KSR, 550 U.S. at 424.
Making other required modifications to increase the data speed by using
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both clock edges, as Inagaki teaches (I1-I3), does not defeat obviousness or
show inoperability.
Rambus fails to present evidence that skilled artisans would have been
unable to modify interrelated parts. Moreover, the arguments are not
commensurate in scope with broad claim 22 which does not have significant
interrelated features other than those required to output data synchronously
using two clock edges of a clock signal. As such, given the claim breadth,
skilled artisans could have modified the iAPX system in view of Inagaki’s
clocking scheme by dropping unneeded functions. For example, with one
(or a handful more) DRAM(s), which the claims do not preclude, and which
Inagaki suggests, arbitration schemes would not be required. Such a
modification would create a “cleaner” memory device for handling mere
one-way or two-way data transfers embraced by broad claim. Making a
device “cleaner” (i.e., simpler) constitutes a universal motivator under
Dystar.
Alternatively, the proposed combination does not require dropping
iAPX functions or a significant amount thereof. Skilled artisans would have
recognized that the iAPX system could have been modified to include the
external slower Inagaki clock as a trigger for the faster CLKA and/or CLKB.
That is, Inagaki (see Fig. 4) teaches that fast clocks can be created by using
the dual edges of a slower external clock: In Inagaki, a slower external
clock φ has rising and falling edges corresponding to and triggering faster
clocks φ1 and φ2, suggesting a similar external clock to trigger signals such
as iAPX CLKA and CLKB signals or modified versions thereof. (See e.g.
Inagaki Fig. 4; I3, I4.) Inagaki and iAPX both employ multiple clock
signals, rendering such a combination obvious.
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The slower external clock’s rising and falling edges would trigger the
existing CLKA and CLKB, with the external clock’s rising and falling edges
corresponding to the existing rising edges of faster CLKB and/or CLKA.
(See RAN 100 (“using the teaching of the generation of two internal clocks
from an external clock as disclosed by Inagaki”).) The iAPX Specification
heuristically illustrates this concept (which Inagaki teaches as noted) by
showing a slower “INIT” clock trigger signal with falling and rising edges
corresponding to the faster CLKA rising edges. (See BIU-41.) The ‘863
patent similarly discloses using internal clock complements being created or
triggered by external bus clocks. (See Fig. 13, App. Br. 21 (describing the
‘863 patent’s 500 MHz clock as triggered by dual edges of a 250MHz
clock).)
Despite Rambus’s related arguments about existing device limitations
based on speed (see Rambus App. Br. 24-26), faster memory chips than
those disclosed in the iAPX system would have been available at the time of
the invention.13 Rambus’s argument that skilled artisans would have used a

13 For example, Rambus expert and inventor Dr. Farmwald testified that 50
MHz computers were available in the late 1980s and that, while DRAM
speed increased at a slower rate than CPUs (which doubled in speed yearly),
solutions were available if expensive. (See Farmwald Trial Dep. 268, 269,
275-276 (attached as Rambus App. Br. Evidence Ex. E-5).) Another article
of record, published in 1989, shows that an IEEE working group would
establish single DRAMs at 500MHz (i.e., “500 hundred million transfers per
second”) as a standard and that there was “no technical reason for this” lack
of speed/bandwidth. See Moussouris, Life Beyond RISC: The Next 30 Years
in High-Performance Computing, Technologic Comp. Let. V. 5, No. 5, p. 2
(July 31, 1989) (attached, inter alia, as Exhibit A (which refers to the article
as Exhibit E to Samsung’s Comments) to Micron’s Third Party Requestor
Comments (filed July 22, 2009).) A patent to Bennett, filed in 1986 and also
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faster clock show that speed would have been desired to accommodate chip
speed advances (see App. Br. 24) with Inagaki’s solution an alternative to a
faster clock. Both iAPX clocks could have been rendered faster as device
speed increased prior to the claimed invention in 1990.
And even if the iAPX components could not have handled faster
speeds, the iAPX system could have benefitted, at the time of the invention,
from a slower external clock’s dual pulse speed doubling function as a mere
substitute or trigger for the existing clock timing, as Inagaki suggests (see
I1-I3). The broad claims recited here do not require any set speed.
Rambus also raises an untimely new argument in its Rebuttal Brief
improperly buttressed by new evidence and thereby waives the argument.
Rambus alleges that the iAPX system requires holding BIU data on the
MACD bus over successive rising edges of CLKB, thereby precluding data
transfers on the falling edge between the two rising edges. (See Rambus
Reb. Br. 12-13 (newly citing BIU-43 as evidence).)14 But even if Rambus’s
characterizations are correct and timely, such data holding does not impact
the substitution and modification rationales described supra. For example,
having rising and falling edges of an external clock trigger the rising CLKB

of record (see Micron’s Cr. App. Br. 3), refers to a 25 MHz preferred
embodiment, but expected 20ns (50MHz) speed. (See U.S. 4,734,909, col. 9,
ll. 58-60; col. 13, ll. 50-54.)

14 Rambus supports the argument by discussing inherent hold and delay
times in the iAPX system. Rambus does not persuasively demonstrate that
those delays necessarily impact the data length on the bus. See id. at 11-12.
See BIU-40, 41, 43) (describing various inherent time delays between clock
edges and signals based on capacitance, etc.) Similar delays would occur in
the ‘863 patent system, but any such delays are not addressed in depth, if at
all.
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25
edges does not impact any timing relying on those rising CLKB edges,
regardless of the data hold length. Or, replacing the iAPX system’s dual
clock system with Inagaki’s simpler single clock system to handle simple
one-way (or two-way) data transfers, without arbitration and other unneeded
functions pursuant to the breadth of claim 22, would obviously involve using
dual clock edges based on whatever the signal length constraints dictate.
Inagaki’s system provides the fastest speed relative to the dual clock edges
regardless of the data length, where speed is ultimately governed by the dual
edges of the clock or the bus width and the system constraints. (See I1-I3.)
Further, setting aside the above-discussed rationales for a moment,
while Rambus relies on an example to show that data is held over successive
CLKB edges (see Reb. Br. 12), this does not mean that the iAPX MACD
data cannot be modified to correspond to rising and falling clock edges.
Rambus’s reliance on specific examples does not show that the iAPX system
requires the data to be held for the duration argued, or that the data could not
have been modified to be held for less than the time defined by the CLKA
pulse, or that the CLKA pulses could not be extended. As Rambus points
out, the iAPX Specification (at BIU-38) reveals that the BIU inputs and
outputs ACD15…0 data (to and from a processor) on both the rising and
falling edges of CLKB. (See Rambus App. Br. 25; BIU 20.) This ACD data
transfer further suggests the claimed combination since not all the iAPX data
had to be held for the duration that Rambus argues. The iAPX system
suggests, and Inagaki shows, that skilled artisans knew how to provide data
over the same bus using the falling and rising edges of a single clock.
In summary, the thrust of Rambus’s arguments, directed as they are
toward arbitration, buffer control, two-way traffic control between the
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26
master BIU and slave memory device MCU, and other unclaimed features
(see e.g., Rambus App. Br. 22-23), are not commensurate in scope with
claim 22, which does not require those features. Claim 22 broadly embraces
a method for controlling a memory device which samples one-way data
portions output from the memory device. Rambus has not demonstrated that
skilled artisans, motivated by Inagaki’s teaching of using rising and falling
clock edges for increasing data transfer speed to a known DRAM memory
device on a single bus, would not have been able to arrive at the broadly
claimed invention. Inagaki’s clocking scheme provides the fastest possible
signal transfer on a bus, regardless of any signal length delays advanced by
Rambus, thereby providing the motivation for the modification.
Rambus’s other arguments fail to demonstrate Examiner error. The
Examiner’s findings and rationale and Micron’s responses are more
persuasive than Rambus’s arguments. Based on the foregoing discussion,
Rambus failed to show error in the obviousness rejection of claim 22 based
on iAPX and Inagaki. See KSR, 550 U.S. 398, 416 (2007) (“The
combination of familiar elements according to known methods is likely to be
obvious when it does no more than yield predictable results.”). Affirmance
of the iAPX based obviousness rejection renders it unnecessary to reach the
Budde based obviousness rejection. Cf. In re Gleave, 560 F.3d 1331, 1338
(Fed. Cir. 2009) (not reaching obviousness after finding anticipation).

Claim 23 – iAPX, Inagaki, and Lofgren
Rambus maintains that it would not have been obvious to combine the
references in the manner suggested because Inagaki discloses pulses that
would be incompatible with a delay lock loop (DLL). (Rambus App. Br. 27;
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Rambus Reb. Br. 14.) But the combination teaches or suggests such a well-
known clock as discussed supra. Rambus’s similar argument that Inagaki’s
clocks signals are not internal clock signals because they are pulses is also
not persuasive for the same reasons. (See Rambus App. Br. 27.)
Moreover, as indicated supra, Inagaki recites an “internal timing
generator circuit” that controls various circuits in the RAM memory chip
device. (See I4.) Inagaki also refers to clock signals generated
synchronously with respect to an external clock and generally refers to an
external clock as discussed supra. (See I2, I4, see also Inagaki at 4; Fig. 10;
I1-I3.) As such, the combination of iAPX, Inagaki, and Lofgren suggests
internal clocks generated by an external clock. Since typical DLL internal
clocks drive various internal RAM circuits as Lofgren suggests and as
discussed above, this further suggests combining the DLL of Lofgren for
precise timing and delay.
Rambus’s remaining arguments primarily restate arguments presented
with respect to claims 21 and 22. Micron’s responses support the
Examiner’s findings and conclusion of obviousness. (See RAN 103-105.)
Affirmance of the iAPX based obviousness rejections renders it unnecessary
to reach the Budde based obviousness rejections. Cf. In re Gleave, 560 F.3d
1331, 1338 (Fed. Cir. 2009) (not reaching obviousness after finding
anticipation).

Secondary Considerations
Rambus contends that substantial secondary evidence supports
unobviousness. But the evidence fails to establish a nexus because any
success likely flows from a variety of several unclaimed features touted here
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or in other Rambus proceedings or patents. Such unclaimed, but disclosed
features, include eight data lines, small DRAM sizes with minimal bus
loading, multiplexed bus architecture and device interfaces, packetized
control, unique device identifiers, time access and arbitration schemes, a 500
MHz data rate, minimal clock skew system, a high speed cache method, a
narrow bus, and memory devices having all the functionality of prior art
circuit boards. (See ‘863 patent, col. 3, ll. 29-62; col. 4, ll. 3-6, 37-52; col. 7,
ll. 18-22; col. 9, ll. 23-30; col. 12, ll. 50-58; col. 14, ll. 48-50.) See also
Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1095 (Fed. Cir.
2003) (“‘The present invention is designed to provide a high speed,
multiplexed bus’” (quoting Rambus’s related ‘918 patent, col. 5, ll. 36-46),
but “the prosecution history shows that a multiplexing bus is only one of
many inventions disclosed in the ‘898 application.”) Rambus agrees that
“the original disclosure describes many inventions.” (Rambus Resp. Br. 22;
accord Murphy Decl. ¶ 30 (filed Jan. 18, 2011) (“the original disclosure
describes multiple objects of the invention”).)
As Micron points out, Rambus presents the same evidence it provided
“in every one of the 10 pending inter partes reexaminations.” (Micron Reb.
Br. 21.) Different claims in the different proceedings have varying scope.
Rambus’s evidence does not demonstrate that any success was due
solely to the claimed features, or to claimed features that were not already
known in the prior art. Rambus’s contentions about “significant sales” and
“that the Farmwald family, which includes the ‘863 patent, has numerous
licensees,” (App. Br. 29) are vague statements which do not show any sales
or even allege that the ‘863 patent is licensed. Rambus does not provide a
copy of any licenses (even if one does pertain to the ‘863 patent) or provide
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evidence showing what claimed features any of the licenses involve. Also, it
is well known and settled law that competitors often take licenses for
commercial or other reasons having nothing to do with unobviousness.
As discussed in related reexamination cases, see BPAI 2012-001639
at 45-47 (adopted and incorporated herein by reference), single chip
synchronous memory devices were known, as were DRAMs, precharging
and DLL circuits, as the prior art discussed supra also discloses. Hence, the
record suggests that at least part of any commercial success would have been
due to features already in the prior art, such as the popular DRAM memory
chip.15 Cf. In re DBC, 545 F.3d 1373, 1384 (Fed. Cir. 2008) (Board’s
conclusion of nonobviousness supported, the Board finding, inter alia, that
“evidence in the record suggested that the success of XanGo™ juice may be
due to other factors-for example, the increasing popularity of the
mangosteen fruit in general” ). The Federal Circuit, further observed in
DBC that
. . . DBC has done little more than submit evidence of sales.
However substantial those sales, that evidence does not reveal
in any way that the driving force behind those sales was the
claimed combination of mangosteen fruit, mangosteen rind
extract, and fruit or vegetable juice. Nor is there any evidence
that sales of XanGo™ juice were not merely attributable to the
increasing popularity of mangosteen fruit or the effectiveness of
the marketing efforts employed.

Moreover, while Rambus argues long-felt need, skepticism, praise,
and failure of others (see Rambus App. Br. 27-29), these arguments appear

15 See BPAI 2012-001639 at 44-45 (finding, based on cited prior art, that
DRAMs where “the most popular” memory chip at the time of the
invention) (adopted and incorporated herein by reference).
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to be directed to the a memory device as a single chip DRAM instead of the
broad claims recited here. Also, while Rambus argues that the memory
devices solve a memory bottleneck problem and obtain high-speed
performance (see App. Br. 28-29), the claims read on slow memory devices,
since the claims do not recite any speed (as a functional limitation) and do
not recite other sufficient and necessary circuitry to obtain such speed.16
Rambus’s allegations of recognition and praise for the “‘high bandwidth
memory-interface technology’” and other similar speed features “‘as a result
of the ideas [Dr. Horowitz] pioneered’” (App. Br. 29 (citation omitted)) lack
a nexus to the claims. The devices claimed here have no bandwidth
limitation, let alone limitations directed to the myriad other “ideas [Dr.
Horowitz] pioneered” – whatever they may have been.
Moreover, Dr. Farmwald testified that “even up into the early part of
the ‘90s, it [speed] wasn’t going to be a problem.” (See Farmwald Trial
Dep. 276 (attached as App. Br. Evidence Ex. E-5).) In other words, Dr.
Farmwald may have solved a problem predicted to occur in the future using
a single chip solution; i.e., not a long-standing problem commensurate in
scope with the broad memory device claimed here. The then-current

16 In another reexamination proceeding, similar to the proceeding here
(Resp. Br. 15), Rambus alleges “disbelief” and pervasive skepticism “‘over a
500 megabit per second DRAM data rate’” and “about many of the specific
features of the technology” as showing “‘strong evidence of
nonobviousness.’” See Rambus Resp. Br. 19 (citations omitted) in the BPAI
2012-000142 reexamination proceeding. Assuming for the sake of argument
that uncorroborated statements by the inventors show skepticism by others,
as noted, claims here do not require the 500 MHz speed touted or “many of
the other specific features” – whatever they may have been.
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technology solved any speed problems (using several chips) as Dr.
Farmwald indicates.
Based on the foregoing discussion, the record suggests that the
proffered evidence is not commensurate with the claim scope and lacks a
nexus thereto. Rambus has not demonstrated that any success is not due to
single DRAM chips which were known to be popular, synchronous memory
chips, synchronous memory devices such as the iAPX memory module, or to
a whole host of unclaimed features, including the unclaimed but touted
multiplexed bus interface, high bandwidth and/or speed, and other
unclaimed circuit features, such as the identification feature, arbitration
control features, low capacitance and power, etc. See Ormco Corp. v. Align
Technology, Inc., 463 F.3d 1299, 1312, 1313 (Fed. Cir. 2006) (“[I]f the
feature that creates the commercial success was known in the prior art, the
success is not pertinent.” Reasoning that success that is due “‘partially’ to
claimed features” and to unclaimed features and/or other features already in
the art lacks the requisite nexus to show unobviousness.) (citations omitted).  
The record also indicates that such added features (and other
pioneering ideas) would have been required to obtain the touted high speed
from a single DRAM. See Infineon, 318 F.3d at 1095 (quoted supra,
mentioning Rambus’s high speed multiplexed system).
Rambus has not established that its secondary evidence is
commensurate in scope with the broad reach of the claims. See Application
of Tiffin, 448 F.2d 791 (CCPA 1971) (commercial success evidence of
thermoplastic foam cups is not commensurate in scope with broad claims
directed to thermoplastic foam containers). Even if Rambus’s evidence does
point to the unobviousness of using dual internal clock edges or a DLL
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circuit inside of a single DRAM, the proffered evidence does not rebut the
obviousness of using these known features within other memory devices
such as the iAPX memory module and array.
Rambus’s proffered secondary considerations fail to outweigh the
evidence and rationale of record for combining known prior art dual edge
clock features with known memory device methods to yield predictable
results as set forth in the method claims at issue here.
Weak secondary considerations generally do not overcome a strong
prima facie case of obviousness. See Media Techs. Licensing, LLC v. Upper
Deck Co., 596 F.3d 1334 (Fed. Cir. 2010), cert. denied, 2010 WL 2897876
(Oct. 04, 2010) (“Even if [the patentee] could establish the required nexus, a
highly successful product alone would not overcome the strong showing of
obviousness.”).
DECISION
The Examiner’s decision to reject claims 1-28 is affirmed. Requests
for extensions of time in this inter partes reexamination proceeding are
governed by 37 C.F.R. § 1.956. See 37 C.F.R. § 41.79.

ack
cc:
Appeal 2012-001917
Reexamination Control Nos. 95/000,250 & 95/001,124
Patent 6,425,863 B2

33
Patent Owner
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP
901 New York Ave., N.W.
Washington, DC 20001-4413

Third Party Requester Samsung
HAYNES AND BOONE, LLP IP SECTION
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DALLAS, TX 75219

Third Party Requester Micron
NOVAK, DRUCE & QUIGG, LLP
(NDQ REEXAMINATION GROUP)
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HOUSTON, TX 77002