Ex Parte 6426916 et al

Board of Patent Appeals and Interferences

Jun 14, 2012

95000166 (B.P.A.I. Jun. 14, 2012)

UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/000,166 08/22/2007 6426916 38512.3 7919 22852 7590 06/14/2012 FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP 901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413 EXAMINER ESCALANTE, OVIDIO ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 06/14/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARKOFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 95/001,122 11/20/2008 6,426,916 8963.002.916 1557 22852 7590 06/14/2012 FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP 901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413 EXAMINER ESCALANTE, OVIDIO ART UNIT PAPER NUMBER 3992 MAIL DATE DELIVERY MODE 06/14/2012 PAPER Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE BOARD OF PATENT APPEALS AND INTERFERENCES ____________ MICRON TECHNOLOGY, INC. Requestor, Appellant v. RAMBUS INC. Patent Owner, Respondent ____________ Appeal 2012-001638 Inter Partes Reexamination Control No. 95/000,166 & 95/001,122 United States Patent 6,426,916 B2 Technology Center 3900 ____________ Before ALLEN R. MacDONALD, KARL D. EASTHOM, and STEPHEN C. SIU, Administrative Patent Judges. EASTHOM, Administrative Patent Judge. DECISION ON APPEAL Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 2 This proceeding arose out of separate requests by Micron and Samsung Electronics Ltd. for inter partes reexaminations of U.S. patent 6,426,916 B2 to Farmwald et al., Memory Device Having a Variable Data Output Length and A Programmable Register (issued July 30, 2002, claiming priority to April 18, 1990) assigned to Rambus. Samsung has not filed a Brief in this proceeding. Appellant, Requestor Micron, appeals from the Examiner’s decision in the Right of Appeal Notice (RAN) rejecting claims 26 and 28. The Examiner’s Answer relies on the RAN, incorporating it by reference. We have jurisdiction under 35 U.S.C. §§ 134(b) and 315. We REVERSE the Examiner’s decision rejecting claims 26 and 28. STATEMENT OF THE CASE Rambus and Micron refer to several related judicial and other proceedings including inter partes and ex parte reexaminations, International Trade Commission proceedings, and Federal District Court and Circuit Court proceedings in their briefs. An oral hearing of this appeal transpired on May 2, 2012 and was subsequently transcribed. Appellant, Requestor Micron, appeals the Examiner’s refusal to maintain the rejections of claims 26 and 28 as anticipated by Bennett1 or JEDEC2, and claim 26 as anticipated by Park.3 The appealed claims follow: 1 Bennett et al., US 4,734,009 (Mar. 29, 1988). 2 Joint Electronic Device Engineering Counsel (JEDEC) Standard No. 21-C, Revision 9 (1999). 3 Park et al., US 5,590,086 (Dec. 31, 1996, effective filing Oct. 1993). Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 3 26. A synchronous semiconductor memory device having at least one memory section including a plurality of memory cells, the memory device comprising: clock receiver circuitry to receive an external clock signal; first input receiver circuitry to sample block size information synchronously with respect to the external clock signal, wherein the block size information is representative of an amount of data to be output by the memory device in response to a first operation code; a register which stores a value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data; and a plurality of output drivers to output the amount of data in response to the first operation code and after the amount of time transpires. 28. The memory device of claim 26 wherein in response to a second operation code, the value is stored in the register. (‘916 patent at cols. 26-27 (reformatted by Board).) ANALYSIS One issue is whether Bennett discloses a memory device which can sample block size information and store a first delay value recited in claim 26. Another issue is whether Bennett discloses the second operation code of claim 28. Another issue is whether the ‘916 patent has written description support prior to the filing dates of the Park and JEDEC references. Bennett’s Teachings B1. Bennett’s “paramount object” is to provide communication between “very large scale integrated VLSI (circuit) elements” (col. 12, ll. 14-18) - i.e., “VLSIC chips” (col. 9, ll.35-40). Bennett discloses combining Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 4 Versatile Bus Interfaces (VBI) and VLSIC “upon the same chip substrate as the VLSI User Device” (col. 12, ll. 29-32) with such a user device including “interfaces intended to be built with a CPU, IOC or Memory, or similar User device for signal or data exchange” (col. 35, ll. 59-61). (See also col. 14, ll. 19-24 (describing “interface to the user devices (usually upon the same chip substrate)”.) As another example demonstrating a preference for a single chip, Bennett states that “[e]ach Versatile Bus Interface Logics, for example Versatile Bus Interface Logics 102a [of Fig. 1], interfaces a User module, for example VLSI Circuit User Device 106a which is pictorially represented in shadow line within FIG. 1 as existing on the same VLSIC chip substrate as Versatile Bus Interface Logics 102a.” (Col. 36, ll. 19-24.) Bennett’s chips have up to 120 pins as a practical limit. (Col. 9, ll. 60-61.) Bennett also discloses different memory types as “Fast Memory” or “Large Memory” with the memory having address widths of 16, 24, or 32, and one fast memory embodiment having 37 pins (col. 92, ll. 15-56; Fig. 32). One large memory has at least 16 pins to access 232 addresses by employing two 16-bit address words over successive clock cycles. (See col. 95, ll. 59-60; Fig. 36.) B2. Figure 38 shows “memories device” 3802c and 3802d connected to a “Versatile Bus.” (Col. 97, ll. 8-10.) In the next paragraph, Bennett refers to “VSLI chips hav[ing] access to all Versatile Bus lines and therefore, the Versatile Bus protocols.” (Id. at ll. 20-22.) Bennett elsewhere refers to “memory devices” including, but not limited to, a ROM: “Not all memory devices can perform all operations; for example, read only memory (ROM) cannot execute the write operations.” Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 5 (Col. 90, l. 66 to col. 91, l. 2.) Bennett then refers to “[s]ample memory operations in the following paragraphs” (col. 90, ll. 4-5) and thereafter describes “relatively small fast memories, and . . . larger and relatively slower memories” (col. 92, ll. 13-14). Bennett also refers to “VLSIC chip devices” and in the next full sentence (under the “Section 4.1” heading) states that “[m]any, if not most, applications of VLSIC technology are likely to include memory devices.” (Col. 90, ll. 42-43.) Bennett generally discusses these chip devices as employing the interconnection protocol standards outlined generally in Section 3 and more specifically discusses memory devices in Section 4 of the ‘051 patent. (Id. at ll. 36-41.) For example, as discussed in Section 4 of Bennett, Figures 32 and 33 represent fast memory write operations using data on 16 pins and 16 other pins for arbitration and slave ID. (See col. 93, l.12 - col. 94, l. 56.) Figure 36 represents pin and timing for a write operation to a large memory device with a 4315335 protocol “configuration.” (See col. 26, ll. 54-57.) Figures 25a-h, represent more generic slave device configurations as discussed in Section 3 of Bennett. (Col. 25, l. 58 to col. 26, l; see generally columns 81- 88). B3. In addition to chips, Bennett also discusses memory cards in Section 2, “Description of the Prior Art” (see col. 5, l. 52 et seq.), and states that “the functionality of VLSIC chips is often similar to cards today” but that “VLSIC technology promises much higher performance than that of cards,” even though cards hold more memory and chips have higher development costs. (Col. 9, ll. 43-56.) In following passage, Bennett discusses creating larger chips to accommodate a greater numbers of pins. Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 6 (Col. 9, l. 66 to col. 10, l. 29.) Bennett also states that interfaces between chips would be as impractical as providing interfaces between cards. (Col. 9, ll. 37-41.) B4. Bennett describes a “third physical objective” - the VBI (versatile bus interface) “should occupy a reasonable VLSI circuit substrate area” using fast and efficient CMOS technology as the preferred embodiment. (Col. 13, ll.18-23.) Typically, only 20 VLSIC devices will be interconnected. As a “first logical object,” the VBI logics “should offer a fixed format, simply controlled, powerfully featured interface to the user devices (usually upon the same chip substrate)” yet with certain options for use. (Col. 14, ll. 20-30.) B5. Figures 25a-h, described in section 3 of Bennett, depict timing diagrams for slave devices on the VLSIC bus which have eight configuration parameter digits (e.g., 122123XX) for the devices. (See col. 86, ll. 31-32.) Master and slave devices make agreements using the different configurations, and Bennett describes masters and slaves in terms of “chips.” (See col. 74 (“no other chips”).) For Figures 25a-h, and for preferred embodiments, Bennett discloses only two choices (i.e., either digit 1 or 3) for the sixth configuration parameter which specifies the number of wait lines between chips transferring data. (See col. 86, ll. 31-41; 55-58; col. 83, ll. 30-40; col. 76, ll. 1-2 (preferred embodiments have zero or one wait line); col. 86, l. 31 - col. 87, l.8 (only specifying configuration digits of either 1 or 3 for the sixth (VI) parameter in Figures 25a-h); col. 86, ll. 55-67 (explaining that wait nullity 2 “should not be used”); compare Figure 3 (generally allowing for configuration digits 1, 2, 3, 4, or 5 for the sixth parameter). The digit 1 Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 7 signifies that the wait function is pin multiplexed (Mpx) on data lines while the digit 3 signifies one designated wait line. (See Fig. 3; col. 86, ll. 31-48.) The sixth parameter configuration digits, 1 and 3, indirectly dictate a relative number of clock cycles which transpire after a function (read or write) signal and a subsequent Wait signal: “Data transfers begin after Wait if multiplexed, or simultaneously with Wait if pipelined . . . .” (Col. 77, ll. 40-41.) (The “pipeline” refers to transferring the wait signal to its own designated pin so that waiting, otherwise required with multiplexing over the same lines, is not required.) As Figures 25a-h show, relative to the ID/FUNCTION command, which includes a read or a write (see e.g. Fig. 35, 36),4 the sixth configuration digit 1 corresponds to an extra clock cycle, based on multiplexing, as compared to the total clock cycle number corresponding to the sixth configuration digit 3, based on pipelining. This extra clock cycle which occurs every time the sixth parameter digit is 1 in Figures 25a-h, amounts to four total clock cycles, or two clock cycles after a function command such as write (i.e., the ID/FUNCTION command). On the other hand, every time the sixth digit is 3 in Figures 25a-h, the delay amounts to three total clock cycles, or one clock cycle after the read or write command (i.e., ID/FUNCTION command). (Compare Figs. 25a, c, e, and g (sixth parameter 1) with Figures 25b, d, f, and h (sixth parameter 3); col. 85, l. 9 to col. 87, l. 6.). 4 Bennett also refers to functions as operations, which include read or write operations. (See col. 91, l. 62 to col. 92, l. 8; col. 91, ll. 43-53 (“functional operations”); Figs. 31, 35, 36.) Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 8 B6. For memory device writes, address information can be sent during the function cycle or during the data cycle. (Compare Fig. 31 with Fig. 36; col. 91, ll. 43-53.) B7. Bennett discloses synchronous clocked communication between bused VLSIC chips over 16 data lines at 25MHz, and notes that synchronous communication is more efficient than asynchronous communication. (Col. 13, ll. 3-17; col. 66, l. 9 - col 67, l.18; col. 101, ll. 50-54 (“all communication . . . is synchronously referenced”); col. 102, ll. 9-27.) Discussion I. Anticipation - Bennett Rambus maintains that the Board should confirm the claims for the same reasons that the Examiner does. (Resp. Br. 2.) Micron shows (App. Br. 12-14; Reb. Br. 2-4) that the Examiner’s articulated reason (RAN 99- 104) - i.e., that Bennett’s sixth configuration parameter (see B5) does not satisfy the representative time value recited in claim 26 - is in error. Rambus adds numerous other reasons alleging Examiner error as to other claim elements which the Examiner finds disclosed in Bennett. Micron’s contentions and the Examiner’s findings persuasively demonstrate otherwise. (See RAN 86-107; App. Br. 3-15; Reb. Br. 1-17).) The Board’s prior decisions (BPAI 2012-000168 and 2012-000169) address the same or similar issues raised by the parties here as to the same or similar claim elements. Also, a previous District Court Order makes extensive factual findings with respect to Bennett and the same or related claim elements in dispute here which the Examiner largely follows.5 Micron’s contentions and 5 December 15, 2008 Order Granting in Part and Denying in Part Rambus’s Motion to Strike; Denying Motion for Summary Judgment No. 1 of Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 9 the Examiner’s findings with respect to Bennett (App. Br. 1-15; Reb. Br. 1- 17; RAN 86-105), and the prior findings in the listed Board prior decisions, are adopted and incorporated by reference herein, except that this Decision does not incorporate the Examiner’s rationale regarding claim 26 and Bennett’s sixth configuration (wait) parameter and any underlying findings supporting that rationale, as explained further below. The Examiner largely followed the findings and the District Court Order. Rambus argues here as it similarly argued before the District Court that Bennett does not disclose a single chip memory device implicitly required by the “synchronous semiconductor memory device” recited in claim 26. Rambus maintains that Bennett does not disclose that the VBI (Versatile Bus Interface) is on the same chip substrate as the memory and that only certain disclosed User devices (i.e., not memories) are single chips. (See Resp. Br. 9-10.) Rambus also argues that Bennett fails to disclose receiving an external clock signal and a request for an operation code, because Bennett fails to disclose a single chip memory. (Id. at 12-16.) The Examiner finds, in line with the District Court and Micron, that Bennett specifically refers to a “memory device” as a type of user device with a VBI and that this memory is on a single chip substrate. (See RAN 86- 89, 89 (adopting and quoting the DC. Order); D.C. Order 17-21 (also adopted and incorporated by reference herein), 21 (“The court concludes that Invalidity; and Striking Motion for Summary Judgment No. 2 of Invalidity, Hynix Semiconductor Inc. v. Rambus Inc., No. 00-2905, Rambus Inc. v. Hynix Semiconcudtor Inc., No. 05-334, Rambus Inc. v. Samsung Electronics Co., Ltd., No 05-2298 RMW, and Rambus Inc. V. Micron Technology, Inc., No. 06-244 (N.D. Cal.) (stayed, Judge R. Whyte) (attached as Ex. O-3 to Resp. Br.). Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 10 . . . Bennett discloses a memory device, and that Rambus has failed to rebut this finding.”).) As in the District Court, Rambus similarly fails to rebut the Examiner’s findings here for reasons largely set forth by the Examiner, Micron, the District Court, and our prior decisions listed supra. Bennett discloses externally clocked synchronous user devices as chips and memories as such user devices, and also refers to “memory devices” connected to the Versatile Bus while implying such devices are VLSIC chips. (B1-B5; B7.) Bennett refers to “VLSIC chips” and discloses combining Versatile Bus Interfaces (VBI) and VLSIC “upon the same chip substrate as the VLSI User Device” with such a user device including “interfaces intended to be built with a CPU, IOC or Memory.” (B1.) Rambus’s arguments here contradict other arguments made elsewhere before the PTO and in numerous related proceedings that a “memory device” only signifies a memory chip to skilled artisans.6 Bennett’s disclosure of the same term, “memory device” (B2), references to “VLSIC upon the same chip substrate,” “interfaces intended to be built with . . . Memory,” (B1) and other similar references to VLSIC, chips or “same” substrates (B1-B5), combined with a limited discussion of memory cards as prior art (B3), all show that Bennett’s memory device includes a single chip embodiment (even if the term also signifies other memory forms of memory 6 See e.g., Rambus reexamination now on appeal to the Federal Circuit, In re Rambus, App. No. 2011-1247 (BPAI App. No. 2010-0011178, Reexam. No. 90/010420) (the Board holding that the term “memory device” is not limited to a single chip contrary to Rambus’s arguments); accord Rambus’s Appeal Brief 5-22 in In re Rambus (Rambus advancing the same or similar arguments that the ordinary meaning and specification dictate that a memory device is limited to a single chip). Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 11 as Rambus argues). Micron’s similar reliance on the memory chip of Bennett’s Figure 1 and memory devices in Figure 38 bolsters the Examiner’s findings. (See App. Br. 5; accord B1, B2.) The Examiner also finds that Bennett discloses synchronous clocked operation which the record supports. (RAN 97 (quoting Bennett at col. 125, ll. 46-56); accord B7).) Rambus argues that Bennett does not disclose a register which stores a value which represents a delay period after which the memory device outputs the first amount of data. (Resp. Br. 2-5.) Rambus argues that “Micron has done nothing more than argue that, in certain circumstances, changing the number of wait times may change when data is sampled” and this does not show the required “representative” relationship. (Resp. Br. 3.) But Micron sufficiently shows the relationship because Bennett’s distinct embodiments relied upon by Micron represent a “memory device” having a representative time delay correlation regardless of whether or not some embodiments may employ the same sixth configuration parameter to show a different time delay. For example, in Bennett’s Figure 25a or Figure 25b embodiments, the sixth parameter 1 or 3 each constitute “a value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data.” A single embodiment is sufficient to anticipate a claim. Rambus’s argument that the same parameter in Bennett may result in different delay times in different embodiments proves nothing. As a related example, the ‘916 similarly envisions different encoding schemes for another value, the claimed block value. (‘916 patent, col. 11, ll. 66-67.) This necessarily means that the same coded block value in the ’916 patent may represent a different data block size in the different embodiments (and Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 12 that other logic must be provided with these codes to interpret the different codes). In a similar fashion, the ‘916 patent discloses picking a delay value from “registers 173;” therefore, skilled artisans would have understood that some associated control would be required to select the correct register to choose the desired value and that such registers could include the same values encoded differently across different embodiments. (See col. 9, ll. 17- 25.) Therefore, even if Bennett’s system employs the same value so that the parameter 3 for example results in different delay times in different embodiments, claim 26 embraces different embodiments having delay values which may or may not represent different times. Moreover, claim 26 fails to specify what starts the “representative . . . time” value - i.e., the phrase “after which” lacks a starting reference point. The claim is broad enough to encompass any number of starting points “after which” the “representative” time “value” starts and thereafter “transpires.” Bennett states that “Data transfers begin after Wait if multiplexed [corresponding to a configuration value of 1], or simultaneously with Wait if pipelined [all other values except 2].” (Col. 77, ll. 40-41.) These transfers occur either one clock cycle or two clock cycles after the initial ID/FUNCTION (write or read) command in Figures 25a-h, with the two choices determined respectively by the sixth (VIth) configuration parameter (see Figure 3). The choice of 1 signifies multiplexing the wait (WT) signal with other data on the data lines which translates to transmission one cycle after the WT signal (a delay of one clock cycle), and the choice of 3 signifies one wait line and “pipelining” different data on different lines so that the WT signal and data transmit at the same time (no delay). (See B5.) Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 13 Rambus compares how the same digit 3 causes different delays from the read or write request in different embodiments (Resp. Br. 4 (comparing Bennett’s Figures 25b, 35, and 36)), but such a comparison of different embodiments fails to show error in the anticipation by any single configured embodiment as explained supra. Rambus does not dispute Micron‘s contention that changing the sixth parameter from 3 to a 1 in Figure 36, following the pattern between Figures 25b and 25a, results “in a change in when the data is sampled.” (Resp. Br. 4 (citing App. Br. at 14).) Rather, Rambus maintains that Micron does not account for other possible digits, such as 2, 4, or 5 - see Bennett Fig. 3. (App. Br. 4-5.) But Bennett only employs digits 1 or 3 for the different configurations specified in Figures 25a-h and discloses a general preference for only using those digits in other embodiments. (B5.) Further, as Micron points out, Rambus fails to show how these other choices for the sixth parameter digits show a claim distinction as “the claim language . . . does not require multiple delay times associated with multiple unique stored values.” (Reb. Br. 4.) Still further, Bennett’s digits show a predictable pattern, with digits 3-5 resulting in no delay relative to the wait signal, 1 resulting in a delay of one clock cycle relative to the wait signal, and the 2 not employing a wait signal - but 2 results in the same delay as the digits 3-5 relative to the FUNCTION/ID signal based on the record and corroborating arguments presented by Rambus.7 7 See Resp. Br. 5 (Rambus explaining that “values 2, 3, 4, and 5 . . . result[] in the exact same number of clock cycles transpiring before sampling within a given system”); id. at 2-3 (explaining that if the value is greater than 2, wait and data are transmitted simultaneously as in Figure 25b, but that if the Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 14 Rambus argued belatedly, and without persuasive detail, in the oral argument before the Board, that Figures 25a-h do not relate to memory. (See BPAI 46-47.) Rambus does not present this argument in its Brief, but argues generally that Bennett does not disclose a memory chip. In any event, Figures 25a-h represent generic slave devices and hence encompass memory devices, and it follows, memory chips, according to the discussion supra. (See B1, B2, B5). The District Court similarly refers to Figures 25a and 25b as representing a “memory device” (D.C. Order 23), and the Examiner implicitly makes a similar finding by considering the figures in terms of other claim limitations unrelated to the memory device limitation. (See RAN 100.) Micron also persuasively explains that Bennett’s Figures 25a, 25b, and 31- 36 (App. Br. 11-13; Reb. Br. 5, 7) signify different configurations for memory devices and that Bennett’s system knows the specific timing relationship for each protocol configuration: Bennett’s protocol defines “‘the what (what operations), when (in what relationship and/or sequence), and where (which lines and pins are used) of bussed digital communication activities.’” (App. Br. 15 (quoting Bennett at col. 39, ll. 31-34); Reb. Br. 5; 7.) For example, the District Court explains that Figures 32 and 33 correspond to pipelining operations with data on the clock cycle following the operation or function cycle. (D.C. Order at 22.) The District Court also explains that Bennett’s preferred operations employ pipelining over three total clock cycles - relative to the BEGIN signal. (D.C. Order at 22 (citing Bennett at col. 44, ll. 21-23).) value is 1 as in Figure 25a, data is transmitted on one clock cycle after the wait signal). Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 15 As Micron further points out, the Examiner finds that Bennett’s “‘Figures 25a and 25b show that a change in the configuration values changes the number of clock cycles that transpire.’” (Resp. Br. 13 (quoting RAN at 103).) The Examiner similarly finds that the two configuration digits, 1 and 3, in Figures 25a and 25b, result in an output change between the two figures of “one clock cycle.” (RAN 103.) This finding is sufficient to show the claimed delay with respect to those two configurations. As Micron explains (Resp. Br. 13), the Examiner’s rationale (RAN 103-104) that Figures 35 and 36 show that there is no “representative” type of correlation incorrectly compares differently configured memories. Bennett’s system envisions similar correlations between read and write timings, but Bennett’s system also envisions variations across different embodiments in order to provide flexibility to system designers. Bennett’s Figures 35 and 36 both represent “large memory” operations, but Figure 35 represents an arbitration system for a single 16 bit data word read operation, with “a 16 bit address (addresses 64K words)” (col. 95, ll. 6-7) for each 16 bit word, while Figure 36 represents a system employing a 32 bit word and address write operation - “232 addresses of 32 bit words shown in FIG 36” (col. 95, ll. 58-60). The Examiner reasons that since Figures 35 and 36 each have the same value of 3 for the sixth configuration parameter, and each figure shows a different clock delay with respect to the wait signal, that this proves that the configuration parameter “is not ‘representative’ of an amount of time.” (RAN 103.) Rambus agrees, but again, this incorrect comparison merely shows that different embodiments may result in different delays for the same digit value. (See Resp. Br. 4.) As Micron stresses, comparing a change of Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 16 parameter from 3 to 1 in a single embodiment, including Figure 36, shows that Figure 36 memory device also satisfies the disputed term. (App. Br. 14.) (And even if Figure 36 does not, this does not mean that Figures 25a and 25b do not satisfy the claim, as explained supra.) Moreover, the Examiner and Rambus incorrectly focus on the wrong data line in Figure 36. Bennett treats addresses and data similarly in some embodiments, such as the Figure 36 embodiment, and the “data” does occur at the same time as the wait signal (one clock cycle after the write command) as the sixth digit 3 predicts. “[I]n FIG. 36 note that Wait is not time multiplexed and occurs during the first data cycle. . . .Write operation . . . dictates that the indicated two sixteen bit addresses will be followed by the indicated two sixteen bit data words.” (Bennett, col. 96, ll. 19-29.) “Four data words which constitute a four word block data transfer are shown in FIG. 36.” (Bennett, col. 95, ll. 56-57.)8 “[I]t simply looks like the User is block transferring 4 sixteen bit words (sixteen bits is the maximum User to Versatile Bus Interface Logics word size with the preferred embodiment of this invention).” (Col. 95, l. 67 to col. 96, l. 2.) Bennett also refers to “a block of 4 sixteen bit data words.” (Col. 96, l. 42.) Bennett mentions that in this Figure 36 “large memory” embodiment, “four total cycles . . . requires . . . some associated control,” with the “first 8 In the next sentence (id. at ll. 58-59), Bennett refers to “32 bit words shown in FIG. 36” as indicated supra. Bennett’s Figure 36 embodiment transfers a 32 bit word which may be envisioned as two 16 bit words accessed by a 32 bit address which may be envisioned as two 16 bit addresses (or words). Rambus’s arguments exploit this terminology difference in “word” or “block” size with respect to Figure 36 and incorrectly conflate any such terminology difference to allege a lack of anticipation with respect to other embodiments. Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 17 received halves [of data and address words] as the most significant bits [a]s mere convention.” (Col. 96, ll. 33-38.) Therefore, the sixth parameter digit 3 in Figure 36 represents a single clock delay value for the data group relative to the write command when the data is viewed as one entity - i.e., including the address “data” - as the 3 digit does in other Bennett embodiments such as Figure 25b. Hence, for the Figure 36 embodiment, as in other embodiments, Bennett’s system knows when the data is to be transferred so that the sixth configuration parameter 3 constitutes “a value that is representative of an amount of time to transpire after which the memory device outputs the first amount of data.” And even though Bennett’s system may require “some associated control” to utilize the information in the sixth configuration parameter, the value of 3 is still representative as claimed. Claim 26 does not preclude associated control. As explained supra, the ‘916 patent indicates that some associated control is required so that the system can decode the transmitted block value and find the correct register and delay value. In oral argument, Rambus also raised a new argument that the data word in Figure 35 transpires, pursuant to arbitration, an indeterminate number of clock cycles after the initial read request from the requestor. (See “FUNCTION=0=READ” in top portion of Fig. 35; BPAI Tr. 47-49.).) This characterization ignores the fact that the memory device can win arbitration on the first instance. Claim 26, a device claim, only requires this capability. Also, even if Figure 35 does not satisfy the claim limitation, other embodiments do as noted supra. Even when the device eventually wins arbitration, relative to the wait signal (WT) in Figure 35, the sixth configuration digit of 3 signifies that data Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 18 will be sent at the same time as the WT signal (i.e., pipelined on separate data lines), but more importantly, one cycle after the “FUNCTION=READ=0” signal which is sent back to the requestor. (Bennett, bottom portion of Fig. 35; col. 95, ll. 28-31.) As explained above, claim 26 does not specify any particular signal to trigger the time delay. In other words, the parameter 3 in Figure 35 corresponds to the following broad reading of claim 26: “a value that is representative of an amount of time to transpire after which [a read acknowledgment signal from the memory device to the requestor] the memory device outputs the first amount of data.” Rambus also remarked during oral argument that some of Bennett’s embodiments relied upon by the Examiner do not employ a wait. (See BPAI Tr. 47-49.) Rambus was referring to embodiments in which no wait lines are employed - i.e., when a sixth configuration digit of “2” is employed. But Bennett’s wait signal is not required to satisfy claim 26. The sixth parameter digit 2 constitutes the claimed value which signifies a delay relative to the operation (read) command. For example, in Figure 32, a “high speed” configuration (42252255), the device transmits 16 data bits in one clock cycle after the operation command. (See Bennett, col. 92, ll. 46- 51.) Rambus also argues that the Examiner incorrectly finds that Bennett discloses “block size information . . . representative of an amount of data to be output by the memory device” as set forth in claim 26. The Examiner (RAN 97), relying partly on the District Court Order (at 31-33, see also D.C. Order at 10-14, 32), finds that the single word read operation which Bennett discloses satisfies the disputed limitation. Rambus’s arguments fail to show error in this finding. As the District Court found, Bennett’s configuration Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 19 parameters VII and VIII “specify the total amount of data to be transferred in response to Bennett’s based, single-word read or block write operation.” (D.C. Order 32.) Rambus focuses on Figure 36 (Resp. Br. 7-8) and argues that since that figure represents employing the values 5 and 5 for configuration parameters VII and VIII, the system should only send a single 16 bit word - as occurs with for example, Figure 32. (See Resp. Br. 8.) This argument fails to rebut the Examiner’s and Micron’s contention that Bennett’s single word transfers (see Bennett’s Figures 31-33) satisfy the claims.9 (RAN 97 (relying on the District Court Order); App. Br. 8; Reb. Br. 5-8).) Bennett contemplates different word lengths as signified by the different configuration parameters VII and VIII listed in Figure 3 (1, 2, 4, 8, 16), rendering each different word length a block of total data, at least when transmitted over single clock cycle. (Accord note 9.) Alternatively, Rambus’s contentions also fail to demonstrate that Figure 36 does not satisfy claim 26. Rambus reasons that since Bennett’s Figure 36 embodiment requires “‘some associated control’” to transfer 4 sixteen bit words in succession, this proves that the configuration parameters VII and VIII do not provide “representative” block size information. (Resp. 9 For example, with respect to Figure 32, the sixth configuration digit of 2 shows “pipelined” activity and hence, “no Wait, the slave test memory must accept data” right after the read or write operation. (See Fig. 32, col. 92, ll. 41-50.) “The seventh and eighth configuration digits establish that 16 data bits will be transferred in 1 Data Cycle.” (Bennett, col. 92, ll. 44-46.) Figures 32 and 33 represent similar fast memory devices, but Figure 33 employs a 4, 4 for the seventh and eighth configuration digits, instead of 5, 5, thereby resulting in an 8 bit word over one data cycle which also immediately follows the operation code or read or write. (See Bennett, col. 93, l. 56 to col. 94, l.5; Fig. 33.) Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 20 Br. 8 (quoting Bennett).) But as explained supra, claim 26 does not preclude any “associated control” from using the two parameters to represent the total word size read. According to the findings supra, Bennett’s system knows exactly how large the total data transfer will be, regardless of whether Bennett refers to that data group as two 32 bit words, four 16 bit words, two 16 bit addresses and two 16 bit data words, or a block. The parameter VII and VIII values of 5 and 5, in that specific Figure 36 large memory device, dictate a16 bit word on 16 lines per clock cycle, a total of four clock cycles, all of which translates to 32 bit data word on two clock cycles following a 32 bit address on two previous clock cycles - pursuant to a write request in that embodiment. (Accord RAN 96-97.) Shifting to another theory of anticipation by Micron as regards the block size information element in claim 26, Micron contends that Bennett’s block transfer operations satisfy it. (App. Br. 8-10.) The Examiner finds (RAN 98) and Rambus contends (Resp. Br. 9), in line with the District Court Order (D.C. Order 31)), otherwise. The claim phrase “block size information . . . representative of data to be output in response to the first operation code” seems to imply that the memory device processes the block size information before all the data is output by the memory device, but Rambus does not specifically make this argument. In any event, according to Micron, Bennett discloses two busy signals which precede and predict three data blocks in Figure 52b, thereby reasonably satisfying claim 26 even under the implied interpretation noted supra. (See App. Br. 8-9.) Micron explained during oral argument that this purported correlation in Figure 52b is consistent with other embodiments and Bennett’s overall scheme of transferring one more block of data than Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 21 then the number of busy signals. (See, e.g., BPAI Tr. 6-20.) The Examiner finds that other figures in Bennett do not show the required correlation, but this finding fails to rebut Micron’s explanation, as supplemented during the oral argument, about Figure 52b. (See RAN 98.) Only one embodiment is required to anticipate a claim. Rambus’s and the Examiner’s contention here, as it is with respect to other argued claim elements, is that evidence related to one embodiment shows that there is no correlation in another embodiment. The Examiner finds that the BUSY signal length in several embodiments correlates to the amount of data. (RAN 98.) But this finding does not explain adequately why Figure 52b does not satisfy claim 26. The record is not entirely clear with respect to Figure 52b. Since this reversal constitutes a remand and the “Block Read” related findings may not be fully developed, the Examiner will be in the best position to sort those issues out. (On the other hand, this alternative theory is not required to support the claim rejection and the Examiner may choose not to rely on it after a fuller development.) With respect to claim 28, the Examiner relies on the finding that Bennett fails to satisfy claim 26. (RAN 104-105.) Based on the foregoing discussion of claim 26, Micron shows error in this finding. (See App. Br. 15-16.) Micron also explains persuasively, in line with the Examiner, how Bennett satisfies the second claimed operation code. Rambus’s contentions do not explain how storing a value in a register in response to a second operation code is patentably distinct from shifting bits into the registers pursuant to the signals in Bennett. (Compare Resp. Br. 16-17 with App. Br. 15-16.) Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 22 While Rambus raises other truncated arguments about other claim elements, the arguments do not show error in the Examiner’s findings and rationale, as supplemented by Micron’s contentions. Based on the foregoing discussion and the record, Micron demonstrates that the Examiner erred in refusing to maintain the anticipation rejection of claims 26 and 28 based on Bennett. II. Priority (relative to the JEDEC and Park references) Micron asserts that claims 26 and 28 do not recite a multiplexed bus, and as such, are not originally supported back to the (first-filed) ‘898 application having a filing date of April, 1990 because the claim is too broad; i.e., too broad absent a recitation to a multiplexed bus which the ‘037 patent touts as important. Based on this contention, Micron asserts that the claims are not entitled to a filing date prior to the ‘916 patent’s application filing date of February 27, 2001, and is therefore anticipated by the JEDEC and Park references which antedate the 2000 date. (See App. Br. 16-28.) In turn, Rambus relies, inter alia, on Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081, 1094-95 (Fed. Cir. 2003) to show that the claims do not require a multiplex bus and are therefore originally supported. (Resp. Br. 24.) The Examiner agrees with Rambus that the claims are originally supported. (See RAN 56-57 (incorporating by reference previous office actions).) The Board’s related decisions (BPAI App. Nos. 2012-000142, 2012- 000168, and 2012-000169) address the same or similar issue between the Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 23 same parties. Our decision, analysis and findings there are adopted and incorporated by reference herein.10 As discussed in our prior decisions, Infineon held that the ordinary term “bus” could not be read restrictively as a “multiplexed bus” even though the patentee described the “present invention” in terms of a “multiplexed bus” in isolated portions of the specification because “the remainder of the specification and the prosecution history shows that Rambus did not clearly disclaim or disavow such claim scope in this case.” Infineon, 318 F.3d at 1094-95. Micron maintains that the claims violates the written description requirement since the ‘898 patent application touts the importance of a multiplexed bus and distinguishes prior art generic bus inventions. (See Micron Cr. App. Br. 16-20.) Micron supports the theory, which in essence, amounts to a scope of enablement attack on the claims, by relying, inter alia, on LizardTech, Inc. v. Earth Resource Mapping, Inc., 424 F.3d 1336, 1344 (Fed. Cir. 2005) (generic seamless DWT claim too broad absent an udapted sums limitation). (App. Br. 18.) Micron relies on a “key factor” in LizardTech as embodied in an analogy there to an inventor who describes a fuel-efficient engine in such detail that it would not necessarily support “a broad claim to every possible type of fuel-efficient engine.” (Id.) (quoting LizardTech at 1346).) As another example, Micron reasons that the claims 10 Rambus also contends that Micron lacks standing to raise this issue and that the Board cannot consider written description issues. (Resp. Br. 17-24.) For reasons articulated in the incorporated Board decisions supra (2012- 000168), Rambus’s standing arguments are not persuasive. Essentially, the appeal is an appeal based on the Examiner’s decision. The question of priority is not precluded in reexaminations. Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 24 here are analogous to the “spikeless” valve claims addressed in ICU Medical. (Id. at 19 (quoting ICU Medical, Inc. v. Alaris Medical Systems, Inc., 558 F.3d 1368, 1378 (Fed. Cir. 2009)). But the gravamen of these arguments is that the ‘916 patent inventors were not in possession of claims not requiring a multiplexed bus scheme including memory devices with interfaces for such multiplexing. However, Infineon’s claim construction analysis, at the minimum, implies that skilled artisans were in possession of generic bus claims. See Infineon, 318 F.3d at 1094-95 (noting that “multiplexing is not a requirement in all of Rambus’s claims” and that the PTO issued a restriction to a multiplexing group and a latency group, that “the PTO demonstrated an understanding of “bus” that is not limited to a multiplexing bus”). Rambus supports the possession of generic bus claims by pointing out that original claims 73 and 91 in the first-filed ‘898 application recite a generic bus. (Resp. Br. 24.) As Rambus also points out, skilled artisans would have understood that other important touted features in the ‘898 disclosure, including clocking schemes and writing blocks of data, could have been practiced on generic buses without a multiplexing interface. (See id. at 22-23.) Accord Infineon, 318 F.3d at 1095 (“a multiplexing bus is only one of many inventions disclosed in the ‘898 application”); cf. Crown Packaging Tech. Inc. v. Ball Metal Beverage Container Corp., 635 F.3d 1373, 1382-84 (Fed. Cir. 2011) (district court erred in finding lack of written description in generic claims where the application discloses separate solutions to related problems). Claims 26 and 28 at issue here require synchronous block size sampling and reading data after a time value delay. Skilled artisans would Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 25 have recognized that these touted features could have been practiced on known buses, whether multiplexed or not. The lack of multiplexing would have been much simpler than a multiplexing scheme. Cf. Hynix Semiconductor Inc. v. Rambus Inc., 645 F.3d 1336, 1351-53 (2011) (holding that evidence supported jury verdict of written description for similar Rambus claims where “the supposed genus consists of only two species, a multiplexed bus and a non-multiplexed bus”). Also, Micron’s spikeless valve analogy is not entirely apt here because valves were recited in the ICU Medical claims, but in the ‘916 patent claims, neither a bus nor an interface for attaching to a bus is recited, so ICU Medical does not dictate that the claims must support any type of bus or bus interface. But even if the claims implicitly require such a bus scheme, Rambus, the Examiner, the Infineon claim construction, and the Hynix Semiconductor written description analysis, show that on this record, the inventors originally possessed inventions directed to a generic bus scheme. Based on the foregoing discussion, Micron has not shown error in the Examiner’s finding that claims 26 and 28 have original written description support as necessary to antedate Park or JEDEC as prior art references. CONCLUSION Micron demonstrated that the Examiner erred in deciding not to maintain the anticipation rejections of claims 26 and 28 for anticipation based on Bennett. Micron did not demonstrate that the Examiner erred in deciding not to maintain the obviousness rejections of claims 26 and 28 based on one or more of JEDEC and Park. Appeal 2012-001638 Reexamination Control Nos. 95/000,166 & 95/001,122 Patent 6,426,916 B2 26 DECISION The Examiner’s decision to reject claims 26 and 28 is reversed.11 ack cc Patent Owner FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER LLP 901 NEW YORK AVENUE, NW WASHINGTON, DC 20001-4413 Third Party Requestors HAYNES & BOONE, LLP IP SECTION 2323 VICTORY AVENUE, SUITE 700 DALLAS, TX 75219 NOVAK DRUCE + QUIGG LLP 1000 LOUSIANA STREET 53rd FLOOR HOUSTON, TX 77002 11 See 37 C.F.R. § 41.77(b) (denominating a reversal of a refusal to reject as a new ground of rejection).