Ex Parte 6,324,120 et al

Patent Trial and Appeal Board

Jan 8, 2013

95000178 (P.T.A.B. Jan. 8, 2013)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/000,178 10/06/2006 6,324,120 38512.4 8591
22852 7590 01/08/2013
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
01/08/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Inter Partes
RAMBUS, INC.
Patent Owner

v.

SAMSUNG ELECTRONICS, CO., LTD. and
MICRON TECHNOLOGY INC.
Requesters
____________

Appeal 2011-009664
Reexamination Control Nos. 95/000,178 & 95/001,152
United States Patent 6,324,120 B2
Technology Center 3900
____________

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON (RAMBUS’S) SECOND REQUEST FOR REHEARING
Appeal 2011-009664
Reexamination Control 95/000,178 & 95/001,152
Patent 6,324,120

Rambus seeks relief in its second Patent Owner’s Request for
Rehearing (Aug. 30, 2012) (cited hereinafter as “Rambus 2nd Reh’g Req.”)
from the Board’s Decision on (Rambus’s) Request for Rehearing (July 30,
2012) (cited hereinafter as “1st Reh’g Dec.” ) which the Board designated as
a new decision under 37 C.F.R. § 41.79 to provide Rambus further
opportunity to respond to the Board’s findings with respect to a block size
information element recited in independent claim 26 of the ‘120 patent. (See
1st Reh’g Dec. 8.) In Response, Micron filed a second Third Party
Requestor’s Comments to Patent Owner’s Request for Rehearing Opposing
Rambus’s Request (Oct. 1, 2012) (cited hereinafter as “Micron 2nd Reh’g
Comments”).
In a rehearing request, appellants have the burden to “state with
particularity the points believed to have been misapprehended or overlooked
by the Board.” 37 C.F.R. § 41.52 (a)(1). Rambus has not made the requisite
showing.
Rambus seeks reconsideration of the Board’s finding that the prior art
Bennett patent discloses the claimed block size information recited in claim
26 of the ‘120 patent. (See Rambus 2nd Reh’g Req. 1-6.) The Board relied,
in part, on its decision in Appeal No. 2012-001638, adopting it and
incorporating it by references as Rambus notes. (See Rambus 2nd Reh’g
Req. 1.)
As Micron points out (Micron 2nd Reh’g Comments 1), the Board’s
first rehearing decision (1st Reh’g Dec. 7-8) addresses the block size
limitations by reference to a myriad of findings and other documents of
record, including, inter alia, a prior federal District Court Order (hereinafter
Appeal 2011-009664
Reexamination Control 95/000,178 & 95/001,152
Patent 6,324,120

3
Hynix II)1 involving the same parties and similar issues, the Board’s BPAI
2012-001638 decision involving the same block size information element
and other similar claim elements, the original reexamination request, the
Examiner’s findings in this reexamination proceeding, including the Non-
Final Office Action (July 22, 2009), the Action Closing Prosecution (ACP),
the Right of Appeal Notice (RAN), and Micron’s citations to Bennett as
responding to Rambus’s contentions, including Rambus’s reliance on
Rambus’s expert Murphy. (See 1st Reh’g Dec. 7-8 (citing, inter alia,
original Dec. at 16-17).) Micron responds here to Rambus’s arguments and
the comments which are responsive to the single word transfer in Bennett
are adopted and incorporated herein by reference. (See Micron’s 2nd Reh’g
Comments 1-4.) Rambus’s contentions are addressed below to simplify and
summarize the contentions, findings, and rationale and to address Rambus’s
newly-phrased arguments.
Rambus’s contentions fail to show that the Board overlooked or
misapprehended anything about how the claim 26 “block size information”
element reads on Bennett’s single word read operations. The Examiner, the
District Court (Hynix II), and the Board’s prior original and rehearing

1 Referred to in the Board’s previous (i.e., first) Decision on (Rambus’s)
Request for Rehearing as the “District Court Order.” (See 1st Reh’g Dec. 8,
n.8). That Order, now referred to as Hynix II, has been officially reported:
Rambus, Inc. v. Hynix Semiconductor, Inc. 628 F.Supp.2d 1114, 1132-38
(N.D. Cal. 2008) (Judge R. H. Whyte ruling on anticipation by Bennett of
similar claims in other patents, including U.S. 6,314,051 also addressed in
BPAI 2012-000169 original and rehearing decisions).
Appeal 2011-009664
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Patent 6,324,120

4
decisions all agree that Bennett’s single word read operations satisfy the
same or similar block size information element.2
As one example with regard to the single word transfer, as noted in
the ‘1638 decision, Bennett states that with respect to Figure 32, “‘[t]he
seventh and eight configuration digits establish that 16 data bits will be
transferred in 1 Data Cycle.’” (‘1638 Dec. 19, n. 9.) The Board also found
that “Figures 32 and 33 represent similar fast memory devices, but Figure 33
employs (4, 4) for the seventh and eight configuration digits, instead of (5,
5), thereby resulting in an 8 bit word over one data cycle which also
immediately follows the operation code or read or write.” (Id. (citing
Bennett at col.93, l. 56 to col. 94, l. 5; Fig. 33).) Similarly, in Hynix II,
Judge Whyte compared the disclosed block size information parameter in
Rambus’s 6,426,916 patent and the recited “block size information” in claim
16 of Rambus’s 6,452,863 patent, and concluded that “[i]ndisputably,
parameters VII and VIII specify the total amount of data that will be
transferred” and that “they . . . specify the total amount of data to be
transferred in response to Bennett’s basic, single-word read or write
operations.” Hynix II at 1139. Further, referring to the related ‘916 patent
disclosure, Judge Whyte found that “[a]nalogously, when Parameter VII
equals VIII, the two parameters ‘specify’ that one data word will be

2 In the ‘1638 decision, the Board, relying on Hynix II, found that Bennett
satisfies a similar claim element set forth in claim 26 of the related Rambus
6,246,916 patent: “block size information . . . representative of an amount
of data to be output by the memory device.” See ‘1638 Dec. at 18; Hynix II
at 1125-28, 1139 (discussing the VII and VIII configuration parameters).
Similar issues are addressed in the ‘1638 rehearing decision.
Appeal 2011-009664
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Patent 6,324,120

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transferred in response to basic read and write operations.” Id. (emphasis
added).
Nonetheless, Rambus attempts to shift focus from these single word
transfers in Bennett’s fast memory devices and contends that “Figures 31,
32, 33, and 36 are all part of the same preferred embodiment.” (Rambus 2nd
Reh’g Req. 2.) Rambus maintains that since the allegedly same embodiment
transfers different block sizes when using the same configured parameters
VII and VIII of 5 and 5, this shows that those parameters do not “define[] an
amount of data to be output by the memory” as claim 26 requires. (Rambus
2nd Reh’g Req. 2.)
But Rambus does not explain that if the different figures represent the
same embodiment as Rambus contends, why they produce different results.
The two different results between Figures 32 and 36 prove the embodiments
(i.e., species) are different - as opposed to proving that the configuration
parameters do not define the amount of memory output in each embodiment.
Bennett supports the finding and refers to a “large memory” for Figure 36
and a “fast memory” for Figure 32. For example, Bennett refers to Figure
36 as representing a “large memory of up to 232 addresses of 32 bit words.”
(Bennett, col. 95, ll. 58-59.) On the other hand, Bennett refers to Figures 31-
33 as representing a “fast memory” (Bennett, col. 92, ll. 19-22) in which, for
Fig. 32, “the seventh and eighth configuration digits [of (5, 5)] establish that
16 data bits will be transferred in 1 Data Cycle” (id. at ll. 44-47 (discussing
fast memory configured with parameters 42252255 – VII and VIII
parameters in bold.)).
Rambus attempts to support its single embodiment theory by quoting
Bennett which refers to “‘the preferred embodiment configuration
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Patent 6,324,120

6
envelope . . . [as] a 55255355 Versatile Bus configuration’” (Rambus 2nd
Reh’g Req. 2 (quoting Bennett at col. 38, ll. 48-50).) However, Figure 32
(42252255, col. 92, ll. 47); Figure 33 (43112244, col. 93, l. 58); and Figure
36 (4315355, col. 95, l. 49) all have different configurations as seen. (Also,
Figure 33 is not within Bennett’s (5, 5) “envelope.”) As indicated supra,
Rambus does not challenge the finding that the Figure 33 configured species
transfers an 8 bit block of data over one cycle as dictated by the VII and VIII
configuration parameters (4, 4) – thereby showing a different species as
compared to the Figure 32 single word species, which transfers a 16 bit
block of data over one cycle as dictated by the VII and VIII configuration
parameters (5, 5). (Compare Bennett Fig. 33 with Fig. 32; see also Bennett
Fig. 3; Hynix II at 1127; ‘1638 Dec. 19, n.9.) In other words, these two
figures show that Bennett satisfies the disputed claim term since a different
combination for the VII and VIII configuration parameters each constitute
“block size information [which] define[s] an amount of data to be output by
the memory device” as claim 26 requires.
As Micron similarly points out, Bennett discloses a myriad of
different configurations, and only a single configured embodiment is
required to anticipate. (See Micron 2nd Reh’g Comments 2-3.) But even if
the comparison is proper, the comparison must recognize that Figure 36
represents a special large memory case in Bennett which transfers multiple
16 bit words (two data words and two address words) over four successive
data cycles. (See ‘1638 Dec. at 19-20.) On the other hand, Figures 32 and
33 represent single word data transfers over a single data cycle. In each
separate species of Figures 32 and 36, each of which use some of the same
parameter values (i.e., 5, 5), the separately configured memory devices each
Appeal 2011-009664
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Patent 6,324,120

7
know what is being transferred. (See ‘1638 Dec. 16-20.) Hence, even
though Figure 36 transfers two 16 bit address words over two data cycles
followed by two 16 bit data words, the combination of the configuration
parameter VII and VIII values 5 and 5 in that embodiment, “dictates that the
indicated two sixteen bit addresses will be followed by the indicated two
sixteen bit data words.” (See Bennett, col. 96, ll. 25-29.) Bennett similarly
refers to Figure 36 as handling “a block of 4 sixteen bit data words.” (Col.
96, ll. 41-42.)3
In comparison, with respect to single word reads in general, Bennett’s
system transfers 1, 2, 4, 8, or 16 bit words over one data cycle based on
specific configuration parameter VII and VIII values, thereby specifying the
claimed block size as set forth in the claim for those single word
configurations – i.e., even if Figure 36 presents a special case or otherwise
does not satisfy claim 26. (See ‘1638 Dec. 19; Bennett, Fig. 3.)
Rambus also attempts to support its theory that Bennett proves a lack
of anticipation by quoting Bennett, inter alia, that the “‘seventh
configuration dimension is the format—the partionment in pins times cycles
as equals bits—of data words and is not the amount thereof.’” (See Rambus
2nd Reh’g Req. 4 (emphasis by Board, Rambus quoting Bennett at col. 17, ll.
29-31).) As explained in the ‘1638 decision and as Hynix II and the
Examiner recognize, the configuration parameters VII and VIII together

3 Bennett also refers to “32 bit words shown in Fig. 36.” (Col. 95, l. 59.)
Alternately calling the different groups 16 or 32 bit data (or address) words
or a group, etc. shows that the particular nomenclature is not important in
Bennett. (See Bennett, col. 90, ll. 50-58 (discussing “function” and “data”
interchangeably whether pure data, address information, or other operations
are transferred over the same multiplexed “data” lines).)
Appeal 2011-009664
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Patent 6,324,120

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dictate the amount of data in a word. Rambus’s quotation of Bennett about
the seventh configuration parameter does not show that the Board, which
relies on the combination of the two parameters, overlooks anything that
would otherwise disturb this finding. (See ‘1638 Bd. Dec. 18-20.) As noted
supra, the District Court agrees, “[i]ndisputably, parameters VII and VIII
specify the total amount of data that will be transferred in response to two
basic types of transaction requests.” Hynix II at 1139 (emphasis added).)
Rambus relies on a similar passage in Bennett’s column 17, i.e., that
“block data . . . [can] flow, on the Versatile Bus without . . . any requirement
for or relation to this seventh configuration dimension.” (Rambus 2nd Reh’g
Req. 4 (emphasis by Rambus, quoting Bennett at col. 17, ll. 24-29).)
Rambus also relies on a similar Bennett passage that states that the
“Versatile Bus knows naught . . . of . . . this information.” (Rambus 2nd
Reh’g Req. 4 (quoting Bennett at col. 96, ll. 38-41).) This latter passage
only refers to the special case in Figure 36 of multiple word transfers which
does require some “associated control” as discussed in the ‘1638 decision (at
20) and as discussed further below. (See Rambus 2nd Reh’g Req. 3
(discussing “associated control”).)
More importantly, the quoted passages only show that Bennett’s
“Versatile Bus knows naught . . . . [because t]he Versatile Bus is simply
handling data.” (Bennett, col. 96, ll. 40-41 (emphasis added).) On the other
hand, the Versatile Bus Interface (VBI) on each chip does know how much
data to transfer, and controls the operation based on the configuration; i.e.,
“‘the what (what operations), when (in what relationship and/or sequence)’.”
(See ‘1638 Bd. Dec. 14 (quoting Bennett at col. 39, ll. 31-34).) As an
example of this control based on the configured parameters and perhaps
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Patent 6,324,120

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other associated control, Bennett states that “[i]n FIG. 36 a Versatile Bus of
43153355 configuration has handled a block of 4 sixteen bit data words.”
(Bennett, col. 96, ll.40-42.)
Bennett makes clear that the VBI controls, and for example, with
respect to the large memory represented in Figure 36, “[t]he configuration
that four total cycles should be utilized requires naught but some associated
control between the Versatile Bus Interface Logic(s) and User(s).” (Bennett,
col. 96, ll. 33-36.) Even if claim 26 precludes such minimal (“naught”)
“associated control,” which it does not as discussed further below, in any
given memory device contemplated by Bennett wherein such minimal
control sets the total number of clock cycles for the block data transfer, the
specific Figure 36 configuration ultimately dictates both the word length and
time delay within that configured embodiment, thereby satisfying claim 26.
Viewed another way, the Figure 36 species may include different
subspecies each of which have different “associated control,” for example,
to specify 4 total clock cycles, 8 total clock cycles, etc., but within each
subspecies, the configuration parameters VII and VIII dictate the block size.
In essence, the associated control serves to define Figure 36 as a “large
memory” which handles multiple word data transfers and this control
renders it a separate species (or sub-species, etc.) as compared to the “fast
memory” single word data transfer of Figures 32.
Most importantly, this interpretation comports with the ‘120 patent.
In the ‘120 patent, skilled artisans must know which code of several “other
block size encoding schemes” will be used to determine the block size. (See
‘120 patent, col. 11, ll. 59-60.) Hence, the same pattern of bits can represent
different block sizes – depending on the encoding scheme. Also, in addition
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Patent 6,324,120

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to these other disclosed encoding schemes, even in the preferred
embodiment of the ‘120 patent, the same 3-bit pattern can represent two
different block sizes. (See ‘120 patent, col. 11, ll. 39-41 (different first bits
dictate the code for the remaining three bits).) In other words, without
knowing the particular encoding scheme or first code bit in the ‘120 patent,
skilled artisans could not determine the block size value. Each particular
encoding scheme defines a particular species or subspecies which governs
the block size. Similarly, even if the “associated control” in Bennett defines
a particular Figure 36 subspecies, Figure 36 still satisfies claim 26 because
the configuration parameters VII and VIII dictate the block size for each
subspecies.
Based on the foregoing discussion, Micron’s alternative BUSY signal
alternative theory of anticipation as regards the block size information is not
required to satisfy the claims. (See Rambus Reh’g Req. 5; ‘1638 Dec. 20-
21.) As such, the alternate finding of anticipation based on Bennett’s BUSY
signal is hereby withdrawn.
Rambus fails to show that the Board overlooked any material
arguments or evidence warranting affirmance of the Examiner’s decision not
to reject claim 26 based on Bennett. Rambus’s reliance on arguments
presented for claim 26 also fails to show an overlooked point regarding
claims 29 and 33.
REHEARING DECISION
We decline to modify the Decision affirming the Examiner’s decision
to reject claims 1-4, 6, 8-11, 15, 16, 19, and 21-25 and reversing the
Examiner’s decision to confirm claims 26, 29, and 33.

Appeal 2011-009664
Reexamination Control 95/000,178 & 95/001,152
Patent 6,324,120

11
DENIED

Counsel for Patent Owner:

Naveen Modi, Esq.
Finnegan, Henderson, Farabow,
Garrett & Dunner, LLP
901 New York Avenue, NW
Washington, DC 20001-4413

Counsel for Third Party Requester Samsung Electronics Co., Ltd.:

David L. McCombs, Esq.
Haynes and Boone, LLP
2323 Victory Avenue, Suite 700
Dallas, TX 75219

Counsel for Third Party Requester Micron Technology Inc.:

Tracy W. Druce
Novak Druce & Quigg, LLP
(NDQ Reexamination Group)
1000 Louisiana Street, 53rd Floor
Houston, TX 77002