Ex Parte 6260097 et al

Patent Trial and Appeal Board

Aug 29, 2014

95001134 (P.T.A.B. Aug. 29, 2014)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
95/001,134 01/09/2009 6260097 42940.4 8506
86497 7590 09/02/2014
Paul M. Anderson, PLLC
P.O. Box 160006
Austin, TX 78716
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
09/02/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

RAMBUS, INC.
Patent Owner, Appellant

v.

MICHELLE K. LEE, Deputy Director,
United States Patent and Trademark Office
____________

Appeal 2012-000171
Inter Partes Reexamination Control No. 95/001,134
United States Patent 6,260,097 B1
Technology Center 3900
____________

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN C. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON REMAND
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Reexamination Control 95/001,134
Patent 6,260,097 B1

STATEMENT OF THE CASE
The prior decision in this case returns to the Board as a remand from
the Federal Circuit. The Federal Circuit affirmed-in-part, vacated-in-part,
and remanded the Board’s prior decision, Rambus, Inc. v. NVIDIA Corp.,
App. No. 2012-000171 (BPAI 2012) in Rambus v. Rea, 731 F.3d 1248 (Fed.
Cir. 2013) (“Rambus-Rea”).
The initial proceeding arose out of a request by NVIDIA Corporation
for an inter partes reexamination of U.S. patent 6,260,097 B1 to Farmwald
et al., Method and Apparatus for Controlling A Synchronous Memory
Device (issued July 10, 2001, claiming priority to April 18, 1990) assigned
to Rambus.
Appellant, Patent Owner Rambus, appealed to the Board from the
Examiner’s decision in the Right of Appeal Notice (RAN) rejecting claims
1–5, 7, 8, 10–12, 14, 26, 28–32, 34 and 35. (App. Br. viii.) The Board
affirmed the Examiner’s decision rejecting these claims. Prior to the
Board’s decision, requester NVIDIA withdrew from the proceeding.
Thereafter, Rambus appealed the Board’s decision to the Federal
Circuit, and Rambus-Rea affirmed the Board’s anticipation holding that
Inagaki anticipates claims 1, 2, 7, 8, 10, and 14.
1
The Board also had held
that claims 1–5, 7, 8, 10–12, 14, 26, 28–32, 34 and 35 would have been
obvious based on the iAPX Manual,
2
the iAPX Specification,
3
and Inagaki.

1
Inagaki, JP 57-210495 (Dec. 24, 1982) (reference hereinafter is to an
English language translation of record) (attached as Exhibit 2 to NVIDIA’s
Respondent Brief).
2
iAPX Interconnect Architecture Reference Manual (Intel Corp.) (1982)
(attached as Exhibit 3 to NVIDIA’s Respondent Brief).
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Rambus-Rea vacated-in-part and remanded a portion of that obviousness
decision, “the Board’s decision that claims 3–5, 11, 12, 26, 28–32, and 35
are unpatentable,” because of procedural and other errors committed by the
Board in its prior decision. Rambus-Rea, 731 F.3d at 1258.
Rambus-Rea determined that the Board committed procedural error
because it “supplied its own reasons to combine iAPX and Inagaki,” thereby
depriving Rambus “of . . . due process rights.” Id. at 1256. Accordingly,
Rambus-Rea cited the Board’s procedure for instituting a new ground of
rejection. Id. (citing 37 C.F.R. § 41.77(b)). In response, this Decision
hereby is designated as a new ground of rejection to provide Rambus its due
process rights. This new Decision also addresses Rambus-Rea’s holding that
the “Board erroneously placed the burden on Rambus to prove that its claims
were not obvious,” id. at 1255, and that “the Board erred in its treatment of
objective evidence of nonobviousness,” id. at 1256.
4

On appeal to the Board and the Federal Circuit, Rambus’s arguments
were directed to the nonobviousness of claim 1. (See Bd. Dec. 29.) Rambus
did not present separate arguments for what are now the remanded claims,
claims 3–5, 11, 12, 26, 28, 32, and 35. Claims 1, 2, 7, 8, 10, and 14,

3
Electrical Specifications for iAPX 43204 Bus-Interface Unit (BIU) and
iAPX 43205 Memory Control Unit (MCU) (March 1983) (attached as
Exhibit 7 to NVIDIA’s Respondent Brief).
4
As to the former holding, the Board stated that “Rambus fail[ed] to present
evidence that skilled artisans would have been unable to modify” the iAPX
system. (See Bd. Dec. 23–24.) The Board made that and a similar statement
under the impression that Rambus had the burden to show error and to show
inoperability. Rambus-Rea held that these statements constitute legal error
for improperly shifting the burden to Rambus. Rambus-Rea, 731 F.3d at
1255. Therefore, the Board herein removes all such statements.
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anticipated by Inagaki as Rambus-Rea holds, would seem at first glance, by
inference from that holding, also to be unpatentable for obviousness over the
combination of iAPX and Inagaki. See In re Pearson, 494 F.2d 1399, 1402
(CCPA 1974) (“lack of novelty . . . is the ‘ultimate or epitome of
obviousness’”) (citation omitted); In re Fracalossi, 681 F.2d 792, 794
(CCPA 1982) (same). Rambus-Rea also did not remand claims 1, 2, 7, 8,
10, and 14 to determine the obviousness thereof. On the other hand, the
central thrust of Rambus-Rea is that the record does not establish the
obviousness of modifying the iAPX system by using Inagaki’s dual edge
clocking scheme.
Pursuant to the remand, the Board hereby addresses the Examiner’s
determination of obviousness of the remanded claims, claims that Rambus
does not argue have separate patentability from the anticipated claims,
including claim 1. (See RAN 52-133.) In this endeavor, in an attempt to
provide guidance and follow the guidance from Rambus-Rea, the Board
selects claim 3, which depends from claim 1, and independent claim 26, to
represent the claims on remand.
We adopt and incorporate by reference the findings by the Examiner
as to the obviousness rejection of claims 3–5, 11, 12, 26, 28, 32, and 35.
(See RAN 52–133.) We modify the Examiner’s findings in response to
concerns by Rambus-Rea about the Examiner’s reason for combining iAPX
and Inagaki. We also address the evidence cited by Rambus-Rea regarding
objective evidence of nonobviousness.
We have jurisdiction under 35 U.S.C. §§ 134(b) and 315.
We affirm the obviousness rejection of claims 3-5, 11, 12, 26, 28, 32,
and 35. This Decision constitutes a new ground of rejection.
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BACKGROUND
Rambus-Rea characterized Rambus’s invention as follows:
This case relates to memory circuits known as dynamic
random-access memory (DRAM). Conventional memory
circuits transfer all of the data upon request, asynchronously.
Each transfer can tie up the computer system for extended
periods of time and create a “bottleneck” that slows down
computer operations.
The ’097 patent solves this problem using a synchronous
memory system to transfer the data. In synchronous systems, a
clock signal that alternates between a digital value of 0 and 1
synchronizes the operations within the system. The change in
the clock signal from a 0 to a 1 is referred to as the “rising
edge” of the clock, and the change in the signal from a 1 to a 0
is referred to as the “falling edge” of the clock. Figure 14 of the
'097 patent, shown below, depicts an exemplary clock signal:

Rambus-Rea, 731 F.3d at 1250.
Rambus’s system and Inagaki’s system each transfer data on
the rising and falling edges of the clock, which is known in the art as
double data rate (DDR) transfer, because the data rate doubles by
using both clock edges, as compared to one edge, to trigger the data
transfer to and from a memory device, as explained more fully below.

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Claims 1–3 and 26, which essentially claim this DDR function,
follow:
1. A method of controlling a synchronous memory
device, wherein the memory device includes a plurality of
memory cells, the method of controlling the memory device
comprises:
issuing a write request to the memory device, wherein in
response to the write request, the memory device samples first
and second portions of data;
providing a first portion of data to the memory device
synchronously with respect to a rising edge transition of an
external clock signal; and
providing a second portion of data to the memory device
synchronously with respect to a falling edge transition of the
external clock signal.

2. The method of claim 1 wherein the write request
includes an operation code.

3. The method of claim 2 wherein the memory device
receives the operation code synchronously with respect to an
edge transition of the external clock signal.

26. A method of controlling a synchronous memory
device, wherein the memory device includes a plurality of
memory cells, the method of controlling the memory device
comprises:
providing first block size information to the memory
device, wherein the first block size information defines an
amount of data to be input by the memory device in response to
a write request;
issuing the write request to the memory device, wherein
the memory device samples the write request synchronously
with respect to an external clock and, in response to the write
request, the memory device samples first and second portions
of data;
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providing a first portion of data to the memory device
synchronously with respect to a rising edge transition of an
external clock signal; and
providing a second portion of data to the memory device
synchronously with respect to a falling edge transition of the
external clock signal.

ADDITIONAL FACTUAL FINDINGS
Rambus-Rea summarized other pertinent facts as follows:
The following facts regarding Inagaki and iAPX are not
in dispute. Inagaki discloses a memory system that transmits
one bit during each half-cycle of the external clock. . . . The
half-cycle system disclosed in Inagaki is a modification of a
conventional full-cycle system. . . . Inagaki achieves the half-
cycle functionality by generating two clock signals based on the
rising and falling edge of the external clock. . . . The two
internal clock signals, in turn, synchronize the transfer of data
during the two halves of the system clock cycle. . . .

The iAPX manual and specification disclose a system
that transfers data based on the rising or falling edges of two
system clocks. . . . The system, however, utilizes the full clock
cycle for each data transfer. . . . Thus, because the iAPX
system employs a full clock cycle to transfer data to the
memory device, the system cannot use both edges of the clock
signal to synchronize the transfer of data portions to memory.
However, Inagaki discloses a mechanism for converting a
conventional full-cycle system into a half-cycle system.
Rambus-Rea, 731 F.3d at 1251.
The Board’s factual findings follow and are letter-numbered, for later
reference in the Decision, as follows:
Inagaki
I1. Inagaki describes increasing data transfer rates in “block access
memory” devices: “the demand is increasing to have higher speeds even for
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MOS RAM.” (Inagaki 2.) As further background, Inagaki explains that
conventional methods to increase data transfer rates in RAMs [random
access memories] included increasing the “bit width (a multi-bit structure),”
which adds to the cost of packaging, by “increas[ing] the number of pins,” or
“increas[ing] the data transfer rate.” (Id.) Adding memory device pins
(which increases bus width) also prevents integration due to the increased
size. (Id.)
Inagaki’s solution doubles the data rate by using the rising and falling
edges of an external clock (i.e., without increasing the clock rate, data bus
width, or pin count): “The rise and fall of external clock φ are detected, and
clocks φ1 and φ2 are generated. Clocks φ1 and φ2 drive shift pulses of the
shift register. . . . In this way, since one bit is output on each half-cycle, the
operating speed is twice that of the conventional speed.” (Id. at 4.)
I2. Inagaki’s system performs “data input or output every half-cycle
based on an external clock.” (Id. at 2.)
I3. Inagaki improves upon conventional methods in terms of speed as
follows: “In order to overcome this problem, the present invention presents
block access memory that transfers data with a speed that is twice the
conventional speed, by performing I/O [input/output] of data on every half-
cycle of the external clock that drives the I/O shift register.” (Id. at 3.)

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iAPX Manual and the iAPX Specification
5

A1. Figure 1-2 of the iAPX Manual follows:

Figure 1-2 depicts a memory module comprising a memory storage
array and a MCU (Memory Control Unit).
In the memory module, “[t]he storage arrays will typically be
constructed with high-density dynamic RAM (DRAM) components.” The
MCU within that module requires a “modest amount of external logic . . . to
interface the MCU to the storage array RAMs - - for simple configurations,
as few as 12 external TTL packages are required.” (iAPX Man. 1-4.) As
Figure 1-2 shows, the system may include one or more memory modules.
The BIU (bus interface unit) works in conjunction with a GDP
(general data processor) in a processor module. (iAPX Man. 1-1 - 1-3;
Fig. 1-2.) “The BIU is also responsible for arbitrating the usage of the
memory bus.” (iAPX 1-3.) It also “decides which memory bus(es) will be
used to form the [memory bus] access.” (Id.)

5
According to Rambus, the iAPX Specification describes the same system
as the iAPX Manual. (App. Br. 26-27.) They are part and parcel of the
rejections at issue.
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A2. The memory module constitutes “a memory confinement area.”
(iAPX Manual 1-8, 3-2.) The MCU “interfaces memory storage arrays to
the memory bus.” (Id. at 1-4.)
A3. A component level constitutes the lowest level of hardware in the
system, an example of which is a RAM chip. A module comprises a group
of interconnected components. (Id. at 2-1.)
A4. The iAPX system allows for “Modular System Expansion.”
(iAPX Spec. INTRO-7.) The presence or absence of any module does not
prevent communication between any other modules. (iAPX Man. at 2-6.)
The system isolates errors within each confinement area. (Id.)
The “Modular System Expansion” involves “three degrees of freedom
when designing, and later, expanding, an iAPX 432 system: Fault
Tolerance, Resource, Performance.” (iAPX Spec. INTRO-7.)
The iAPX Specification provides the following diagram to illustrate
the flexibility that system designers may exploit:

(Id.) The diagram above indicates that minimal or no fault tolerance (which
includes some error correction), and virtually any number of memory
devices and processors, including one, may be employed: “The BIU and
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MCU allow the iAPX 432 hardare to modularly and transparently extend the
processing power (from 1 to 63 modules of processors or memories), bus
bandwidth (1 to 8 backplane buses), and fault-tolerant capablities of the
system.” (iAPX Man. 1-2.)
Several functions, including error correction functions, are optional:
“Functional Redundancy Checking (FRC) . . . is an optional mechanism.”
(Id. at 1-11.) Many other functions are deemed “optional capabilities.” A
“register holds a set of bits that enable many of the optional capabilities in
the MCU and BIU components.” (Id. at 10-1.) Examples of optional
functions to disable: “Disable SLAD Bus FRC Detection,” “Disable MACD
Bus FRC Detection,” and “Disable ECC Error Reporting.” (Id. at 10-2.)
Errors are “detected and localized to a confinement area. . . . and
reported to all of the modules in the system.” (Id. at 1-6.) Error reporting
occurs on buses that are separate from the data buses. (Id. at 1-11, 1-12.)
Errors are constrained to memory confinement areas (i.e., modules). (Id. at
1-6, 1-11, 1-12.) Normal data, address, and control information is “checked
by a pair of parity bits that are interlaced among the signals that they check.”
(Id. at 1-11.)

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A-5. A block diagram of a simple, single memory module, iAPX
system, appears below:

(iAPX Spec., BIU-17.) The figure shows the MACD Memory Bus, at issue
here, connected to the BIU and the memory module, which includes the
MCU (MACD interface) and the memory array, or DRAMs.
A-6. A diagram of the two clock (CLKA and CLKB) waveforms that
drive the MCU memory module and BIU above, appears next:

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(iAPX Spec., MCU-39.) As seen above, the two clocks differ in phase by
90 degrees. Each of these two clocks has rising and falling edges that
govern the timing of a variety of transactions of the multiple bus iAPX
system. (See, e.g., iAPX Spec., MCU-36, BIU-38 (listing the various
transactions timed to the falling and rising edges of the two clocks, CLKA,
CLB).)
For example, the MCU and the BIU output data onto the MACD
“Memory Bus” at rising CLKB edges. (iAPX Spec., MCU-13, MCU-36,
BIU-38.) Both devices, the MCU and the BIU, input data or other signals
from the MACD bus on rising CLKA edges. The BIU also drives and
receives data from the processor on the ACD bus. (See MCU-36; BIU-38.)

ANALYSIS
Pursuant to this remand, Rambus-Rea issued the following guidance:
“To be clear, we are not passing judgment on the merits of the Board's
findings regarding the motivation to combine.” Rambus-Rea, 731 F.3d at
1256. “We express no opinion . . . as to whether . . . claims [3–5, 11, 12, 36
and 28-32] should issue.” Id. at 1258. “[T]he Board’s findings may
ultimately be correct . . . .” Id. at 1256.
Single Chip Argument
Rambus’s Appeal Brief before the PTO argues that the iAPX memory
module is not a “memory device.” The prior decision addresses this
argument. (See Bd. Dec. 15–21.) Rambus argued that the iAPX module is
not a “memory device,” because it is not a single chip. (See id.) Rambus
pointed to its preferred memory device, a single chip DRAM (dynamic
random access memory). Subsequent to the filing of Rambus’s Appeal Brief
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and Rebuttal Brief, in another case, the Federal Circuit decided against
Rambus regarding the same claim term, the “memory device,” which is
recited in a related patent to Rambus.
6
In re Rambus Inc., 694 F.3d 42 (Fed.
Cir. 2012). In that case, the court held that the claimed “synchronous
memory device” is not limited to a single chip, and that the same iAPX
Manual at issue here anticipated the sole claim at issue there. See id.
(affirming the Board’s decision in BPAI 2011-011178, Reexamination
Control No. 90/010,420). Rambus’s arguments essentially reduced to the
single chip argument dismissed by In re Rambus as incorrect based on
similar arguments, evidence, and prosecution history. (See Rambus Appeal
Brief 2–16.) Rambus did not pursue this argument before the Federal
Circuit.
It is not clear if Rambus will attempt to pursue the argument on
remand. If so, addressing how the iAPX memory module constitutes a
memory device of claims 1, 3, and 26, the Examiner previously found that

6
In addition to the reexamination involved in In re Rambus, Rambus raises
the same “single chip” issue in at least two other related appeals before the
Board (App. No. 2011-008431, App. No. 2011-009664). The patents
involved in In re Rambus and these Board appeals claim continuity back to
the same application (App. No. 07/510,898) as the ’097 patent under
reexamination and appear to have the same or substantially the same
disclosures. The relevant findings and reasoning from those related appeal
decisions address Rambus’s similar arguments including, inter alia,
prosecution history, District Court findings, expert opinion and other such
“memory device” interpretation arguments, and are adopted and
incorporated by reference here. See Gemalto S.A. v. HTC Corp., 2014 WL
2766195, ---F.3d---- (Fed. Cir. June 19, 2014) (No. 2013-1397) (applying
same claim construction to patents deriving from common application).

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the iAPX BIU (bus interface unit) sends data packets, which include a write
request, to the MCU (memory control unit), the recited memory device.
(See, e.g., RAN 53-55; A1 (showing the GDP and BIU to be part of a
processor module).) Similar to the findings in In re Rambus, the Examiner
here found the MCU to be a synchronous interface to memory arrays in the
memory module; therefore, the iAPX memory module constitutes the
memory device recited in claims 1, 3 and 26. (See RAN 53-54.) The
Examiner also found data to be sent synchronously with respect to rising
clock edges. (Id.) The iAPX BIU, in a fashion similar to the ’097 patent’s
memory controller or master, may aid in making other memory bus access
decisions. (Compare A1 with ’097 patent col. 12, ll. 55-58.)
Considering the holding of In re Rambus, which controls the “single
chip” issue, and in light of the Examiner’s independent findings and findings
in our prior decision here, Rambus does not show error in the Examiner’s
finding that the iAPX memory module constitutes a memory device as
recited in the claims.
Combining iAPX and Inagaki
As Rambus-Rea and our prior decision discusses, the Examiner relies
on Inagaki to suggest modifying the iAPX system to include providing first
and second data portions on rising and falling clock edges, often referred to
as DDR (double data rate). (See RAN 55-57.) As noted, as In re Rambus
decided, the “synchronous memory device” recited in claim 18 there reads
on the iAPX memory module. The iAPX memory module includes a
memory control unit (MCU) and numerous DRAM chips. (See supra A1-
A3 (factual findings from the iAPX Manual).)
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The Examiner makes specific findings regarding the obviousness of
representative claims 3 and 26, and the other remanded claims. (See
RAN 52–133.) As to claim 3, the Examiner finds that the iAPX system
sends an operation code synchronously, relying on operation code bits of a
message packet sent over the MACD bus to the memory device’s MCU.
(See RAN 57–58.) With respect to claim 26, the Examiner finds that iAPX
discloses a BIU that controls the memory module on the MACD BUS,
sending, for example, bits 8-11 as block size information. (See RAN 75–
76.) Rambus does not challenge these findings with specificity, which the
record supports. Further, In re Rambus holds that the iAPX Manual
anticipates a similar (albeit non-DDR) claim with a “block size information”
limitation: Anticipated claim 18 in related Rambus patent, U.S. Patent No.
6,034,918, recites “[a] method of operation of a synchronous memory device
. . . outputting the first amount of data corresponding to the first block size
information.” In re Rambus, 694 F.3d at 43.
In its Federal Circuit brief in this case, Rambus does not focus on the
operation code and block size information recited in claims 3 and 26. Rather,
Rambus maintains that the iAPX system is too complicated to modify as
suggested––sampling data on falling and rising clock edges (i.e., using
DDR), i.e., arguing the nonobviousness of anticipated claim 1. Rambus
reasons that “iAPX discloses using the rising and falling edges of both of its
clock signals for purposes other than double data rate (only one edge of one
clock signal is used for data transfer.)” (Fed. App. Br. 33.)
Rambus notes that the iAPX system uses two clocks, CLKA and CLKB.
Rambus argues that “[s]everal pieces of information are carried on both edges
of both clocks, including “buffer directional control.” (Fed. App. Br. 34
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(emphasis added).) According to Rambus, this buffer control renders “both
edges of both clocks . . . necessary for the operation of the iAPX, [and] they
cannot be used to add a double data rate for data transfer.” (Fed. App. Br. 34.)
The record does not support Rambus’s argument, factually or otherwise.
Contrary to Rambus’s argument, clock edges do not “carr[y]” any information.
Rather, the clock edges trigger actions or data transfers that carry information.
The iAPX Manual explicitly shows that a clock edge triggers more than one
action on multiple buses. For example, the rising edge of CLKA triggers
several different inputs to and outputs from different pins on the MCU
(memory control unit in the memory module): MACD15, CTL2, CHK1,
MBOUT, INIT, ABCHK. (See iAPX Spec., MCU-36, A-6.) The clocks also
trigger multiple actions in the BIU and on different buses. (See BIU-38 (ACD
and MACD bus).) The Examiner similarly finds that the iAPX Manual
describes that the system, including the MCU, is “kept in ‘lock step’ by
operating with respect to a transition (‘a clock edge’) of an external clock.”
(RAN 58 (citing iAPX Man. at 4-15).)
Rambus also argues that if both rising and falling edges of CLKB were
modified to be used for data transfer, the MCU would not be able to
reconfigure its actions from reading data to writing data or “vice versa.” (Fed.
Br. 34.) According to Rambus, “‘buffer directional control’ occurs between
data transfers and is used to configure the memory control unit to either receive
data or output data.” (Id.)
Again, the record does not support this argument. Contrary to the
argument, the CLKA edge does not control the data direction, it merely acts as
a trigger to control the timing thereof, as noted above. As Mr. Murphy states,
the clocks “manage information transfer.” (See Supp. Murphy Decl. ¶ 23.)
The iAPX Specification discloses that an “MBOUT signal controls the
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direction of external buffers for the MACD, CHK, and CTL signals. When
MBOUT is asserted, it indicates that external buffers must be directed to carry
information outbound from the component [i.e., the BIU or MCU] to the
memory bus.” (iAPX Spec., BIU-5; see also BIU-17.) The phrase “when
MBOUT is asserted” shows that it is not asserted at every CLKA signal,
contrary to Mr. Murphy’s and Rambus’s implications. Logically, as iAPX
discloses, “MBOUT remains asserted” when data flows in one direction, such
as a write for “two double-bytes.” (iAPX Spec., BIU-19; see also BIU-16
(MBOUT asserted in cycle 5 in a 4Byte Memory Read).)
The Examiner similarly finds that an operation code “instructs the
memory device to input the amount of data . . . from the MACD bus.” (RAN
53.) The Examiner finds, with respect to claim 4, which is similar to claim 26,
that the “LLLL field indicates the number of bytes of memory data to be
transferred by a memory device.” (RAN 58.) The Examiner similarly finds
that the MCU accepts variable length data requests. (RAN 66 (citing iAPX
Man. at 1-4).) Each CLKA does not trigger a different direction between data
blocks that have variable lengths to be input to the MCU, because that long
block flows in one direction without an unnecessary direction signal between
each piece (byte) of the block. As indicated, the CLKA signal merely triggers
the timing of the MBOUT signal, which controls the data direction.
Mr. Murphy does not contradict these findings persuasively or even
discuss MBOUT. Discussing buffer control, Mr. Murphy relies on Budde.
(See Supp. Murphy Decl. ¶¶ 23–24.) Budde (assignee Intel Corporation), the
iAPX Manual, and the Specification (Intel’s product manual and specification),
involve the same flexible system (see A4), albeit, implemented differently
pursuant to this flexibility, as discussed further below. In any event, as
Mr. Murphy indicates, the Examiner finds that buffer directional control is
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responsive to a CLKA edge. (See id.) The Examiner finds that buffer control
triggered by CLKA would not render the system inoperable if both edges of
CLKB were employed to transfer data. (See ACP, 61-62 (Feb. 19, 2010).)
Mr. Murphy cites Budde to show that “buffer directional control is altered with
CLKA rising.” (See Supp. Murphy Decl. ¶¶ 23–24.) According to Mr.
Murphy, “Budde provides for buffer direction control between each data
transfer.” (Id. at ¶¶ 23–24 (emphasis added).)
Mr. Murphy, however, does not contend that the data direction must
change or even does change during each block data transfer, or even between
each rising CLKB signal. (See A7.) “[P]rovid[ing] for” directional control at
each rising CLKA edge, if Rambus contends that must occur at each CLKB
cycle, contradicts its other argument, discussed below, that data must be held
for a full CLKB cycle. In any case, MBOUT simply directs a component’s
buffer to change the data transfer direction at a CLKA edge when the system
user desires such a change (i.e., a read or write command). Using the MBOUT
signal, variable length data may be sent in one direction on the MACD bus on
successive CLKB pulses without corrupting the data flow. This would occur
logically, as explained above, without requiring each CLKA pulse to trigger a
change between successive data bytes of a block data transfer. (See MCU-5,
27, 36, BUI-5, 17.)
Moreover, a block data direction signal triggered by any clock is so
trivial that Inagaki does not discuss it. As the Examiner finds, Inagaki provides
read/writes for a block data memory device at twice the conventional speed,
suggesting the modification in iAPX. (See RAN 55–56; RAN 90; I1-I3.)
Inagaki constitutes evidence that a data direction signal logically is not required
to be sent at each between rising or falling clock edge, and suggests the same
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for a simple or more complicated, but flexible, iAPX system (A4, i.e., one
module/device).
The evidence shows that eliminating some functions in iAPX to create
a simpler iAPX 432 system, if that is necessary to support the rejection,
would have been obvious. The iAPX Specification specifically notes that it
offers “expansion flexibility” and “three degrees of freedom when
designing, and later, expanding, an iAPX 432 system: Fault Tolerance,
Resource, Performance.” (iAPX Spec., INTRO-7; accord A4.) Many
functions are optional and can be disabled, especially in a single module
system. (See A4.) In any event, no functions need to be eliminated under
one proposed modification that employs both iAPX clocks, especially in
simple single module systems contemplated by iAPX and disclosed by
Inagaki. (Although, as noted further below, there is nothing to arbitrate and
no error reporting when there is only one memory module.) Alternatively,
Inagaki teaches, and iAPX at least suggests, that all the iAPX functions need
not transpire in a simple single memory module using one clock. (See A4.)
For example, the iAPX Specification provides the following diagram
to show the flexibility in the system:

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(Id.) The diagram shows that fault tolerance can be zero or high, as
required. Flexibility specifically includes one memory module: “The BIU
and MCU allow the iAPX 432 hardware to modularly and transparently
extend the processing power (from 1 to 63 modules of processors or
memories, bus bandwidth (1 to 8 backplane buses), and fault-tolerant
capablities of the system.” ( iAPX Manual, 1-2; accord A1, A4.)
Therefore, the record shows that the iAPX system can be modified
essentially to be as simple as Inagaki’s system––with a single memory
module and BIU/processor and a single backplane bus between the BIU and
MCU (i.e., the MACD bus, see A5). As the chart and disclosures imply or
suggest, all functions are not necessary. For example, the iAPX system
implies or suggests that arbitration between modules or error messaging
between modules does not transpire with one only one module in the system.
(See A4.) For example, the BIU “arbitrate[s] the usage of the memory bus.”
(iAPX Man. 1-3.) In one example, two processors/BIUs arbitrate for the
same memory module. (iAPX Spec., BIU-36.) This implies, logically, that
one processor/BIU need not arbitrate for MACD memory bus usage with a
single memory module. Simply, there is nothing to arbitrate for a single
processor and single module.
Similarly, a single memory module system does not report an error to
other nonexistent modules. (See A4.) As another example, multiple access
read or writes, with interleaving, would not be required for a single module.
(See iAPX Spec., BIU-25 (showing two modules for multiple access).)
Inagaki does not employ or discuss, arbitration, multiple access, and error
checking or reporting in its simple system, further showing that system
designers knew these functions were unneeded in simple systems. The
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claims do not require any of these functions. (Even if an iAPX designer
desires some error correction in a flexible single module APX system, iAPX
provides for that as part of the normal data flow pursuant to the normal clock
edges: normal data, address, and control information are “checked by a pair
of parity bits that are interlaced among the signals that they check.” (iAPX,
1-11.))
Rambus also maintains that using Inagaki’s clocking scheme in the
iAPX system would not have been obvious because Inagaki uses shift
registers, and the iAPX system uses dual edges of two clocks for other
specific functions. (App. Br. 21-26.) All of Rambus’s arguments reduce to
the unpersuasive assertion that the two systems must be bodily incorporated.
See In re Seed, 710 F.2d 1544, 1550 (Fed. Cir. 1983) (“[I]t is not necessary
that the inventions of the references be physically combinable to render
obvious the invention under review.”); In re Nievelt, 482 F.2d 965, 968
(CCPA 1973) (“Combining the teachings of references does not involve an
ability to combine their specific structures”).
Skilled artisans would have recognized that Inagaki teaches that data
bus systems, like that of iAPX, can push data on a bus by using the rising
and falling edges of a clock (i.e., DDR) to trigger sampling the data at twice
the normal speed. (See I1-I3.) Rambus’s allegation that Inagaki’s shift
registers render unobvious using dual edge clocks in the iAPX system for
data transfer to the MCU, ignores the agreed-upon fact that the iAPX system
already employs dual clock edges to control multiple buses. Therefore,
contrary to Rambus’s assertions, skilled artisans would have understood how
to implement the known feature of using both clock edges on data transfers
to maximize speed, whether shift registers were employed or not. As
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NVIDIA persuasively reasoned prior to withdrawing: “the fact that iAPX
already uses both rising and falling edges of the clock” for other purposes
“means that iAPX already has the circuitry available to send/receive data on
both edges” without a shift register. (See NVIDIA Resp. Br. 12.) In other
words, iAPX discloses that shift registers are not required, contrary to
Rambus’s unsupported arguments.
Further, Inagaki provides a good reason to modify a system to use
both clock edges: As the Examiner finds, Inagaki’s system “provides
read/write data at twice the rate of the external clock.” (RAN 68.) As the
Examiner also persuasively reasons, “‘if a technique has been used to
improve one device, and a person of ordinary skill would recognize that it
would improve similar devices in the same way, using the technique is
obvious unless its application is beyond his or her skill.’” (Id. (quoting KSR
Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007) (citation omitted).) The
record shows that using the technique is not beyond the skill level involved
here.
Inagaki’s teachings, and the iAPX use of dual edges, evidence a
reasonable expectation of success in using dual clock edges on data for
increased speed. Increased speed and compactness by reducing bus width
and corresponding pin number while saving cost, as Inagaki specifically
teaches (see I1) constitute universal motivators. Dystar Textilfarben GmBH
& Co. Dutschland KG v. C.H. Patrick Co., 464 F.3d 1356, 1368 (Fed. Cir.
2006) (“[A]n implicit motivation to combine exists … when the
‘improvement’ is technology-independent and the combination of references
results in a product or process that is more desirable, for example because it
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is stronger, cheaper, cleaner, faster, lighter, smaller, more durable, or more
efficient.”)
Despite Rambus’s related arguments that the proposed modification
would have rendered the iAPX system nonfunctional (see App. Br. 23-25),
the Court also recognized that “the interaction of multiple components
means that changing one component often requires the others to be modified
as well.” KSR, 550 U.S. at 424. In other words, as KSR implies, making
other required modifications to increase the data speed by using both clock
edges, as Inagaki teaches (I1-I3), does not defeat obviousness or show
inoperability.
Nevertheless, according to Rambus, “[c]omplex systems like iAPX’s
cannot have significant features replaced by other features.” (Rambus Reb.
Br. 11.) Skilled artisans, with the ability to exploit the flexibility in the
iAPX system, could have made it a simple single module system, with a
single backplane bus, as a standard option. (See A4; I1-I3.) Rambus’s
evidence also shows that skilled artisans knew how to modify the use of both
clocks in iAPX system. For example, Mr. Murphy testifies that Budde
employs the iAPX system, and that in Budde, “MACD[15:0] is driven and
sampled with CLKB rising.” (Murphy Decl. ¶ 127; accord Budde, col. 7, ll.
16–17.) On the other hand, the iAPX Specification shows that, unlike in
Budde, the iAPX MACD data bus is sampled (by the MCU and BIU) on
rising CLKA edges, and like Budde, driven with CLKB rising (driven by the
MCU and BIU). (See iAPX Spec. MCU-36, BIU-38).
7
The iAPX system is

7
Rambus agrees that the iAPX system functions as noted: “The data is
output on the MACD bus based on the rising edge of CLKB and sampled
based on the rising edge of CLKA.” (Reb. Br. 12; accord A7.)
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designed to be altered (A4), and Budde shows designers exploited that
flexibility and altered the clocking scheme.
In addition to these designer implemented changes to the clock
system, according to the iAPX Specification, the system allows designers to
vary the clock pulse width and the clock cycle time across a wide range.
(See iAPX Spec., BIU 40.) The record, including the iAPX Manual,
Inagaki, and articles cited by Rambus, shows that artisans in the field of
memory systems were skilled at a relatively high level in the field of
memory systems and devices. Mr. Murphy testifies that a skilled artisan
would have had a BSEE degree and 3-5 years of experience in designing
memory circuits Rambus such as DRAMs. (Murphy Decl. ¶ 4.)
Rambus essentially argues that such ordinarily skilled artisans could
not have simplified or altered the iAPX system that was designed to be
altered and flexible. Budde and the iAPX Manual contradict this argument.
The flexibility provides for reducing the number of modules to one memory
module (out of 63), as noted. (See A-4; iAPX Manual 1-2 (“A system with
one processor and one memory may be built with a single memory bus.”).)
Reducing the number to one memory module on a single memory bus
eliminates the need to arbitrate and report errors between modules, as iAPX
and Inagaki each suggest, as discussed above. (See A4.)
Moreover, Mr. Murphy admits that the iAPX designers “knew they
could use both edges of a clock signal–but chose not to,” but maintains this
knowledge shows a teaching away from “the [modification] proposed by the
Office.” (Murphy Supp. ¶ 23 (emphasis added).) This statement contradicts

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Rambus’s argument that the use of DDR would create a nonfunctional
device. Skilled artisans knew how to send data on both clock edges (i.e.,
employ DDR), as Inagaki proves and Mr. Murphy verifies.
Contrary to Mr. Murphy’s unsupported legal conclusion, a decision
not to do something is not a teaching away. Skilled artisans also would have
recognized that iAPX does not need two clocks, or all of its disclosed
options, or other functions, to operate, as Inagaki teaches. The two iAPX
clocks provide for expansion of multiple device systems with further
flexibility for fault tolerance and multiple buses, further suggesting no need
for two clocks in a single module system. (See A4.) See In re Sovish, 769
F.2d 738, 743 (Fed. Cir. 1985) (“This argument presumes stupidity rather
than skill.”); In re Kuhle 526 F.2d 553, 555 (CCPA 1975) (deleting a prior
art “switch member (and other elements) . . . thereby deleting their function,
was an obvious expedient.”); In re Larson, 340 F.2d 965, 969 (CCPA 1965)
(obvious to eliminate “a great deal of additional framework,” including an
additional axle, which “serve[] a particular purpose in that it increases the
cargo carrying capacity,” if the structure and its function are not desired.)
A single clock for a single memory module, as Inagaki teaches, would
create a “cleaner” iAPX memory device for handling data transfers at twice
the speed of the clock. Making a device “cleaner” (i.e., simpler) constitutes
a universal motivator under Dystar. Inagaki teaches that memory devices
function without arbitration, error correction, or two external clocks, and the
iAPX system similarly teaches simple and flexible single memory device
systems that do not require all disclosed error correction reporting and other
functions.
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Broad claims 3 or 26 do not have significant interrelated features
other than those required to sample or transfer data. The obviousness
inquiry must focus on the claim breadth. Given the claim breadth, skilled
artisans could have modified the iAPX system in view of Inagaki’s clocking
scheme. Some of the functions either could have been dropped, or triggered
on a different clock edge and retained, because each edge can govern more
than one control signal, as explained above and further below. (See iAPX
Spec., BIU-38, MCU-36, listing multiple actions triggered by the two clock
edges of CLKA and CLKB.)
Despite Rambus’s arguments about existing device limitations based
on speed (see Rambus App. Br. 25-26 (discussing 10 MHz operation)),
faster memory devices than those disclosed in the iAPX system would have
been available at the time of the invention, in 1990. Also, this argument
does not acknowledge that the iAPX system already handles the speed of
using both clock edges of CLKA and CLKB for various timing functions.
Therefore, Rambus’s argument tends to bolster obviousness, because as
Inagaki suggests, any data rate, including the iAPX data rate, doubles
without increasing the (10MHz) clock speed, simply by using both CLKB
(or CLKA) edges to transfer data.
Under a simple clock triggering alternative, even if somehow, the
iAPX MCU could not have handled both CLKB edges for data transfers, the
iAPX system could have benefitted, at the time of the invention, from a
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slower external clock’s trigger for the existing clock timing, as Inagaki and
iAPX suggest. (See I1-I3; BIU-41.)
8

Setting aside this simple triggering alternative, Rambus argues, as
another part of its nonfunctional allegation, that the iAPX system requires
holding BIU data on the MACD bus over successive rising edges of CLKB,
thereby precluding data transfers on the falling edge between the two rising
edges. (See Rambus Reb. Br. 11-12 (newly citing and modifying BIU-43 as
evidence to the Board, without presentation of it to the Examiner); see
A1710, similar slide presented by Rambus to Federal Circuit.) Rambus
reasons that the parameter tcd specifies how long it takes MACD data “to

8
In addition to using clock edges for multiple functions, skilled artisans
would have recognized that the iAPX system could have been modified to
include an external slower Inagaki clock as a trigger for the faster CLKA
and/or CLKB –thereby retaining all existing APX functions. That is,
Inagaki (see Fig. 4) teaches that fast clocks can be implemented by using the
dual edges of a slower external clock as triggers. In Inagaki, as the
Examiner recognizes, a slower external clock φ has rising and falling edges
corresponding to and triggering faster clocks φ1 and φ2, suggesting a similar
external clock to trigger the iAPX CLKA or CLKB. (See e.g. Inagaki Fig. 4;
I3, I4; RAN 37.) Inagaki and iAPX similarly employ multiple clocks,
suggesting such a combination. The slower external clock’s rising and
falling edges would trigger the existing CLKA and CLKB, with the external
clock’s rising and falling edges corresponding to the existing rising edges of
faster CLKB and/or CLKA, and the latter clocks retaining all functions. The
iAPX Specification heuristically illustrates this concept (which Inagaki
teaches as noted) by showing a slower “INIT” clock trigger signal with
falling and rising edges corresponding to the faster CLKA rising edges. (See
BIU-41.) The ’097 patent similarly discloses using internal clock
complements being created or triggered by external bus clocks. (See Fig.
13; App. Br. 4, 25-26 (describing the ’097 patent’s internal “device” 500
MHz clocks as triggered by dual edges of an external “bus” 250MHz
clock).)

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actually show up” after a rising CLKB edge. (See Reb. Br. 12.) Rambus
also argues that the parameter tdh shows how long past the next rising
CLKB edge that same data must be held on the bus “to ensure proper
reception by the receiving device.” (Id.) Rambus, or its expert, do not
specify what causes these alleged constraints. These arguments amount to
attorney conjecture and lack record support.
Rambus states that tdh specifies “how long the bus interface unit is
required to hold the data.” (Reb. Br. 12.) Rambus fails to direct attention to
where the iAPX Specification specifies that tdh has anything to do with the
BIU or its “proper reception.” The iAPX Specification does not specify that
the BIU is constrained by that parameter. Even if it did, the relevant device,
the MCU, samples the MACD data “based on the rising edge of CLKA,” as
Rambus acknowledges on the same page. (Reb. Br. 12; iAPX Spec., MCU-
36.) Rambus makes the unsupported logical leap that somehow the MCU
and BIU must hold the data for the same amount of time. (See Reb. Br. 12.)
The record does not support Rambus’s conjectural argument. Rambus
conflates different delay times for different devices and different data on
different buses, without support.
9

9
Short electrical lengths minimize the capacitance that naturally occurs
between longer conductors, which impacts rise times and speed, as an
ordinarily skilled engineer would have known. See BIU-40 (specifying
capacitance and varying frequency/speed at specific rise and other times).
Rambus was not the first to recognize a relationship between bus lengths,
capacitance, rise times, and speed. See, e.g., Bennett, U.S. 4,500,988, col. 6,
ll. 2–10 (1985) (specified capacitance of transmission line renders a
propagation speed of 5.72 nsec per meter) (incorporated by reference in
Bennett, U.S. 4,734,909, col. 12, ll. 6–10, or record). At the relatively low
frequencies of iAPX, transmission length would not have been a concern––
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Rambus’s data holding constraint arguments are not supported for
other reasons (i.e., besides the fact that delays, etc. on short bus lines
implicit in a single module system would be insignificant, as Inagaki
implies, see also note 9). The arguments also rely on an alleged depiction of
MACD data held over successive CLKB edges. (See Reb. Br. 11, citing and
annotating BIU-43.) The relied-upon figure ambiguously refers to “ACD
DATA” or other “3-STATE or PREVIOUS DATA” on the timing diagram,
with “MACD” listed to the left of the diagram. (See iAPX Spec., BIU-43.)
Rambus maintains that the “ACD DATA” in the timing diagram (see BIU-
43) actually should be “MACD DATA,” implying that the page includes a
typographical error. (See Rambus Reb. Br. 11.) The MACD and ACD
buses are distinctly different, and in any event, Rambus’s explanation
addressed above conflates or confuses ACD data with MACD data. (A5;
BIU-20.) The record does not support Rambus’s position, which relies on
an alleged typographical error and conflates ACD and MACD parameters or
data.
10

clock cycles (100 nsec) are long compared to transmission delays on a bus
and clock line (e.g., 5.72 nsec per meter in Bennett’s system). In any event,
one module and one processer, as iAPX discloses, obviously can be on a
very short bus. As capacitance (bus length) decreases, so do rise and fall
times, as an ordinary electrical engineer would have known. See, e.g., id.;
W.H. Hayt, Jr. & J.E. Kemmerly, Engineering Circuit Analysis 154–157
(1971) (discussing RC time constant and rise times) (Appendix).
10
As noted, Rambus did not present this data holding argument to the
Examiner, and complained to the Federal Circuit that the Board supplied its
own reasons in addressing Rambus’s new Rebuttal Brief arguments. (See
Fed. App. Br. 39 (“the Examiner never made any such findings” and
implying Mr. Murphy supports its new argument); Bd. Dec. 25-26 (noting
Rambus’s “untimely arguments” (citing Reb. Br. at 11-12).)
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Other record facts shows that MACD data does not need to be held,
and is not held, over two CLKB rising edges. First, essentially, if it is so
held, the system would not transfer data at 10 MHz, which Rambus agrees is
the disclosed iAPX preferred data rate. (See App. Br. 25 (arguing that the
iAPX cannot “support data transfers at 20MHz instead of the 10 MHz rate
for which the system is designed”).) Second, Rambus agrees that the MCU
and the BIU capture (sample) MACD data on the rising edge of the CLKA
cycle. That sampling occurs between rising CLKB edges––i.e., before a full
CLKB cycle transpires. (See MCU-36; BIU-38; BIU-43; Reb. Br. 9.)
Stated differently, the BIU writes data to the MCU on the MACD bus
during rising CLKB edges, and the MCU samples the data on rising CLKA
edges. (See A5-A7; App. Br. 23.) This implies that the MCU samples
MACD data before the full CLKB cycle transpires (i.e., on the rising CLKA
edge in the middle of the CLKB cycle). This comports with the record,
because the system puts different data, for long words, for example, on the
MACD bus on CLKB successive rising edges. (See iAPX Spec., BIU-21, BIU-
38, MCU-36, MCU-17–MCU-23 (showing different bytes per clock cycle),
iAPX Man. 1–5 (variable length data of 1–16 bytes); RAN 59.)
11
Hence,
whatever the relied-upon figure shows (iAPX Spec., BIU-43), the iAPX
Specification, in its entirety, shows that the MACD bus does not hold data for
the entire CLKB cycle. The MCU samples the data at the intervening rising

11
In related case PTAB 2012-001976, Rambus essentially agreed with this
analysis: “Specifically, the BIU outputs data onto the MACD bus based on the
rising edge of CLKB, inputs data from the MACD bus based on the rising edge
of CLKA, outputs data on the ACD bus based on the falling edge of CLKB, and
inputs data on the ACD bus based on the rising edge of CLKB.” (Rambus
Reb. Br. 3 (emphasis added).)
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CLKA edge, allowing more data (in a long word, for example) to be output on
the MACD bus on the next rising CLKB edge. (See, e.g., iAPX 1-5 (variable
length words); MCU-17 (showing bytes 1100 and 3322 on successive clock
cycles 7 and 8); MCU-17–MCU-23.)12
Holding data over two CLKB edges, as Rambus argues, and then
sampling on the next rising CLKA edge, would significantly increase the data
transfer time over 100nsec (10 MHz). In other words, Rambus’s arguments,
carried to their logical conclusion, imply that the data must be held not just for
1 clock cycle, but for 1.75 clock cycles––i.e., until the next CLKA rising edge
required to sample that data––which occurs ¾ cycles after the rising CLKB
edge. (See iAPX Spec., BIU-41.) Rambus’s arguments, if correct, would result
in a 175 nsec or 5.7 MHz (1/(175 x 10-9) data rate, instead of 100 nsec or a 10
MHz (1/(100 x 10-9) rate implied by the clock rate, and stated by Rambus to be
the data rate. (See iAPX Spec. BIU-40 (relating cycle time of 100nsec to
10MHz, its inverse); App. Br. 25 (specifying iAPX data rate of 10 MHz).)
Logically then, the relied-upon figure simply does not demarcate when
new (long-word) data is placed on the MACD bus at each rising CLKB edge.
(See iAPX Spec. BIU–43). Rambus’s allegations are unsupported and
contradict the iAPX disclosure for the reasons discussed. The iAPX system
outputs and samples bytes on the MACD bus during each CLKB cycle,
allowing another byte to be output and sampled in the next cycle (at least for
long words), at a rate of 10 MHz, which Rambus agrees is the iAPX data rate,
instead of 5.7 MHz, which would be the resultant rate according to Rambus’s

12
At least some of the figures involve “functional diagrams” that depict
CLKA for purposes of explanation, and iAPX explains that “[t]he MCU
actually sources MACD information on the rising edge of CLKB.” (iAPX
Spec., MCU-13.)
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unsupported argument. (See, e.g., iAPX Spec., MCU-17, 20, 21(different bytes
for reads and writes in successive clock cycles); BIU-40.)
Even if Rambus’s attorney arguments show a constraint, Inagaki
provides a reason for accommodating a modification of outputting data on both
rising and falling CLKB edges––to increase data transfer speed without using a
faster clock––by using both edges of an existing clock. The iAPX clock pulse
widths (t1, t2, t3, t4), delay times, rise times and other times may vary,
implying that any alleged fixed data hold times vary or may be accommodated
by ordinarily skilled memory designers. (See iAPX Spec., BIU-40; note 9.)
Rambus also argues that the Examiner erred by reasoning that both
CLKB edges could have been modified to trigger other actions, because,
according to Rambus, that reasoning is based on the Examiner’s erroneous
finding that a CLKB rising edge is not used for anything specific. (App. Br.
23.) Mr. Murphy declares that the clock edges “are already being used for
something specific, and thus, the system cannot simply be altered to use both
edges for data transfer . . . without rendering the system inoperable for its
intended purpose.” (Murphy Supp. Decl. ¶ 24.) Setting aside the premise,
Budde and iAPX contradict Mr. Murphy’s conclusion of inoperability,
because the two disclosures show that the clock edges can be used
differently. Mr. Murphy further contradicts that conclusion by also stating
system designers “knew that they could use both edges of a clock signal but
chose not to.” Id.
All the clock edges are used for something specific, as Rambus
argues, but that does not help Rambus. Rambus relies on the use of the
rising CLKB edge on the ACD bus to contradict the Examiner’s finding:
“signals on the Address/Control/Data (ACD) Bus are sampled based on the
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rising edge of CLKB and driven based on the falling edge of CLKB.” (App.
Br. 24.) See also Rambus-Rea, 731 F.3d at 1254 (discussing Examiner’s and
Board’s fact finding about the rising CLKB edge).
Nevertheless, the ACD bus is not relevant, because the Examiner
relies on the MACD bus, not the ACD bus. (RAN 51–87.) The falling
CLKB edge is not used to trigger anything on the relevant bus, the MACD
bus. (iAPX Spec., BIU-38; MCU-36.) More importantly, whether the
CLKB edge is used to trigger another event, is not relevant either, because,
as discussed above, the record shows a clock edge does not “carry”
information, as Rambus argues, rather, it can be used to time or trigger
multiple events. (See iAPX Spec., BIU-38, BIU-42; MCU-36.)
Specifically, the other three rising and falling edges of both CLKB and
CLKA are used to time/trigger multiple control events, thereby implying that
the falling CLKB edge similarly can trigger multiple control events, if
desired. (See iAPX Spec., BIU-38, MCU-36.)
Accordingly, iAPX, in light of Inagaki, suggests two simple
modifications that employ both iAPX clocks. In a first modification, recall
that the BIU outputs data on the MACD bus on the rising CLKB edge as a
trigger. (A-6.) In a small single MCU/BIU system (with a corresponding
short transmission length for the clocks and signals and single module),
under the first modification, the same rising CLKB edge can be used to
trigger sampling that data by the MCU as Inagaki and iAPX each suggest.
13

13
Similar to Inagaki, as another example of using the same clock edge to
time events at receiving and transmitting devices in the iAPX system, as
Rambus states, the BIU inputs and outputs data on the ACD bus on rising
and falling CLKB edges. (BIU-38.) The BIU and another processor connect
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The next falling CLKB edge can be used to trigger the output of more BIU
data, and trigger sampling thereof by the MCU, as Inagaki also suggests,
thereby satisfying the DDR function recited in the claims.
Under this timing modification, CLKA can be used to trigger all of its
remaining disclosed functions. Recall that Budde employs the rising CLKB
edge differently than the iAPX system, showing that system designers knew
how to modify the use of the clock edges to time desired events in the
flexible system. The modification involves rearranging timing events,
something well within the realm of an ordinarily skilled artisan, adept at
modifying flexible systems like the iAPX system and Budde’s similar
system, and relatively simple systems like the Inagaki system.
A second modification that also involves both clocks also involves a
mere rearrangement of timing triggers, especially for small, single module,
single memory bus, systems. As explained above, the iAPX system employs
the rising CLKA edge to trigger data sampling by the MCU on the MACD
bus. In light of the reason (speed, reduction of data lines) for using DDR
provided by Inagaki, and the flexibility of iAPX, ordinarily skilled artisans
would have recognized that the MCU could have used the falling and rising
CLKA edges to sample (input) data that the BIU outputs on rising and
falling CLKB edges. Therefore, in another relatively minor modification to
the iAPX timing scheme using both clocks, the BIU can send data onto the

to the ACD bus, suggesting that these devices use the same clock edges to
input and output data. (See A-4, BIU-20; A-5) As found above, clock
cycles at issue are long compared to transmission delays on a short bus and
clock line. One module and one processer, disclosed by iAPX, obviously
can be connected by a very short bus. (See note 9.)

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MACD bus on a rising CLKB edge, the MCU can sample that data on a
falling CLKA edge, the BIU can send more data to the MACD bus on the
falling CLKB edge, and the MCU can sample that data on the rising CLKA
edge, and so on. (See iAPX Spec., BIU-38, BIU-40, MCU-41.)
Even if data holding or other constraints must be considered by a
skilled artisan for the two-clock modification, they would not impact, at all,
the triggering (note 8) and single clock modification rationales described
above. For example, having rising and falling edges of an external clock
trigger the rising CLKB edges does not impact any timing relying on those
rising CLKB edges, regardless of the data hold length. Also, replacing the
iAPX system’s dual clock system with Inagaki’s simpler single clock system
to handle simple data transfers in a single MCU/BIU as claims 3 and 26
embrace, and iAPX and Inagaki fairly suggest, would not have the alleged
timing constraints of four clock edges. Inagaki provides the fastest speed
relative to a set clock speed or data bus width regardless of the rise times or
data hold times, because speed ultimately is triggered and governed by the
dual edges of the clock. No faster speed is possible for a given clock speed
or bus width unless both clock edges are employed. (See I1-I3.) Therefore,
if Rambus’s argument that there is some constraint due to clock rise times or
data holding times is correct, this further suggests using one clock to
maximize speed as Inagaki does for a given clock rate or bus width.
Most of the proposed modifications effectively double the iAPX data
rate from 10MHz to 20MHz. Even if some timing constraints exist as
Rambus argues, but which the record does not support, ordinarily skilled
artisans also would have recognized a trade-off, using a slower clock to
accommodate any such constraints, for example, an 8 MHz clock, and
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effectively creating 16MHz data speeds. The record does not show that any
alleged constraints exist for systems within the claim breadth, i.e., small
systems with short conductor lengths that have one or two memory modules,
like that of Inagaki or those suggested by iAPX.
Rambus alleges in a section heading that “iAPX Does Not Disclose
Other Features Recited in the Claims.” (App. Br. 21 (emphasis omitted).)
Rambus’s truncated arguments reduce to the unpersuasive “single-chip”
arguments addressed supra. For example, with respect to claim 26, Rambus
asserts that “[t]he actual memory devices in the storage array of iAPX never
receive any block size information.” (Id.) Rambus does not contest the
Examiner’s finding that the MCU in the memory device receives the block
size information. (RAN 76.)
Based on the foregoing discussion and the secondary considerations
discussed next, we sustain the Examiner’s obviousness rejection of
remanded claims 3–5, 11, 12, 26, 28–32, and 35 based on the iAPX (Manual
and/or Specification) and Inagaki. Affirmance of the iAPX based
obviousness rejection renders it unnecessary to reach the Budde based
obviousness rejection. Cf. In re Gleave, 560 F.3d 1331, 1338 (Fed. Cir.
2009) (not reaching obviousness after finding anticipation).
Objective Evidence of Nonobviousness
1. Background
Rambus alleges secondary considerations of long-felt need, failure of
others, skepticism, commercial success, and praise by others, as rebuttal to
the obviousness finding by the Examiner regarding claims 1–5, 7, 8 10–12,
14, 26, 28–32, 34, and 35. (App. Br. 27–30.) Rambus does not specify, and
it is not clear on this record, which of the claims on remand, claims 3–5, 11,
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12, 26, 28–32, and 35, are coextensive with the asserted evidence of
nonobviousness. See Brown & Williamson Tobacco Corp. v. Philip Morris
Inc., 229 F.3d 1120, 1130 (Fed.Cir.2000) (stating the presumption that
commercial success is due to the patented invention applies “if the marketed
product embodies the claimed features, and is coextensive with them”)
(emphasis added).
As noted, Inagaki anticipates claims 1, 2, 7, 8, 10, and 14. Rambus-
Rea remanded to the Board to reconsider whether “claims 3–5, 11, 12, 26,
28–32, and 35 are unpatentable.” Rambus-Rea, 731 F.3d at 1258. At this
juncture, Rambus’s arguments have focused on claim 1. In Rambus-Rea, the
court directed the Board to “to determine if Rambus’s objective evidence on
nonobviousness pertains to the Rambus device or simply to the dual-edge
functionality [DDR] disclosed in Inagaki.” Id. at 1258. In other words,
Rambus-Rea directs the Board to make new evidentiary findings and
designate the Decision as a new ground.
“Once a prima facie case of obviousness has been established, the
burden shifts to the applicant to come forward with evidence of
nonobviousness to overcome the prima facie case.” In re Huang, 100 F.3d
135, 139, 40 (Fed. Cir. 1996) (Concluding that “Huang simply has not
carried his burden to prove that a nexus existed between any commercial
success and the novel features claimed in the application.”) On this record,
Rambus has not carried its burden as to the remanded claims, claims which
Rambus does not argue separately from claims anticipated by Inagaki.
Rambus-Rea indicated that the Board’s requirement that the claims
must recite a set speed to show that the objective evidence is reasonably
commensurate in scope with the claims, was too strict on that record. The
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court stated that “we do not require a patentee to produce objective evidence
of nonobviousness for every potential embodiment of the claim.” Id. at
1257.
The court reasoned as follows:
Moreover, Rambus’s evidence shows beyond dispute that the
claimed dual-edge data transfer functionality is what enabled
the praised high-speed transfer of data. A Byte Magazine
article explained that, “by using both edges of a 250–MHz
clock,” Rambus's memory chips “will deliver a tenfold increase
in component throughput.” J.A. 2623. The Electronic
Engineering Times likewise described the dual-edge
functionality as “designed to burst the bottleneck between
processors and DRAMs in desktop systems.” J.A. 2624–25.
The Board did not point to any contrary evidence, and we have
not found any in the record.
Id. at 1257 (emphasis added).
Inagaki’s double-data-rate (DDR) concept does not show
unobviousness or produce ten-fold speeds. However, Rambus-Rea indicates
that Rambus may be able to rely on Rambus’s DDR concept to show
unobviousness, because the Board “did not point to contrary evidence” that
Rambus’s DDR concept does not “enable[]” the touted tenfold speed
increase that bursts the bottleneck. See id. at 1257.
Inagaki anticipates claims 1, 2, 7, 8, 10, and 14. Rambus-Rea 731
F.3d at 1254. That holding means Inagaki’s DDR concept includes
Rambus’s DDR concept to the extent it is recited in the anticipated claims.
The court’s rationale indicates that Rambus may be able to rely on “the
claimed dual-edge transfer [DDR] functionality,” as it is recited in the
remanded claims, because certain magazine articles showed that that feature
solved a long-felt need and evidenced industry praise. See id. at 1256-1257
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(citing an article in Microprocessor Report). The court reiterated that “the
Board did not address any of this evidence.” See id. at 1257
Accordingly, on remand, we address the evidence as it relates to the
claims, as the court instructs, to determine whether or not the claimed DDR
functionality inherently creates the touted ten-fold (or enhanced, e.g., five-
fold, seven-fold, etc.) speed increase to solve the bottleneck problem, or
shows unobviousness based on commercial success or other indicia of
unobviousness argued.
2. Rambus’s Contentions
In its Federal Appeal Brief, Rambus argues that “[w]ith respect to the
claims not ‘recit[ing] a specific clock speed,’ synchronous DRAMs
employing a dual-edge/double-data-rate [DDR] feature were shown to
enable speeds ten times faster than the prior-art asynchronous DRAMs.”
(Fed. App. Br. 61 (emphasis added).) In other words, Rambus appears to
argue that the claims solve the prior art speed problem, because the claimed
device “enables” high speeds. However, Rambus acknowledges that long-
felt need evidence is negated when the claims cover devices that do not
solve the speed problem. See id. (citing Therasense, Inc. V. Becton,
Dickinson & Co., 593 F.3d 1325, 1336 (Fed. Cir. 2010) (“finding no long-
felt need because the claims were broad enough to cover devices that did not
solve the problem”) (emphasis added, quoting Rambus’s characterization of
the case). In other words, Rambus acknowledges that if the claims “cover
devices that did not solve the problem,” then the claims are not reasonably in
scope with the proffered objective evidence.
Rambus also implicitly acknowledges that Rambus-Rea’s anticipation
(by Inagaki) holding changes the analysis in terms of nexus: “By the Board’s
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logic, the PTO could always make an alternative anticipation rejection and
dismiss all evidence of long-felt need based on the putative anticipation
rejection.” (Fed. App. Br. 61 (emphasis added).)
3. Claims 3 and 26
Method claims 3 and 26 recite no hardware, circuitry, function, or
structure that supports or requires high speed operation. The claims recite
“memory cells” in a “memory device.” Claim 3 depends from claim 2,
which depends from claim 1. Claim 1 includes limitations pertaining
respectively to a method of using the rising and falling edges of a clock
signal (i.e., DDR–double data rate) but does not require the operation code
recited in claim 2. Rambus argued that claim 1 includes features that
address the long-felt need for higher memory performance. (App. Br. 28.)
Rambus, without explanation, argued that the operation code also solves the
speed problem. (See id.) Inagaki anticipates claim 2. Therefore, the
operation code could not have solved a speed problem that claim 2
embraces.
Claim 3 further limits the operation code of claim 2 by requiring it to
be received synchronously. Claim 2 requires synchronous operation in
general. Claim 26 is similar to claim 1 and adds the feature of block size
information. As explained further below, Rambus’s evidence of non-
obviousness points to bottleneck (speed) problems solved by modified DDR
DRAMs (or at most, other single chip devices) with interface circuitry
required to create the touted speed (e.g., 500 MHz). Claims 3 and 26 do not
implicitly or otherwise require a single chip, a DRAM, or include interface
circuitry that inherently requires, or enables, speeds in significant excess, if
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any, of what anticipated claims 1 and 2 recite. Claims 3 and 26, therefore,
do not address or solve any bottleneck (speed) problem.
Claim 26 recites providing block size “wherein the block size
information defines a first amount of information to be output by the
memory device in response to a read request.” According to the ’097 patent,
block size can include zero or more bytes (zero represents a special
command). (See ’097 patent, col. 11, ll. 38-50 (Table, “Number of Bytes in
Block” includes 0–7).) As indicated above, In re Rambus held that the iAPX
system anticipates a similar (albeit single edge) claim that recites block size
information.
Also, Rambus does not specify how many bits a byte may include. A
byte, in the context of data, alternatively may refer to the number of parallel
bits on a data bus, or the number of sequential bits on one data line (one
memory device pin). For example, a preferred embodiment implies an 8-bit
data byte carried on an 8-bit data bus of parallel lines. (See ’097 patent, col.
4, ll. 8-11.) Alternatively, “other numbers of bus data lines can be used to
implement this invention.” (Id. at col. 4, l. 7–8.) Typically, a byte is “[a]
sequence of adjacent binary digits [i.e., bits] operated on as a unit . . . usually
shorter than a word.” McGraw-Hill Dictionary of Scientific and Technical
Terms 288 (5th ed. 1994) (Appendix).
Mr. Murphy describes block operations as follows: “[r]ather than
inputting or outputting a single bit of data per pin . . . the memory devices
. . . can input or output, for example, four bits, eight bits or other amounts of
data per pin in response to a request, where the number of bits can be
selected based on the needs of the system or application.” (Murphy Dec.
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¶ 23 (emphasis added).) In other words, in at least one embodiment, block
size refers to “data per pin”––bit data that comes out of or goes into a pin
sequentially in time (to form a block) as the DDR edges rise and fall.
In contrast to the claims at issue here, Mr. Murphy notes that original
application claims recited “a package with a plurality of bus lines.” (Id. at
¶ 34.) Mr. Murphy also states that a “separate object” of the invention
“provide[s] a method of transferring address, data and control information
over a relatively narrow bus.” (Id.) This disclosed “narrow bus,” includes
the narrowest of buses, one with a single data line, even if the claims, which
do not recite a bus, or a number of device data pins, implicitly require a bus
(with address and control lines, for example). It follows that the recited
memory device only requires one data pin, and block data may include a
block of, for example, two bits, which may be written into a memory device
single pin, as opposed to several pins that correspond to several parallel data
lines.
An Initial Decision from the Federal Trade Commission (“FTC”),
cited by Rambus to the Federal Circuit in Rambus-Rea, 731 F.3d at 1257
(citing J.A. 2099), further corroborates this claim construction. The FTC
summarizes part of the testimony by one of Rambus’s inventors, Dr.
Horowitz:
88. One of the ways that RDRAM technology achieves a high-
speed data transfer over the narrow bus is through
“multiplexing,” which means that the bus can carry different
pieces of information at different points in time. (Horowitz, Tr.
8620-21). This aspect of the RDRAM interface protocol means
that over several clock cycles the bus can carry a combination
of address and control and data signals on one or more of the
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same bus lines. (Horowitz, Tr. 8620-21; see Rhoden, Tr. 402-
03).
(FTC 19 (emphasis added).)
14

The FTC findings and Mr. Murphy corroborate that the claims cover
memory devices with “one or more” data bus lines (and one or more
memory device data pins).
The FTC also noted that Rambus described a feature known as
“variable block size,” as innovative:
57. As another example of an innovation related to the protocol,
Drs. Farmwald and Horowitz allowed the response to a request
to include a variable amount of data, a feature known as
“variable block size” or “variable burst length.” (Farmwald, Tr.
8116- 8146; Horowitz Tr. 8512; RX 82 at 9).
(FTC 15.)
Claims 3 and 26 do not recite a “variable block size.” Claims 3 and
26 do not recite a bus, a plurality of bus lines, or a set number of data pins.
Claim 26 recites “block size information.” Even if somehow, block size
information must vary, one variation may include the special command
noted above, a block size of zero bytes (i.e., implicitly zero bits). Therefore,
if some variation is required, the block size information may include a block
size of zero or two bits, bits which are transmitted sequentially into or out of
one or more pins (implicitly) on the recited memory device. Such sequential

14
See Initial Decision at the United States of America Federal Trade
Commission, Office of Administrative Law Judges, In re Matter of Rambus
Inc., No. 9302 (Feb. 23, 2004) (Chief ALJ S. J. McGuire) avail. at
http://www.ftc.gov/sites/default/files/documents/cases/2004/02/040223initia
ldecision.pdf. (attached as App. Br. Ex. G-3.)
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transmission does not alter the data bit rate or the data byte rate, which is
touted as fast, as explained further below.
4. Praise for a DDR Memory Device
DDR in synchronous memory devices cannot be the object of praise
that shows unobviousness, because Inagaki discloses DDR in a memory
RAM device, and anticipates claims 1 and 2. See Ayst Techs., Inc. v.
Emtrak, Inc., 544 F.3d 1310, 1316 (Fed. Cir. 2008) (“even though
commercial embodiments . . . have enjoyed commercial success, Asyst’s
failure to link that commercial success to the features of its invention that
were not disclosed in Hesser undermines the probative force of the evidence
pertaining to the success of Asyst's and Jenoptik's products.”); J.T. Eaton &
Co. v. Atl. Paste & Glue Co., 106 F.3d 1563, 1571 (Fed.Cir.1997) (“asserted
commercial success of the product must be due to the merits of the claimed
invention beyond what was readily available in the prior art”)(emphasis
added). Under Ayst and Eaton, Rambus has the burden of showing nexus by
linking its evidence “beyond what was readily available in the prior art.”
See also In re Huang, 100 F.3d 135, 140 (Fed. Cir. 1996) ( Cir. 1996)
(“[T]he PTO must rely upon the applicant to provide hard evidence of
commercial success.”)
5. Inherent Speed-–Nexus-–Unclaimed Chip Interface and Other
Unclaimed Features
On nexus, Rambus-Rea, 731 F.3d at 1258 directs the Board to “be
careful to parse the evidence that relates only to the prior art [DDR]
functionality and the evidence that touted Rambus’s patented design as a
whole.” Rambus’s disclosed design as a whole, prominently includes the
chip interface on a single chip and its attendant functional hardware, which
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is touted, but is not claimed. Without the chip interface, the touted speeds of
250–500Mhz, are not enabled, much less inherent, in claims 3 and 26.
15
The DDR recited in claims 3 and 26 cannot enable the touted high
(250–500 MHz) speeds. Inagaki, the ’097 patent, and other evidence, shows
this. Inagaki discloses DDR memory devices, and anticipates all of the
patented design recited in claims 1 and 2. Claims 3 and 26 fail to add to the
speed capability, as a matter of structure, or function, in any appreciable
manner advanced by Rambus on this record. Although the DDR
functionality may be necessary, it is insufficient to enable, by itself, the
touted speeds of 250–500 MHz, or to handle a 250 MHz (or less) clock to
create that touted speeds using DDR. If it were, Inagaki’s device also would
be five to ten times faster than prior art memory devices, because it uses the
claimed DDR functionality, as the anticipation holding proves.
According to the ’097 patent, and as anticipation by Inagaki implies,
unclaimed memory interface features in a single chip “must be added” to
obtain the speed: “New bus interface circuits must be added and the
internals of prior art DRAM devices need to be modified so they can provide
and accept data to and from the bus at the peak data rate of the bus. This
requires changes to the column access circuitry in the DRAM . . . .” (’097
patent, col. 4, ll. 27–31.)
The ’097 patent discloses fast (e.g., 500 MHz), single chip, DDR
DRAM devices, which require a fast (e.g., 250 MHz) clock to obtain that
speed:

15
Articles generally tout a ten-fold speed of 500MHz, with at least one
discussing five- to ten-fold speed increases. (See PTO Fed. Br. 49–50
(summarizing articles; App. Br. App. L.)
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High bus bandwidth is achieved by running the bus at a
very high clock rate (hundreds of MHz). This high clock rate is
made possible by the constrained environment of the bus. . . .
For a data rate of 500 MHz, the maximum bus propagation
time is less than 1 ns (the physical bus length is about 10 cm).

(’097 patent, col. 4, ll. 36–43 (emphasis added).) Similarly, to enable the
high speed, i.e., “to operate at a 2 ns data rate, the transit time on the bus
should preferably be kept under 1ns[ec] . . . . Thus, the bus lines must be
kept quite short, under about 8 cm for maximum performance.” (Id. at col.
18, ll. 12–16 (emphasis added).)
The method claims do not specify any chip interface, bus, or bus
length. As part of what “must be added” to memory device chip interfaces
to handle the “very high clock rate made possible” by short propagation
lengths (10cm), Figure 10 discloses the sole embodiment of part of this
required “new bus interface circuit[]” in the modified DRAM: “a set of
input receivers 71, 72 . . . and circuitry to use the internal clock 73 and
internal clock complement 74 to drive the input interface.” (’097 patent, col.
21, ll. 49-53.) Further, “each device pin, and thus each bus line, is
connected to two clocked receivers, one to sample the even cycle inputs, the
other to sample the odd cycle inputs.” (Id. at col. 21, ll. 56-58.) In addition,
the interface must control skew: “One important part of the input/output
circuitry generates an internal device clock based on early and late bus
clock. Controlling clock skew (the difference in clock timing between
devices) is important in a system running with 2 ns cycles.” (Id. at col. 22,
ll. 53-57.) (Note that a 500 MHz frequency corresponds to a 2 nsec or “2 ns
cycle[]”time period.)
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Rambus’s related patent, U.S Patent No. 5,513,327 (Apr. 30, 1996),
specifically claims these first and second input receivers, and an internal
clock, to handle DDR, in a “DRAM.” See id., claim 1. The ’097 patent
recites broader claims, without DRAMs, the internal clock, the receiver
clock circuitry, or skew correction circuitry, and relies on the ’327 patent for
continuity. (The ’097 patent also implies that a “number” of other changes
over “conventional DRAMS” contribute to speed or efficiency––such as
“registers,” to “store control information,” “device identification” and
“address” information. See id. at col. 4, ll. 22–27.)
Mr. Murphy corroborates these findings and points to similar
disclosures about the two internal clocks in the chip interface (in an effort to
show that the system does not require two external clocks). (See Murphy
Decl. ¶39 (noting “two clocked receivers”), ¶¶ 36–40 (describing clocking).)
Mr. Murphy declares that “one object of the invention is to ‘use a new bus
interface built into semiconductor devices to support high-speed access to
large blocks of data from a single memory device by an external user of the
data, such as a microprocessor, in an efficient and cost-effective manner.’”
(Id. at ¶ 32 (quoting original patent application for the ’097 patent, “the ’898
App.,” citation omitted).)
Rambus’s argument in its Federal Circuit brief about the
“synchronous DRAM[],” quoted above, Dr. Horowitz’s discussion of the
“RDRAM interface,” below, magazine articles, and the claims in the earlier
’327 patent, all show agreement with, and bolster, the findings. As noted,
Rambus alleges that a modified DRAM chip, using DDR, solves the speed
problem. Claims 3 and 26 do not require a DDR DRAM, or RDRAM, or
any single chip DDR memory device, inherently or otherwise.
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Contrary to its assertions to the Federal Circuit about inherency and
tenfold speed based on DDR, Rambus admitted to the Board that DDR only
“allowed data to be transferred at twice the rate of the external clock signal,
thus improving the speed of data transfer for a particular clock frequency,”
and Rambus called this a “[s]ignificant performance improvement[].” (See
PTAB 2012-001976, rexam. cont. nos. 95/001,128 & 95/001,026; Rambus
App. Br. 22 (Sept. 23, 2010) (emphasis added).)
Rambus-Rea directs the Board’s attention to a Microprocessor Report:
article:
For example, an article in the Microprocessor Report stated that
Rambus “ha[d] unveiled its radical new processor-to-memory
interface and DRAM architecture, which promise to create the
most significant change in processor/memory system
architecture since the introduction of the DRAM two decades
ago.” J.A. 2633. The article explains that the technology
“operat[es] with a 250–MHz clock and transfer[s] a byte of data
on each clock edge,” an approach that was “somewhat counter-
intuitive.”
Rambus-Rea, 731 F.3d at 1257.
Rambus-Rea also directs attention to similar articles. See id. As the
quote and virtually all, if not all, the articles show, in line with the ’097
patent disclosure, the touted speeds of 250–500 MHz require a “radical”
Rambus chip interface with the ability to handle fast (e.g., 125–250 MHz
clocks). The memory chip requires “a significant change in . . .
architecture,” and/or “a radical new . . . interface,” in a DRAM (or other chip
perhaps): i.e., interface circuitry having the necessary structure ability to
handle a high speed (e.g., 125–250 MHz) external clock. (See App. Br., Ex.
L, R39356-60, Microprocessor Report article.)
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The Microprocessor Report article explains that “[t]he high clock rate
is made possible by a combination of special CMOS interface circuits,
careful circuit board layout, short trace lengths, RAM packages with low
parasitic capacitance and inductance, and low voltage swings.” (App. Br.,
Ex. L. R39357 (emphasis added).) Claims 3 and 26 do not recite this
“combination,” which includes the “special CMOS interface circuits,” which
makes speed “possible.”
The same article refers to “[l]ogic designs for the Rambus master and
slave interfaces, to be incorporated into processors for interface ASICs and
DRAMs.” (App. Br., Ex. L., R 39356 (emphasis added).) “In addition to the
Rambus Channel interface, the major difference between a standard DRAM
and an RDRAM is the way the sense amplifiers are used.” (App. Br., Ex. L.
R 39357.) Claims 3 and 26 do not require the interface, a DRAM, short
traces, low parasitic capacitance, and other noted features.
Rambus-Rea also cites an Electronic Engineering Times (“EET”)
article for “describ[ing] the dual edge functionality as ‘designed to burst the
bottleneck between processors and DRAMs in desktop systems.’” Rambus-
Rea, 731 F.3d at 1257.
16
The system includes “a unique 500-MHz, 9-bit
data channel designed to burst the bottleneck between processors and
DRAMs in desktop systems.” (Id.) (App. Br., Ex. L, R39847 (the EET
article).) The DDR concept, by itself, does not burst the bottleneck. Rather,
the 500MHz, 9-bit DRAMs, with the chip interface circuitry, at the least, are
required. The 500 MHz speed requires the 250 MHz clock, which requires

16
The EET article is listed as R39347–R38348 in Rambus App. Br. Ex. L
(Ron Wilson and David Lammers, “Rambus Lets Loose fast DRAM
channel,” Electronic Engineering Times, Iss. 684, Mar. 16, 1992).
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the interface to handle that. A “key part” requires the “high-speed bus [to
be] . . . synchronized to a 250MHz clock.” (Id. at R39348.) The EET article
describes an “RDRAM,” which refers to the interface features as discussed,
including, at least, the disclosed receiver circuitry that “must” be included to
handle fast clocks in a single modified DRAM chip.
The EET article touts other related features. “To achieve this speed,
the bus employs low-voltage, CMOS drivers and receivers . . . .” (Id.) Also,
“the Rambus channel moves bytes over 9 data wires, synchronized to a 250
MHz clock.” (Id.) “The combination of sense-amp caching and a
500Mbyte/second bus provides enormous theoretical bandwidth between the
DRAM memory array and a processor.” (Id.) “The DRAM produces an
entire row of data . . . at its sense amps.” (Id.) None of the described
features, the DRAMs, low voltage CMOS drivers and receivers, the high
speed bus, the nine data wires, 250MHz (or similar speed) clock interface
circuitry, the sense-amp caching, or other touted features, are recited in
claims 3 and 26.
Rambus-Rea also cites to a Byte Magazine article that shows that “‘by
using both edges of a 250-MHz clock,’ Rambus's memory chips ‘will deliver
a tenfold increase in component throughput.’ J.A. 2623.” Rambus-Rea, 731
F.3d at 1257. This also shows that, at a minimum, the 250 MHz clock
DRAM receiver interface, to handle the “250-MHz clock,” is required to
create the touted ten-fold increase.
Stated differently, the DDR (double data rate) function itself cannot
deliver a ten-fold increase: DDR, as the name implies, only doubles the
speed. At the least, the chip interface, touted in the articles, and disclosed in
the ’097 patent, must be present to enable the ten-fold speed increase.
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Multiplying the five-fold increase, which the unclaimed DRAM interface
circuit (and, inter alia, short bus lengths, etc.) provide, by the predictable
two-fold claimed DDR function, results in the touted ten-fold increase.
Another article cited by Rambus, Semiconductor Currents, verifies
this, and states that “Rambus Slashes memory bottleneck with 500 Mbytes/s
memory bus,” and states that transfers on both clock edges “doubl[es] the
bandwidth to 500 Mbytes/s.” (App. Br., Ex. L, R39362 (emphasis added).)
This corroborates the findings of record that other disclosed, but unclaimed,
hardware elements, including the chip “interface” to handle the 250 MHz
clock, are necessary to obtain the remaining five-fold (out of ten-fold) factor.
Rambus’s Appeal Brief Exhibit L consists of several other articles that
generically tout the 500MHz speed and many other unclaimed features,
including the Rambus DRAM chip interface. For example, the San
Francisco Chronicle article, generically discusses Rambus technology, such
as the “so-called new interface for DRAMs that is both simpler and faster
than earlier designs,” and touts the tenfold speed of 500MHz. This article
does not mention DDR. Rambus appears to be the source of the article.
(App. Br., Ex. L, R39338.)
Another article, Semiconductor Currents, states that “Rambus Slashes
memory bottleneck with 500 Mbytes/s memory bus.” The article states that
“the bus only requires CMOS at each end! No fancy/costly BiCOMS, or
other bipolar wizadry.” (App. Br., Ex. L, R39362.) The article also notes
that transfers on both clock edges “doubl[es] the bandwidth to 500
Mbytes/s.” (Id. (emphasis added).) This also shows that DDR only doubles
the speed. The article states that the “Rambus concept consists of a Rambus
master, either included on-chip in the CPU . . . driving a 9-bit, 250 MHz bus
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to Rambus slaves.” (Id.) This Rambus concept requires the fast clocks on a
9-bit bus, and the DRAM slave interface to handle that, which does not
pertain to the claims at issue here.
Further corroborating the article evidence, the ’097 patent describes a
litany of other significant features that implicate commercial embodiments
and support either bit or byte speed. Unclaimed, but disclosed features,
include eight data lines, small DRAM sizes with minimal bus loading,
multiplexed bus architecture and device interfaces, packetized control,
unique device identifiers, time access and arbitration schemes, controlled-
impedance, double terminated lines, reduced power, and memory devices
having all the functionality of prior art circuit boards. (See ’097 patent,
Abstract, col. 3, ll. 23–48; col. 4, ll. 22–57; col. 7, ll. 7–30; col. 9, ll. 38–64;
col. 12, ll. 45–58; col. 14, ll. 46–65; Murphy Decl. ¶¶ 31–36.)
As another example of an unclaimed, but touted feature in the chip
interface supporting speed, Dr. Horowitz obtained praise for “a number of
phase-locked loop circuits” and for other “ideas he pioneered.” (See Ex. J,
IEEE Horowitz release (touting “significant[] increase [in] the bandwidth of
the access to DRAM circuits” up “to several gigabits/second.”) The IEEE
release includes praise because of changes in “the way an entire industry
thinks about memory interfaces.” It touts his work “on interface circuits.” It
does not mention DDR. (See also App. Br., Ex. E-5, Farmwald Testimony,
277–279 (touting 8 bit wide DRAMs at 500MHz).
17
Rambus points to

17
Rambus also cites to Dr. Farmwald’s testimony to show a solution to a
long-felt need, but Dr. Farmwald does not even discuss DDR at the cited
passages. He only generally discusses building a 500MHz, 8 data bit wide,
single DRAM chip (i.e., 8 data pins), without any specifics, as a general
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similar evidence by Dr. Horowitz, who also indicates that at least part of any
success was due to other unclaimed features. The inventor declared that “it
was felt that . . . one could not put a phase locked loop or delay locked loop
on the DRAM itself” and that others expressed “disbelief” about a 500
[MHz] DRAM rate.” (App. Br. 29 (emphasis added).) This disbelief, or
skepticism, if it existed, goes to unclaimed features: a PLL on the DRAM
itself (the single chip interface), and the 500 MHz speed.
Under Ormco,Corp. v. Align Tech., Inc., 463 F.3d 1299, 1311-12
(Fed. Cir. 2006), Rambus’s evidence does not establish a nexus, because it
relies on, at the least, an unclaimed chip interface with specifically required
receiver features, to inherently provide unclaimed speed (setting aside the
short bus length and the PLL): “[I]f the commercial success is due to an
unclaimed feature of the device, the commercial success is irrelevant. So
too if the feature that creates the commercial success was known in the prior
art, the success is not pertinent.” Id. at 1312 (footnotes and citations
omitted). The DDR feature “is not pertinent,” because it is in the prior art,
i.e., Inagaki. The features required to handle the highly-touted remainder of
speed, the factor of roughly two-and-a-half to five, involves unclaimed
features, at a minimum, the unclaimed chip interface, with its dual receivers
(that may require clock skew correction circuitry) to handle the high speed
clocks (e.g., 125-250 MHz). The record also shows that the high speed
requires short bus distances, delay or phase locked loop interface circuits for

trade-off based on cost, and solution to future speed problems in the mid-
1990s. (See App. Br. Ex. E-5, 277-280.) The claims do not require speed, a
DRAM, or 8 data pins.
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skew correction, and other receiver features. Rambus has not met the
burden of showing nexus for the remanded claims.
6. Counterintuitive-Nexus
In 1982, Inagaki’s method, using DDR, increased the speed of prior
art “conventional” devices from “about 100nsec” (10MHz), to “twice the
conventional speed,” or 50nsec (effectively 20 MHz). (See Inagaki 3.) In
1990, Rambus touted a ten-fold increase over those speeds––speeds of about
2nsec (1/2nsec = 500 MHz), by using DDR on a 250 MHz clock). (See ’097
patent, col. 18, ll. 1-5 col. 21, l. 60, col. 22, l. 20.)
Rambus-Rea also states that “[t]he [Microprocessor Report] article
explains that the technology “operat[es] with a 250-MHz clock and
transfer[s] a byte of data on each clock edge,” an approach that was
“somewhat counter-intuitive.” Rambus-Rea, 731 F.3d at 1257. Rambus-Rea
indicates the Board erred in finding of lack of nexus, because this quotation
shows a nexus by praising the claimed DDR feature. See id. The DDR
feature, at least for a single bit on a single pin, is in the prior art, as Inagaki
shows, and does not show a nexus to claims that do not recite a set number
of data pins or bus lines, or implicitly require such a number.
The praise, as noted in the article, and as discussed above, touts
several unclaimed features, the “special CMOS interface circuits,” “logic
designs,” and a “combination” of features that make “possible” the “high
clock rate”: “The high clock rate is made possible by a combination of
special CMOS interface circuits, careful circuit board layout, short trace
length RAM packages with low parasitic capacitance and inductance, and
low voltage swings.” (App.Br., Ex. L, R39357.)
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According to the article, a counter-intuitive feature focuses on
obtaining fast speed by using a “narrow bus”:
The Rambus approach is somewhat counter-intuitive, in
that it achieves its high bandwidth through fast data rates
rather than wide buses. One benefit is that a minimum system
can use a single Rambus memory device, regardless of the
system’s word width. The narrow bus also minimizes the
number of pins and amount of board area required.
(App. Br., Ex. L, R39356.)
Setting aside the focus on the unclaimed “single Rambus memory
device,” and focusing on the “narrow bus,” Inagaki already taught that a
major beneficial aspect of DDR is that it increases data speed for a given
clock speed or a given number of data lines (and corresponding memory
device data pins). (See I1, Inagaki 2–3.) Inagaki specifically disparages the
prior art method of “increas[ing] the number of pins,” because that makes it
“impossible to increase the integration on a board.” (Inagaki, 2; accord I1.)
In other words, Inagaki addresses part of the speed problem that
otherwise requires an increased pin count (i.e., an increased data bus width)
by using DDR on a relatively narrow bus. (See also I1-I3.) The
Microprocessor Report describes as counterintuitive the same DDR concept
that Inagaki described about 8 years prior to the filing date involved here.
Essentially, Inagaki teaches minimizing the number of data lines or pins by
using both clock edges (i.e., narrowing the bus). (See I1-I3.) Therefore, it
was not counter-intuitive at the time of the invention to reduce the pin count
or narrow the bus width, and increase the data rate, by simply using DDR in
a memory device, because Inagaki already did that.
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Even if the article somehow praises the use of DDR on a byte, i.e., for
two bits of data on either a single data line or on unclaimed parallel bus
lines, this does not show nexus. The non-novel DDR feature, precluded by
Inagaki as a basis of praise or commercial success, at the least, includes the
synchronous transfer to a memory chip device of successive bits of data (a
byte) on a data line using DDR. See Tokai Corp. v. Easton Enters., Inc., 632
F.3d 1358, 1369 (Fed.Cir.2011) (“If commercial success is due to an
element in the prior art, no nexus exists.”). Even if the use of DDR on two
data lines (i.e., a data byte on parallel lines in a narrow bus of two) attached
to two pins in a memory device was not in the prior art (i.e., Inagaki), unless
that feature inherently produces the speed or other features touted in the
articles, it fails to solve the bottleneck problem and runs afoul of
Therasense, which Rambus cites, as noted above and further below. As
explained, DDR only doubles the data rate, as expected, and which includes
bit rate or byte rate, and DDR does not enable the touted speed, much less
inherently require it.
Moreover, as set forth above, claims 3 and 26 do not require a data
byte transfer on parallel lines (i.e., at least two bits per clock edge). Hence,
any praise to a DDR byte transfer, even if it relates to parallel lines, relates to
an unclaimed feature. The remanded claims do not recite multiple data lines
or multiple pins on the memory device, and therefore do not require “a byte
of data on each clock edge,” which the article addresses. Ultimately, the
praise either goes to unclaimed features related to a transfer of a byte of data
on successive clock edges of a 250 MHz clock that triggers multiple data
lines simultaneously (albeit, a small set thereof on a narrow bus), or it goes
to the DDR feature in the prior art that Inagaki discloses.
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Further, as the Examiner found per the rejection of the claims, and as
In re Rambus implies, iAPX discloses byte transfers on parallel lines
triggered by a single clock edge to a synchronous memory module (having
aggregated memory chips controlled by the MCU). Inagaki discloses that
prior art memory device chips were employed in parallel to “increase the
MOS RAM bit width (a multi-bit structure) to increase the data transfer
rate.” (See Inagaki 2.) Therefore, skilled artisans would have recognized
that the Inagaki DDR concept, even if a specific embodiment therein is
limited to a single data pin (and single data line), is not limited to using
DDR on a single data pin, given further that Inagaki disparages “increasing”
“a multi-bit” pin width. (See id.; I1.) In general, Inagaki’s “invention
presents block access memory that transfers data with a speed that is twice
the conventional speed.” (Inagaki 3.) That generic teaching, for data, is not
limited to DDR on a single data line or pin, even if Inagaki’s disclosed
embodiments may be so limited.
Moreover, the difference between what the iAPX system does and
what claims 3 and 26 recite relates materially only to Inagaki’s DDR. See
Ayst Tech., Inc. 544 F.3d at 1310 (emphasis added) (“While the evidence
shows that the overall system drew praise as a solution to a felt need, there
was no evidence that the success of the commercial embodiment of the . . .
patent was attributable to the substitution of a multiplexer for a bus, which
was the only material difference between Hesser and the patented
invention.”) Similarly, no evidence shows that substituting Inagaki’s DDR
function for iAPX’s similar clock function, the only “material difference
between [iAPX] and the patented invention,” would have drawn the praise
or success, or solved the problem, advanced by Rambus as showing
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unobviousness. The DDR simply would have doubled the iAPX data speed,
in a predictable manner––i.e., as Inagaki specifically predicts.
7. Related Rambus Proceedings Show Speed Related to Other
Features
The Federal Circuit recognizes the importance of speed in Rambus
devices, and notes the additional use of a multiplexed bus in related Rambus
patents. See Rambus Inc. v. Infineon Technologies AG, 318 F.3d 1081,1095
(Fed. Cir. 2003) (“The present invention is designed to provide a high speed,
multiplexed bus”) (internal quotations and citations omitted, emphasis
added).) In another case involving a related Rambus patent, the Federal
Circuit determined that access-time registers in DRAM memory devices to
store delay values helped to solve the memory bottleneck problem. See
Rambus v. Rea, 527 Fed.Appx. 902, 903-905 (Fed. Circ. 2013)
(unpublished).
As the Federal Circuit cases show, different inventive aspects, which
are not claimed here, contribute to the touted speed functionality. In
addition to the multiplexed bus and access-time registers noted by the
Federal Circuit, Rambus argued about other speed inducing features in
related proceedings.
In another related reexamination proceeding, PTAB 2012-001639,
Rambus argues that “the success was because of the claimed features
[recited there, but not here], such as the claimed operation code including
precharge information.” (See Rambus Reh’g. Req. 30 (Oct. 31, 2012)
(reexam. control nos. 95/001,109 & 95/001,155) (emphasis added). Claims
3 and 26 do not recite the touted precharge feature.

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8. Licensing
Rambus-Rea found, on the limited record, that Rambus licenses
“linked its commercial success to the claimed dual-edge data transfer
functionality.” Id. at 1257. Ordinarily, “[t]he mere existence . . . of licenses
is insufficient to overcome the conclusion of obviousness.” Sibia
Neurosciences, Inc. v. Cadus Pharm Corp., 225 F3d. 1349, 1358 (Fed. Cir.
2000) (“three licenses . . . of the ’629 patent, all of which were part of larger
licensing packages,” does not show nexus); see also Pentec, Inc. v. Graphic
Controls Corp., 776 F.2d 309, 316 (Fed. Cir. 1985); EWP Corp. v. Reliance
UniversaI Inc., 755 F.2d 898, 907-09 (Fed. Cir. 1985); Iron Grip Barbell
Co., Inc. v. USA Sports, Inc., 392 F.3d 1317, 1324 (Fed. Cir. 2004).
In Iron Grip, 392 F.3d at 1324, the court noted that competitors may
simply take a license “‘because it is often “cheaper to take licenses than to
defend infringement suits.’” Id. (quoting EWP Corp. v. Reliance Universal
Inc., 755 F.2d 898, 908 (Fed.Cir.1985).). The court held that “two . . . taken
in settlement of litigation” fails to show nexus and that “the existence of
licenses is of little significance.” Id.
In In re GPAC Inc., 57 F.3d 1573, 1580 (Fed.Cir.1995), the court
found that “in affidavits reciting the license history of the ’111 patent,
GPAC did not establish which claims(s) of the patent the licensing program
incorporates, GPAC has not shown that licensing of Natele’s invention arose
out of recognition and acceptance of the subject matter claimed.”
Rambus-Rea found error in the Board’s reasoning that competitors
typically take licenses for reasons unrelated to obviousness, and found
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factually that the limited record suggested otherwise. Based on Rambus’s
arguments and citations to the Federal Circuit, Rambus-Rea relied partially
on the EET article discussed above that Rambus attached in Appendix L of
its Appeal Brief to the Board. Rambus did not cite that article to the Board
to show licensing. (See App. Br. 29 (discussing licensing under Commercial
Success).)
18
Rambus does not specify claims in an affidavit as GPAC
requires.
The EET article, discussed at Rambus-Rea, 731 F.3d at 1257, states
that “the other key part of the Rambus idea is the memory bus” that “moves
one byte on each clock edge.” Rambus-Rea links this statement with another
statement in the article that three (Japanese) companies had paid “substantial
license fees to participate in the technology.” The court also found that
nothing in the record showed that “the commercial value of the licenses
stemmed from other licensed Rambus patents.” Id. The court also indicated
that another reference, the FTC Initial Decision described above, evidences
licenses by Hitatchi, Ltd., Oki Electric Industry Co., Lucky Goldstar, and
Intel Corp. Id. at 1257. Rambus’s Appeal Brief to the Board also does not
mention the FTC Initial Decision in a licensing connection or otherwise, but

18
In the main body of its Appeal Brief to the Board, in another context,
Rambus cited five (out of 30 articles which Rambus listed and attached in an
appendix Exhibit L) by listing five “R” numbers as showing an existing
prior art memory bottleneck problem, without mentioning any other context
or specific point about those articles. (App. Br. 28.) Rambus’s citation and
limited statement to the Board follow: Dr. Farmwald “recognized that these
trends would result in a memory bottleneck, where memory technology
would limit computer system performance. (See id.; see also Murphy Decl ¶
28; see also Ex. L at R39338, R39340, R39343, R39344, R39362,
discussing memory bottleneck.).”
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mentions these and other companies as “[o]ther licensees,” and implies they
may have “licensed the technology disclosed in the Farmwald Family” of
patents. (See App. Br. 29.) Rambus pointedly fails to name a specific
company that has a license to the ’097 patent, let alone a remanded claim in
that patent. (See App. Br. 29.)
The Board herein points to other counter evidence. Only the
remanded claims in the ’097 patent are at issue. Rambus fails to explain,
with evidence, which specific claims, if any, remain as a license subject, as
GPAC requires. Further, the ’097 patent did not issue until July 10, 2001.
Therefore, the record does not show how Rambus could have licensed any
“patent” claims to the three Japanese companies in 1992 when the EET
article was published. According to the prosecution history, even if Rambus
had a contract to license future claims that had not issued, the patent
application was filed as a continuation with preliminary amendments drawn
to the DDR technology on February 28, 2001, about nine years after the
article. (See USPTO EDAN App. No. 09/252,998 “Preliminary
Amendment” (Feb. 28, 2000).) Rambus’s related patent, U.S Patent No.
5,513,327 (Apr. 30, 1996), specifically claims these first and second input
receivers, and an internal clock, to handle DDR, in a “DRAM.” Perhaps
these narrower claims in the ’327 patent were the subject of a license to the
Japanese companies. Rambus does not state either way.
Other evidence shows that Rambus licensed “trade secrets.” (FTC
21.) Rambus has not met the burden, on this record, under Iron Grip, and
other cases, to explain how the licenses mentioned in the article pertain to
the claims at issue.
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Rambus’s Appeal Brief before the Board specifically admits to
multiple patents involved in the licensing: “For instance, in addition to the
significant sales of products embodying the claimed inventions, the
Farmwald Family, which includes the ’097 patent, has numerous licenses.”
(App. Br. 29 (emphasis added).) This ambiguous statement only admits that
the Farmwald Family has licenses. Rambus describes “numerous patents in
the Farmwald Family.” Id. (emphasis added). Rambus also explains that
“Samsung, which has requested reexamination of numerous patents in the
Farmwald Family, took a five-year license under the Farmwald Family as
applied to synchronous DRAM devices in October 2000, and recently took
another license to the Farmwald Family, among other patents.” Id.
(emphasis added). Rambus’s further admission that Samsung took licenses,
and also challenged numerous patents in the same Farmwald Family, shows
that licensees (e.g., Samsung) knew there were different types of Farmwald
Family licenses and patents, and implies that Samsung had different reasons
either to challenge the patents or to take licenses.
Rambus does not specify what any of the alleged licenses include, by
declaration or even argument. For example, if the licensees paid fees for the
anticipated claims in the ’097 patent, it is not clear how such a payment for
broad anticipated claims shows unobviousness. Rambus has not met its
burden under Iron Grip and GPAC of showing nexus, including whether or
not the three Japanese companies mentioned, paid for a license to the ’097
patent, let alone a remanded claim therein, and the reason behind it.
The EET article is a report about a “Rambus announcement.” (EET,
see R39347, Ex. L, App. Br.) In other words, Rambus, again, is a source of
the article. The article states that “[t]he announcement included not only
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Rambus’s unique channel, but plans for Rambus-specific DRAMs, ASICs
and microprocessors from Fujitsu Ltd., NEC Corp., and Toshiba Corp. The
three Japanese companies have worked closely with the startup, and have
paid substantial license fees to participate in the technology.” Id. These
companies, who worked with Rambus, “desperately want[ed] a way to
differentiate themselves from the commodity DRAM market.” (Id. at R39348
(emphasis added).) The EET article states that “reports have put the license
fee as high as $2.5 million each.” Id.
The EET article does not state whence the “reports” came, only that
Rambus is its source. The article does not tie a license to any particular
patent claim, or even a patent. It appears that microprocessor and ASIC
inventions also may have been involved. The article states a reason for the
licenses, the companies were “desperat[e]” to stay in the DRAM market.
Even if the third-hand reports, including reports by Rambus, can be
credited, paying $2.5 million to stay in the DRAM market, by companies
desperate to stay in the market for the most popular chip known, a DRAM,
indicates that the licenses may have been due to the popularity of DRAM
chips, which the claims cover, but do not require.
19
See In re DBC, 545 F.3d
1373, 1384 (Fed. Cir. 2008) (“Nor is there any evidence that sales of
XanGo
TM
juice were not merely attributable to the increasing popularity of
mangosteen fruit or the effectiveness of the marketing efforts employed.)
Under DBC, Rambus has the burden to explain the typical value of a license

19
See Wicklund et al., U.S. 5159,676, col. 1, ll. 36-37 (Oct. 27, 1992) (“At
the present time, the most popular form of read/write memory is the
semiconductor DRAM . . . .); see also FTC, 16 findings (finding 66,
discussing the “large size of the DRAM market”).
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in the DRAM market, and compare that to any license it may have sold for
the ’097 patent. See id. (“Based on this increasing popularity, [the Board]
observed that there was no evidence comparing the growth in sales of
XanGo™ to the growth in sales of mangosteen juice in general.”) In DBC,
evidence showed gross sales of $130 million, here the license fee involves
$2.5 million and desperate DRAM partners in a popular DRAM market
(assuming arguendo that the fee is for the ’097 patent).
The EET article also states that “Fujitsu plans an ASIC
implementation of the Rambus master later this year.” (App. Br., Ex. L.,
R39348.) It also states that Fujitsu plans to implement a Rambus DRAM in
the form of “a unique plastic package that mounts astride the Rambus strip
line.” (Id.) NEC “will develop a system based on the Rambus architecture.”
(Id.) The Rambus master, the ASSIC implementation, the plastic package,
and the system point to other unclaimed Rambus inventions. The claims at
issue here also do not recite a system that “moves one byte on each clock
edge,” which the article mentions. On its face, it does not appear from the
article that the described methods or devices there were the subject of any
alleged licenses that are tied to any specific claim in the ’097 patent.
Even if the article somehow implicates Rambus patents with DDR,
many of Rambus’s Farmwald Family patents involve the DDR functionality.
(Rambus had filed 80 patent applications by 1994, as discussed further
below.) One example includes the predecessor patent, with narrow DDR
DRAM claims, noted above. Another includes Rambus U.S. 6,304,937,
which is currently on remand from the Federal Circuit due to a joint motion
by Rambus and the PTO to consider similar issues raised here. (See In re
Rambus, Inc., PTAB 2013-004540 (Reexam. Control 95/001,188).) Still
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other reexaminations involve DDR, including the reexamination that
discusses precharge cited above. In most, if not all, the myriad of cases
appealed to the Board, Rambus submitted virtually the same secondary
considerations of nonobviousness as submitted here.
The court also notes that “Rambus also obtained licenses from
Hitatchi, Ltd., Oki Electric Industry Co., Lucky Goldstar, and Intel Corp.
J.A.2099.” Rambus-Rea, 731 F.3d at 1257 (citing the FTC Initial Decision).
The cited page, in the FTC Initial Decision, does not show what patent is
involved in any licenses. It states that the licenses were obtained “by June
1992.” (FTC 21.) The page states that Rambus “had entered into license
contracts that compelled Rambus partners to use Rambus technology patents
and trade secrets only for use in RDRAM-compatible chips.” (Id. (emphasis
added).) It also mentions “technology license agreements” with the three
Japanese companies discussed in the EET article: NEC Corp. (“NEC”),
Toshiba Corp. (“Toshiba”), and Fujitsu Laboratories, Ltd. (“Fujitsu”). It
states that “Rambus had filed for, but not yet obtained, a base patent on its
technology.” (FTC 21.)
In other words, the licenses include “trade secrets” and “Rambus
technology patents” that had not yet issued in 1992, the date of the EET
article. Further, by August, 1996 Rambus had filed 80 patent applications
and 16 patents had issued. (FTC 37.) According further to the FTC
findings: “Rambus has obtained patent claims that cover programmable
CAS latency, variable burst length, dual-edge clocking, and on-chip DLL as
those features are used in SDRAMs and/or DDR SDRAMs. (Complaint,
¶ 91). Rambus has asserted claims covering these four features against
SDRAMs and DDR SDRAMs. (Complaint ¶ 92).” (FTC 37.)
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Four years after the article about licensing, in 1996, Rambus had
obtained licenses for trade secrets, and had patent claims covering a wide
variety of broad inventions, which involved modified DRAMs. Rambus
does not state who licensed the ’097 claims or why they did it. In its Federal
Circuit Brief, Rambus argues that it “settled” the instant matter with
NVIDIA, perhaps attempting to imply a license by NVIDIA for the ’097
patent. (Fed. App. Br. 43.) This argument does not show NVIDIA has a
license, the terms, or the reason, and fails to show a nexus under Sibia
Neurosciences, GPAC, and Iron Grip.
Rambus also refers to Mr. Murphy’s declaration, which states the ’097
patent has many licenses. (Fed. App. Br. 44.) Mr. Murphy does not state
the basis for his belief or describe the terms or circumstances involving any
such license or the ’097 patent: “The industry has accepted the inventions
disclosed and claimed in the ’097 patent, as shown by the numerous
companies that have licensed the inventions claimed in that patent, as well as
those claimed in other patents derived from the ’898 application.” (Murphy
Decl. ¶ 29 (emphasis added).) The statement lacks corroboration or
specificity to any claim on remand.
Rambus lists other licenses in its Federal Circuit brief but does not
argue, let alone show, that a single company has a license to a remanded
claim in the ’097 patent, or the circumstances surrounding the license. (See
Fed. App. Br. 42-41.) Iron Grip requires an evaluation of how these myriad
licenses for possibly over 80 patents show a nexus to the claims at issue
here. Rambus does not “explain the terms of the licenses nor the
circumstances under which they were granted,” as applied to the claims at
issue here, as Iron Grip, 392 F.3d at 1324, requires.
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With further regard to licenses, the FTC discusses Rambus’s strategy:
72. As a 1989 draft business plan explained, Farmwald
and Horowitz hoped to establish a de facto standard by offering
all interested DRAM and central processing unit (“CPU”)
vendors a sufficiently low licensing fee (2%) that it will not be
worth their time and effort to attempt to circumvent or violate
the patents.” (RX 15 at 9).
(FTC 17 (emphasis added).)
This “sufficiently low licensing fee” contradicts the characterization
of the “reported” “significant” fees of $2.5 million, otherwise touted in the
EET article involving Rambus press announcements. According to
Rambus’s business plan, it also provides a reason to obtain a license
unrelated to obviousness: “it would not be worth their time and effort to
circumvent the patent.” (Id. at 16.) Other reasons appear in the FTC record:
Rambus’s market strategy was to convince chip makers that the Rambus
technology would become a standard, and that “charg[ing] lower royalties
. . . [would] foster acceptance.” (Id. at 18.)
The FTC further found the following related Rambus licensing
strategy:
67. To become and remain a viable company, it intended to
charge low single digit royalties, which it believed to be fair in
light of the importance of Rambus’s intellectual property
contribution to the product and the large size of the DRAM
market. (Farmwald, Tr. 8128; Cf (1282 at 5).
(Id. at 17 (emphasis added).)
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The “large size of the DRAM market,” the popularity of DRAMs, the
low licensing fees, such fees set to avoid litigation, and the desperate DRAM
partners, each constitute valid reasons to license the technology, apart from
obviousness. The claims do not recite DRAMs or modified DRAMs.
The FTC also found that “[p]art of [Rambus’s] early strategy . . . was
to pursue an application for ‘a basic, broad patent filed in all major
industrial nations’ and thereafter ‘follow up with additional patents on
inventions created during the development of the technology.’” (Id. at 16.)
It is not clear, on this record, how providing inexpensive licenses to broad
patent claims and trade secrets to desperate partners in a large DRAM
market, shows unobviousness. The record does not show a nexus between
the remanded claims and any alleged license.
9. Multiple Inventions––FTC
Corroborating the Boards findings, the FTC also describes the
following multiple inventions and Rambus’s strategy for marketing:
62. Rambus’s founders intended to improve memory
performance through multiple inventions based on
modifications of standard DRAMs (see CX 533 at 2), which
could be used separately or in combination(s). The greatest
performance gains would be realized by using these inventions
in combination. Rambus DRAM or “RDRAM” is the name for
the “revolutionary DRAM architecture and high speed chip-to-
chip data transfer technology” that incorporates several of
Rambus s inventions, including its proprietary bus technology.
(RX 81 at 3). Each of the various generations of RDRAM are
manufactured in accordance with specifications established
through a collaboration among Rambus and its DRAM partners.
(Farmwald Tr. 8149, 8241).
(Id. at 16 (emphasis added).)
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The FTC findings largely coalesce with and serve to summarize
similar findings on this record:
86. The RDRAM technology in the early 1990’s included
numerous inventions relating to the bus, the interface between
the bus and computer chips, and the DRAM. The 1992
Corporate Backgrounder makes clear that the Rambus “solution
is comprised of three main elements: the Rambus Channel, the
Rambus Interface, and the RDRAM.” (RX 81 at 6). The
Rambus Channel refers to the bus, while the Rambus Interface
and RDRAM refer to other Rambus innovations separate from
the bus. (RX 81 at 7). Each of these elements contain a number
of independent inventions. (RX 81 at 8- 11).

87. RDRAM narrow bus technology contemplates the use of
circuitry on the chips at either end of the bus connection to
optimize the signals flowing across the connection. (Horowitz,
Tr. 8488-90). This circuitry contains high-level logic which
implements a protocol for the chip-to-chip information transfer.
(Horowitz, Tr. 8489-90).

88. One of the ways that RDRAM technology achieves a high-
speed data transfer over the narrow bus is through
“multiplexing,” which means that the bus can carry different
pieces of information at different points in time. (Horowitz,
Tr. 8620-21). This aspect of the RDRAM interface protocol
means that over several clock cycles the bus can carry a
combination of address and control and data signals on one or
more of the same bus lines. (Horowitz, Tr. 8620-21; see
Rhoden, Tr. 402-03).
(Id. at 19.)
Hence, according to the FTC, Rambus’s main inventions each contain
a number of different inventions. The FTC’s description of the “Memory
Interface Protocol” follows:
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54. With respect to the design of the protocol, additional
optimizations developed for high speed operation included
returning a variable amount of data in response to a request
rather than a single bit of data and by putting registers and
associated control circuitry directly on the DRAM. (Farmwald,
Tr. 8115; Horowitz, Tr. 8489-90).

55. With respect to the protocol, Drs. Farmwald and Horowitz
again came up with various innovations. As one example, they
decided to put registers on the DRAM to make the interface
more efficient. (Farmwald, Tr. 8115- 16; Horowitz, Tr. 8506).
These registers would be programmed with parameters, such as
the address range that a particular DRAM would respond
to or the access time of the DRAM. (Horowitz, Tr. 8507, 8509-
10).

56. Drs. Farmwald and Horowitz wanted to make the access
time variable for two reasons. First, if the bus were improved
so that it could operate at a faster clock frequency, the access
time of the DRAM could be adjusted so that it would operate
with that faster clock. Second, a variable access time would
allow the access times of all the DRAMs in a system to be
adjusted to have the same access time. (Horowitz, Tr. 8510-
11).
(Id. at 15.)
The FTC noted “four . . . technological features,” including DDR
clock circuitry, and DLL (delay-locked loop) on-chip––in the DRAM
interface, as part of the combined features for operating at 500 MHz:
111. The May 7, 1990 technical description described all four
of the technological features at issue in this case. (Horowitz,
Tr. 8525-29).

112. For example, the technical description described dual-
edge clocking in a figure with two input receivers, one clocked
by a signal designated “CLK” (clock) and the other clocked by
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the complement of CLK (clock bar), a signal that is zero when
clock is one and vice versa. (R 63 at 10; Horowitz, Tr. 8525-
26). This means that one receiver samples an input when the
clock goes high (the rising edge of the clock) and the other
when the clock goes low (the falling edge). (Horowitz,
Tr. 8526).

113. The May 7, 1990 technical description also described a
delay-locked loop on the DRAM (on-chip DLL feature).
(Horowitz, Tr. 8527-28). A figure in the technical description
shows two delay locked loops generating the internal clocks for
Rambus s design. (RX 63 at 14; Horowitz, Tr. 8527).

(Id. at 23 (emphasis added).)

138. [According to a public document by Rambus] . . . [t]he
technology descriptions included the use of dual-edge clocking:
“(a)n innovative electrical interface permits the Rambus
Channel to operate at 500 Megabytes/second by using both
edges of a 250 clock.” (RX 81 at 8). Moreover, the technology
descriptions explicitly state that Rambus used the on-chip
PLL/DLL technology: “(c)lock skew and capacitive loading are
minimized by a phase lock loop circuit on board both the
master and the RDRA.” (R 81 at 8).

(Id. at 26 (emphasis added).)
The FTC findings also point to a Rambus 1992 marketing brochure
that states that the “heart of (the Rambus) Interface is high performance PLL
(phase-locked-loop) circuitry which provides the clocks for transmitting and
receiving Rambus Channel data.” (Id. at 27.) Another article cited by the
FTC states that the “Rambus Channel is a 500-Mbyte/s interface, operating
with a 250-MH clock and transferring a byte of data on each clock edge”
and that a “phase-locked loop on each Rambus device limits clock skew
within the chip.” (Id.)
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These FTC facts coalesce with the record here. The record shows that
Rambus, which appears to be a successful and innovative company, touted
many of its inventions, which, in 1996, involved over 80 patents, some of
which may have involved DDR DRAMs, although any licensing appears to
have included trade secrets. The record shows that a combination of
unclaimed features is required to support the touted speeds, primarily, the
interface circuitry in a DRAM chip. For example, paragraph 112 supports
the Board’s finding above and indicates that the DRAM chip interface at
least needs to have “two input receivers” to support the DDR. Paragraphs
113 and 138 show that some type of delay lock or phase lock loop, to correct
skew in high speed clocks, implements DDR at 500 MHz. Paragraphs 54–
57 imply the requirement of at least four different facets to support or
enhance speed touted in different articles.
10. Multiple Inventions Disclosed -Murphy Declaration
Mr. Murphy’s declaration bolsters the voluminous record that shows
that that many inventions were involved in any touted success, praise or
other indicia, and that the synchronous interface was an important feature.
Mr. Murphy states that the “inventions disclosed” were “very successful.”
(Murphy Decl. ¶ 28.) Mr. Murphy cites faster memory, and states that other
skilled artisans were unsuccessful “without using the synchronous interface
and related inventions disclosed in the ’898 application.” (Id. at ¶ 30
(emphasis added).) Mr. Murphy states that in addition to the ’097 Patent,
“other patents based on the ’898 application, have been instrumental in
increasing DRAM performance.” (Id. at ¶ 28.)
As another specific example included in these other patents, Mr.
Murphy explains that one such invention pertains to a Delay Locked Loop
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(DLL), which “achieves better performance” in the system and “improves
timing margins.” (Id. at ¶ 26.) Mr. Murphy states that yet another
(unclaimed) function improves speed: “access time information improves
the speed and efficiency of the overall system.” (Id. at ¶ 27.) Mr. Murphy
also states that the disclosed invention in the ’097 Patent employs two
clocked input receivers to perform the DDR function. (See id. at ¶ 39.) Mr.
Murphy also implies that success was due not only to memory devices:
“memory controllers . . . employ features that are claimed in the ’097 patent”
and attempts by others “to create faster memory controllers” were
unsuccessful. (Id. at ¶ 39.)
11. The Micron Website
To show success due to DDR, Rambus also newly cited Micron‘s
advertisement of DDR SDRAMs, in Rambus’s Federal Appeal Brief.
Rambus does not direct the Board to where it discussed this with the
Examiner or the Board (or even list in the attached voluminous “Evidence
Appendix”––the working file is currently 342 Mbytes). Rambus-Rea directs
the Board to respond to it: “A press release issued by Micron Technology,
Inc., a Rambus competitor, referred to the dual-edge data transfer
functionality as a ‘revolutionary and pioneering technology’ that ‘vastly
improv[ed]’ the performance of memory chips. J.A. 1711. The Board did
not address any of this evidence.” 731 F.3d at 1257 (quoting the website).
The Micron website now states, in part, the following:
When we introduced our DDR SDRAM, it was
revolutionary and pioneering technology. DDR allows
applications to transfer data on both the rising and falling edges
of a clock signal, doubling bandwidth and vastly improving
performance over SDR SDRAM. To achieve this functionality,
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we use a 2n-prefetch architecture where the internal data bus is
double the size of the external data bus, so data capture can
happen two times each clock cycle.
See http://www.micron.com/products/dram/ddr-sdram (attached in
Appendix) (emphasis added).
This evidence shows that Micron touted DDR functionality as
revolutionary in a synchronous DRAM––a single chip. The claims at issue
do not require a single chip. As found above, Inagaki already used DDR in a
synchronous RAM. Whatever the website implies, it was not revolutionary
to put a DDR feature in a generic synchronous memory device, as
anticipation by Inagaki proves. Therefore, the website amounts to sales
puffery about Micron’s specific implementation of DDR in a DRAM chip.
Moreover, “to achieve this [DDR] functionality,” Micron employs “a
2n-prefetch architecture where the internal data bus is double the size” of the
external data bus. See id. Micron’s website also notes speeds of up to
400MHz with clocks at 200MHz. Id. The website bolsters the findings
noted above that DDR, and especially DDR at high speeds, requires some
chip interface or hardware architecture to enable that functionality, what
appears to include 400 MHz speed in Micron’s chip using a 200MHz clock.
See id. The ‘097 patent claims do not recite anything like this required chip
hardware that Micron describes as helping to enable the touted speeds.
Micron’s website bolsters the finding of a lack of nexus, because it shows
that DDR requires specific hardware, as does the touted speed, touted in
combination with DDR, neither of which Rambus’s claims require.

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12. Reasonably Commensurate in Scope
In addition to showing nexus, Ramus must show that its evidence of
unobviousness is “reasonably commensurate” with the claim scope. On the
other hand, Rambus need not “produce objective evidence on
nonobviousness for every potential embodiment of the claim.” Rambus-Rea,
731 F.3d at 1257 (citing In re Kao, 639 F.3d 1057, 1068 (Fed. Cir. 2011).
As discussed above, Rambus-Rea indicated that, on the record before it,
Rambus’s evidence was reasonably commensurate in scope with the claims
because “the claimed dual-edge data transfer functionality is what enabled
the praised high-speed transfer of data.” Id. Rambus-Rea reasoned that, on
the record before it, the Board “did not point to any contrary evidence.” Id.
Contrary findings are discussed above and further below. In summary
to the above, anticipation by Inagaki, and the findings above, show that a
typical DDR memory device, without more, cannot enable the high speeds
touted. At a minimum, a single chip DRAM or other single chip, with
Rambus’s (or similar) modified interface circuitry, including at least the
receiver circuitry, must be recited in the claims at the least to enable the
touted speeds and praise, and to solve any bottleneck problem. Skepticism
or disbelief involves putting PLL or DLL circuits in the DRAM interface to
handle high speeds.
Similar to Therasense, in In re Tiffin, 448 F.2d 791 (CCPA 1971), the
court found that claims that are “too broad” fail to show that the claims are
reasonably commensurate with the scope of the objective evidence of non-
obviousness: “The solicitor's position is that the objective evidence of non-
obviousness is not commensurate with the scope of claims 1–3 and 10–16,
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reciting ‘containers’ generally, but establishes non-obviousness only with
respect to “cups” and processes of making them. We agree.” Id. at 792.
By analogy, following Tiffin (and Therasense) means that even if
Rambus shows non-obviousness for the disclosed, but unclaimed five- to
ten-fold speed capability in a modified DRAM chip (analogous to a cup in
Tiffin), Rambus’s claim 3 and 26 are “too broad,” because they embrace
unmodified, slow, DDR multi-chip memory devices (analogous to a
container generally in Tiffin) that did not inherently require or even enable
fast speeds or solve any prior art problem. In a similar case, the court held
that evidence of commercial success of dockboards having a bead could not
show success for claims that did not recite a bead. In re Law, 303 F.2d 951,
1162 (CCPA 1961) (“Thus, assuming the affidavits are a proper showing of
commercial success, they do not show commercial success of dockboards
covered by the appealed claims which are not limited to the bead of claim
13.”)
Subsequent to Rambus-Rea, the Federal Circuit made a similar ruling
to that in Tiffin and Law. In MeadWestVaco Corp. v. Rexam Beauty and
Closures, Inc., 731 F.3d 1258 (Fed. Circ. 2013), the court held that a district
court erred by considering “secondary considerations of non-obvious [that]
involved only fragrance-specific uses, but the claims now at issue are not
fragrance-specific.” Id. at 1264 (emphasis added). The claims here
analogously are not “speed-specific,” but the relied-upon evidence is.
MeadWestVaco held error because the district court “credited
evidence advanced to show long-felt need and commercial success specific
to the perfume industry,” and the claims were not limited to fragrance-
specific dispensers. See id. (reasoning that “‘objective evidence of non-
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obviousness must be commensurate in scope with the claims which the
evidence is offered to support’”)(quoting Ayst Techs., Inc. v. Emtrak, Inc.,
544 F.3d 1310, 1316 (Fed. Cir. 2008) (internal quote citation omitted).)
Similar to the broad memory device claims here, which do not
preclude or require fast speeds handled by a single chip (e.g., DRAM), the
broad claims at issue in MeadWestVaco did not preclude or require
fragrance-specific uses, the broad claims in Law did not preclude or require
beads, the broad claims in Tiffin did not preclude or require cups, and the
broad claims in Therasense did not preclude or require devices that solved
the short fill problem.
Further, in MeadWestVaco, although the court did not discuss the
issue of inherency or enablement in terms of the relied upon objective
evidence of obviousness, the “dispenser assembly for dispensing a liquid”
recited in claim 15 necessarily could have carried (i.e., “enabled”) a
fragrance-specific liquid, because it recited a generic dispenser: “[S]ome of
the claims . . . are specific to fragrance dispensers and others are directed to
generic dispensers.” Id. at 1262. Therefore, it appears that the claimed
dispenser “enabled” the dispensing of fragrance-specific liquids, because it
could dispense generic liquids. Nevertheless, because the commercial
success and other evidence were “fragrance-specific,” claims 15 and 19 were
not commensurate in scope with the evidence: Claims 15 and 19 did not
require “fragrance-specific” dispensing. Id.
Here, claims 3 and 26 are not “speed-specific”; moreover, they do not
even enable the touted five- to ten-fold speed increase, unlike the enabling
dispenser claims in MeadWestVaco, which still were too broad. Even
though DDR enables twice the speed, DDR is in the prior art of Inagaki, and
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claims 3 and 26 do not enable the touted 250-500 MHz DRAM speeds.
Under MeadWestVaco and Therasense, simply allowing for fast speeds (like
fragrance specific liquids) is not enough, if the claims do not require the
speed (or something close to it). At the least, on this record, the claims must
enable the touted speed, as Rambus-Rea suggests, and they do not. Without
a claimed receiver chip interface (setting aside the required short bus
lengths, and DLL or PLL), the touted speeds are not enabled because DDR
only doubles the speed, and the touted speeds are not inherent. Nothing
recited in the claims enables, let alone requires, a five- to ten-fold speed
increase. In summary, the claims here are broader relative to those deemed
to be too broad in MeadWestVaco. Rambus chose not to recite speed range
functionality or structure enabling or requiring that speed. A long line of
precedent dictates that Rambus, without reciting structure or functionality
enabling or pertaining to something close to the touted speed, cannot rely on
the evidence of unobviousness touting that speed.
Kao relies on Tiffin and provides further guidance:
Evidence of secondary considerations must be
reasonably commensurate with the scope of the claims. See In
re Tiffin, 448 F.2d 791 (CCPA 1971)); In re Hiniker, 150 F.3d
1362, 1369 (Fed.Cir.1998). This does not mean that an
applicant is required to test every embodiment within the scope
of his or her claims. If an applicant demonstrates that an
embodiment has an unexpected result and provides an adequate
basis to support the conclusion that other embodiments falling
within the claim will behave in the same manner, this will
generally establish that the evidence is commensurate with
scope of the claims.
Kao, 639 F.3d at 1068 (emphasis added).
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Therefore, Rambus must “demonstrate[] that an embodiment has an
unexpected result [or commercial success] and provide[] an adequate basis
to support the conclusion that other embodiments falling within the claim
will behave in the same manner.” Id. (emphasis added).
Rambus has not produced a persuasive reason explaining why
memory devices falling in the broad claim scope, DDR devices with block
information or synchronous operation codes, which do not support the touted
speeds (because they lack receiver interface circuitry to enable the high
speeds), would be expected to be similar to any commercial device in terms
of success, praise, satisfaction of a long-felt need, or high-speed
functionality. This rationale coalesces with the holding in Therasense,
which downplays evidence if the claims “are broad enough to cover devices
that either do or do not solve the [relied upon] problem.” Therasense, 593
F.3d at 1336 (emphasis added).
As Therasense reasons:
Because the claims are broad enough to cover devices
that either do or do not solve the “short fill” problem, Abbott's
objective evidence of non-obviousness fails because it is not
“commensurate in scope with the claims which the evidence is
offered to support.” In re Grasselli, 713 F.2d 731, 743
(Fed.Cir.1983); see also In re Kubin, 561 F.3d 1351, 1356
(Fed.Cir.2009) (“[T]he obviousness inquiry requires this court
to review the Board’s decision that the claimed sequence, not
appellants’ unclaimed cloning technique, is obvious in light of
the abundant prior art.” (emphases added)).
Id. (first sentence emphasis added).
Like Therasense, Kao provides a practical limit for the breadth of a
reasonably commensurate claim: “As this court recently explained, ‘[i]t
seems unlikely that a company would sell a product containing multiple,
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redundant embodiments of the patented invention. . . . Under the [Office’s]
logic, there would never be commercial success evidence for a claim that
covers more than one embodiment.’ In re Glatt Air Techniques, Inc., 630
F.3d 1026, 1030 (Fed.Cir.2011).” Kao, 639 F.3d at 1069.
This case does not involve any redundant embodiments. Kao protects
“redundant embodiments” or reasonably close embodiments within a claim
scope. Similar to the reasoning in Rambus-Rea, Kao also reasoned that
“[t]he Board’s refusal to credit the applicant’s evidence of commercial
success because it was not proven across the entire claimed range of
dissolution rates was improper.” Id. Kao also reasoned that an applicant
“need not sell every conceivable embodiment of the claims in order to rely
upon evidence of commercial success, so long as what was sold was within
the scope of the claims.” Id. (emphasis added).
In context to the cited precedent, including Tiffin, Kao’s references to
“redundant embodiments” and “sell[ing]” imply that a reasonably
commensurate claim scope protects embodiments that would have behaved
similarly, in a beneficial manner, to the touted marketed device. This is
similar to what Rambus-Rea directs the Board to determine in terms of
devices that enable speed. Rambus does not argue that its licensees
contemplated selling slow, DDR, multi-chip, memory device embodiments,
which conceptually fall in the claim scope, but that lack the capability (i.e.,
the chip receiver interface) for higher speeds. Cf. Brown & Williamson
Tobacco Corp.., 229 F.3d 1at 1130 (look at any success “if the marketed
product embodies the claimed features, and is coextensive with them.”)
Showing success for a commercial embodiment, like a modified
DRAM capable of high speeds, within a claim scope that does not recite,
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inherently require, or even enable the touted high speeds, is not sufficient to
rebut obviousness across the whole claim scope, because Kao did not
overrule Tiffin, Law, and Therasense. By further analogy, Tiffin’s
commercial cup embodiment was in the scope of the broad “container”
claims. Nevertheless, the court held that evidence of successful “cup” sales
was not “commensurate in scope with the [container] claims which the [cup]
evidence is offered to support.” See Tiffin, 448 F.2d at 792.
In terms of Kao’s rationale, Tiffin’s broad containers were not
“redundant embodiments of the [cup] invention.” Analogously, a DDR-
modified iAPX memory module is not a redundant, or reasonably close,
embodiment to a touted interface-modified single chip DDR DRAM with
five- to ten-fold high speed capability, even though both fall within the claim
scope. Showing unobviousness for the latter disclosed, but unclaimed
device, does not show the unobviousness for the former. Focusing on what
the claims cover, Rambus does not supply a reason why a DDR-modified
iAPX module would have been expected to garner the praise, skepticism, or
success, or would have been expected to solve the long-felt need, or would
have been expected to operate similarly in terms of speed or otherwise, to
what Rambus attributes to its disclosed DDR interface-modified DRAMs.
Rambus’s evidence pertaining to skepticism about, praise for, and a
solution by, high speed DDR, interface-modified DRAMs, enabled to run on
125-250 MHz clocks, does not satisfy Therasense, Law, Tiffin, Kao, and
MeadWestVaco for claims 3 and 26 at issue here. Rambus’s analysis
essentially agrees with the Board’s: for evidence of praise to be reasonably
commensurate with the claim scope, the claims cannot cover devices that
solve and do not solve the bottleneck problem. See Rambus Fed. App.Br. 61
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(citing Therasense, 593 F.3d at 1336 (“finding no long-felt need because the
claims were broad enough to cover devices that did not solve the problem”))
(emphasis added, quoting Rambus’s characterization of the case). In any
event, the method claims here do not enable the touted speed. Allowing for,
or not precluding, speed, does not enable the touted speeds, inherently
require it, or create a reasonably close embodiment within the claim scope.

13. Summary
Rambus’s evidence, including, inter alia, commercial success (i.e.,
licenses), praise, skepticism, and solution to a long-felt need, the memory
bottleneck problem, points to unclaimed features, including the use of, or
processing of, high speed clocks, transmitted over short bus lengths, with
synchronous DDR DRAM single chip embodiments having unclaimed
interface features required to obtain the touted speed and solve any prior art
problem. Nothing of record implies or suggests that all DDR memory
devices, including the DDR-modified iAPX memory module, falling in the
scope of claims 3 and 26, would have been successful or solved any long-
felt problem, as the Federal Circuit requires.
Rambus-Rea directs focus on whether the objective evidence relates to
“the claimed invention as a whole.” 731 F.3d at 1258. Not just the DDR
function, but all of claims 1 and 2 are in the prior art. The record does not
show that dependent claim 3 or independent claim 26, which add an
operation code feature and a block information feature, to what is in the
prior art, would have been unobvious. The iAPX system discloses those
features. The record does not show that claims 3 and 26 add significant
Appeal 2012-000171
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Patent 6,260,097

84
features that contribute to success, the touted speed, or other indicia of
unobviousness.
Claims 3 and 26 cover embodiments that are far from being redundant
to, or reasonably coextensive with, Rambus’s disclosed, but unclaimed,
modified-interface, high-speed, DDR DRAM embodiments. Claims 3 and
26 cover devices that both do and do not solve any bottleneck problem. On
this record, Rambus’s proffered unobviousness evidence does not satisfy
Therasense, Tiffin, Law, Kao, and MeadWestVaco. Because this Decision
includes a new ground on remand from Rambus-Rea, Rambus will have the
opportunity to explain why representative claims 3 or 26, or other claims,
have a nexus to the evidence of nonobviousness, and are reasonably
commensurate in scope therewith.
Even if there is some nexus, weak secondary considerations generally
do not overcome a strong prima facie case of obviousness. See Media
Techs. Licensing, LLC v. Upper Deck Co., 596 F.3d 1334 (Fed. Cir. 2010),
cert. denied, 2010 WL 2897876 (Oct. 04, 2010) (“Even if [the patentee]
could establish the required nexus, a highly successful product alone would
not overcome the strong showing of obviousness.”). “The objective
evidence of unobviousness is not evaluated for its “separate knockdown
ability” against the “stonewall” of the prima facie case, In re Rinehart, 531
F.2d 1048 (CCPA 1976), but is considered together with all other evidence,
in determining whether the invention as a whole would have been obvious to
a person of ordinary skill in the field of the invention.” Applied Materials,
Inc. v. Adv. Semiconductor Materials Am., Inc., 98 F.3d 1563, 1570 (Fed.
Cir. 1996).
Appeal 2012-000171
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85
Rambus’s proffered secondary considerations considered together
with evidence of obviousness shows that combining Inagaki’s DDR feature
with iAPX’s memory device system would have yielded the predictable
result of sending data using DDR to double data speed for a given number of
data lines or a given clock speed. Inagaki provides the same motivation for
using DDR that the Rambus inventors used to do the same thing––double
speed in a similar memory device. The Rambus inventors did not invent
using DDR in memory devices, as Inagaki proves. Using the same, well-
known DDR concept in another memory device, the iAPX memory module,
would have been obvious.
CONCLUSION
On this record, considering the evidence of record, and following the
guidance and directive by Rambus-Rea, claims 3–5, 11, 12, 26, 28, 32, and
35 would have been obviousness based on the iAPX (Manual and/or
Specification) and Inagaki. The Examiner’s decision to reject claims 3–5,
11, 12, 26, 28, 32, and 35 is AFFIRMED.
This decision contains new grounds of rejection pursuant to 37 C.F.R.
§ 41.77(b) which provides that “[a]ny decision which includes a new ground
of rejection pursuant to this paragraph shall not be considered final for
judicial review.” Correspondingly, no portion of the decision is final for
purposes of judicial review. For further guidance on new grounds of
rejection, see 37 C.F.R. § 41.77(b)-(g). The decision may become final after
it has returned to the Board. 37 C.F.R. § 41.77(f).
37 C.F.R. § 41.77(b) also provides that the Patent Owner, WITHIN
ONE MONTH FROM THE DATE OF THE DECISION, must exercise one
Appeal 2012-000171
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86
of the following two options with respect to the new grounds of rejection to
avoid termination of the appeal as to the rejected claims:
(1) Reopen prosecution. The owner may file a response requesting
reopening of prosecution before the examiner. Such a response must be
either an amendment of the claims so rejected or new evidence relating to
the claims so rejected, or both.
(2) Request rehearing. The owner may request that the proceeding be
reheard under § 41.79 by the Board upon the same record.
Any request to reopen prosecution before the examiner under 37
C.F.R. § 41.77(b)(1) shall be limited in scope to the “claims so rejected.”
Accordingly, a request to reopen prosecution is limited to issues raised by
the new ground(s) of rejection entered by the Board. A request to reopen
prosecution that includes issues other than those raised by the new ground(s)
is unlikely to be granted. Furthermore, should the patent owner seek to
substitute claims, there is a presumption that only one substitute claim would
be needed to replace a cancelled claim.
Compliance with the page limits pursuant to 37 C.F.R. § 1.943(b), for
all patent owner responses, is required.
The examiner, after the Board’s entry of a patent owner response and
requester comments, will issue a determination under 37 C.F.R. § 41.77(d)
as to whether the Board’s rejection is maintained or has been overcome.
The proceeding will then be returned to the Board together with any
comments and reply submitted by the owner and/or requester under
37 C.F.R. § 41.77(e) for reconsideration and issuance of a new decision by
the Board as provided by 37 C.F.R. § 41.77(f).

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87
AFFIRMED
Patent Owner:

PAUL M. ANDERSON, PLLC
P.O. BOX 160006
AUSTIN, TX 160006

Third Party Requester:

HAYNES AND BOONE LLP
IP SECTION
2323 VICTORY AVENUE, SUITE 700
DALLAS, TX 75219
Appeal 2012-000171
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Patent 6,260,097

88
Attachment
Engineering CirCuit AnalysisSecond Edition
William H. Hayt, Jr.
Professor of Electrical Engineering
Purdue University
Jack E. Kemmerly
Professor of Engineering
California State College, FuJJerton
MCGraw-Hill Book Company
New York

St. louis

Son FrancIsco

Dusseldorf

Johannesburg
Kuala lumpur

london

Mexico

Montreal

New Delhi
Panama
Rio de Janeiro
Singapore
Sydney
Toronto
Engineering Circuit Analysis
Copyright © 1962, 1971 by McGraw-Hill, Inc, All rights reserved,
Printed in the United States of America. No part of this
publication may be reproduced, stored in a retrieval system,
or transmitted, in any form or by any means, electronic,
mechanical, photocopying, recording, or otherwise, without
the prior written permission of the publisher.
Library of Congress Catalog Card Number 70-141920
07-027382-0
234567890 HDBP 7987654321
This book was set in Laurel by York Graphic Services, Inc., printed on
permanent paper by Halliday Lithograph Corporation, and bound by
The Book Press, Inc. The designer was Merrill Haber; the drawings
were done by John Cordes, J. & R. Technical Services, Inc, The
editors were Michael EJia and Madelaine Eichberg, Robert R,
Laffier superVised production,
154 The Transient Circuit
and (t < 0)
= _0.24e-50 ,OOO! (t> 0)
In idealized circuits in which a pure inductance loop is present, such
as that through the 2- and 3-mH coils of Fig. 5-7, a constant current may
continue to circulate as t ~ 00. The current through either of these
inductors is not necessarily of the form, Ae- tlT, but takes the more general
tform, Ai + A 2e- / T This unimportant special case is illustrated by Frob. •
10 at the end of this chapter.
'Ve have now considered the task of finding the natural response of
any circuit which can be represented by an equivalent inductance in series
with an equivalent resistance. The most general RL circuit will be con­
sidered in Sec. 5-7; the analysis is made more complicated because the
response is composed of the sum of a number of negative exponentials.
Drill Problems
5-5 After t = 0, each of the circuits in Fig. 5-2 is source-free. Find expressions
for i and v in each case for t > O.
8t StAns. 2.5e-O. A, _lOe-o. V; 2e-2t A, - 8e-2t V; - 2e-5t A, 20e-5t V
Fig. 5-9 I
to the initiol
ofaneq1.
the RL I
smaller J
approxir
ment it
as exern,
Let 1
circuit (
Fig. 5-9
selectin)
The tot
be zero
Divisio
Equati
shows
equati
nowaJ
forces
expres
resista
155
Fig. 5-8 See Dnll Prob. 5·6
400 n 80 n
(
5-6 For the circuit shown in Fig. 5-8, find: (a) iL(O+); (b) iL(1O-3); (e) i 1(1O-3).
Ans. 54.1; 67.7; 500 mA
s-s THE SIMPLE RC CIRCUIT
The series combination of a resistor and a capacitor has a greater practical
importance than does the combination of a resistor and an inductor. When
an engineer has any freedom of choice between using a capacitor and using
an inductor in the coupling network of an electronic amplifier, in the
compensation networks of an automatic control system, or in the synthesis
:ent, such
rent may
of these
e general
Fig. 5-9 A parallel RC circuit for whICh v(t) is to be determined, subject by Prob.
to the Imtiol condition thot v(O) = Yo.
;ponse of
: in series of an equalizing network, for example, he will choose the RC network over
! be con­ the RL network whenever possible. The reasons for this choice are the
!ause the smaller losses present in a physical capacitor, its lower cost, the better
mentials. approximation which the mathematical model makes to the physical ele­
ment it is intended to represent, and the smaller size and lighter weight
as exemplified by capacitors in hybrid and integrated circuits.
Let us see how closely the analysis of the parallel (or is it series?)RC
circuit corresponds to that of the RL circuit. The RC circuit is shown in
~pressions Fig. 5-9. We shall assume an initial stored energy in the capacitor by
selecting
v(O) = Vo
The total current leaving the node at the top of the circuit diagram must
be zero, and, therefore,
c dv + E.. = 0
dt R
Division by C gives us
v o (9)+ RCi (10-3).1
lOO mA
Equation (9) has a familiar form; comparison with (1),
di + !li = 0 (1)
dt L
shows that the replacement of i by v and L/R by RC produces the identicallractical
equation we considered previously. It should, for the RC circuit we are. When
now analyzing is the dual of the RL circuit we considered first. This duality 1d using
forces v(t) for the RC circuit and i(t) for the RL circuit to have identical , in the
expressions if the resistance of one circuit is equal to the reCiprocal of theynthesis
resistance of the other circuit and if L is numerically equal to C. Thus,
155
156 The Transient Circuit
the response of the RL circuit,
enables us to write immediately
(10)
for the RC circuit.
,
;1
Now let us suppose that we had selected the current i as our variable
in the RC circuit, rather than the voltage v. Applying Kirchhoff's voltage
law,
,i 1 t
CJ i elt - v(to) + Ri = 0
I"
we obtain an integral equation and not a differential equation. However,
if we take the time derivative of both sides of this equation,
(ll)
and replace i by viR,
~+ dt) 0
RC elt
we obtain (9) again. Equation (11) could have been used as our starting
point, but duality would not have appeared as naturally.
Let llS discuss the physical nature of the voltage response of the RC
circuit as expressed by (10). At t 0 we obtain the correct initial condi­
tion, and as t becomes iIilinite the voltage approaches zero. This latter
result agrees with our thinking that if there were any voltage remaining
across the capacitor, then energy would continue to flow into the resistor
and be dissipated as heat. Thus, a final voltage of zero is necessary. The
time constant of the RC circuit may be found by using the duality rela­
tionships on the expression for the time constant of the RL circuit, or it
may be found by simply noting the time at which the response has dropped
to 30.8 per cent of its initial value,
T 1
RC
and T = RC (12)
(10)
lrrent i as our variable
ing Kirchhoff's voltage
II equation. However,
~quation,
(11)
v
Fig. 5-10 The copocitor voltage ott) in the parallel RC circuit is plotted as
a function of time. The initio I value of ott) is assumed to be Yo'
Our familiarity with the negative exponential and the significance of
the time constant T enables us to sketch the response curve readily, Fig.
5-10. Larger values of R or C provide a larger time constant and a slower
dissipation of the stored energy. A larger resistance will dissipate a smaller
power l with a given voltage across it, thus requiring a greater time to
convert the stored energy into heat; a larger capacitance stores a larger
energy with a given voltage across it, again requiring a greater time to
lose this initial energy.
n used as our starting
rrally.
e response of the R C
~ correct initial condi­
:hes zero. This latter
.ny voltage remaining
I flow into the resistor
:ero is necessary. The
ISing the duality rela­
f the RL circuit, or it
response has dropped
(12)
Drill Problems
5-7 For each of the circuits shown in Fig. 5-11, determine 0(0+).
Ans. 10; 50; 60 v
Fig. 5-11 See Drill Probs. 5·7, 5·8. and 5·10.
200 n
+
v
1000 n
. ?l.~~i
~t) ~500f!
,2p.F -
(e)
+
v90 V
(b)
,
\ .
5 kfl
l"Greater resistance leads to less dissipation" might be the scholar's motto.
157
Appeal 2012-000171
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Patent 6,260,097

89
Attachment
DDR: Still an Ideal Choice for Many New Designs
When we introduced our DDR SDRAM, it was revolutionary and pioneering technology. DDR allows applications to transfer data on both the rising and falling edges of a clock
signal, doubling bandwidth and vastly improving performance over SDR SDRAM. To achieve this functionality, we use a 2n-prefetch architecture where the internal data bus is
double the size of the external data bus, so data capture can happen two times each clock cycle.
Because DDR continues to be the ideal choice for many new designs, we're committed to long-term product support and availability.
DDR SDRAM
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Appeal 2012-000171
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Patent 6,260,097

90
Attachment
MCGRAW-Hill

ICTIONARY Of

ClfNTlflC AND

fCHNICAI

fRMS

fifth Edition ­
Sybil P. Parker
Editor in Chief
288 butyl oleate
BUXBAUMIALES
seta
(C)1fjJ
Morphological features of
Buxbaumlales. (a) Sporophyte of
Buxbaumia aphylla (from W. H.
Welch., Mosses oj Indiana,
Indiana Department oj
Conservation, 1957). (b)
Diphysciumjoliosum, habit
sketch, (c) leaves, and
(d) perlchaetialleaf (from H. S.
Conard, How to Know the Mosses
and LiveTworls, William C.
Brown, 1956).
\:"C\X\"n~ 'd ~:.Sy;:t,v'C)'\\.e.x\." <)\ '5,,&~~ ~~t::.'te'\Qn·~ U".$:\\ c'C)mme;tc\a\\~ a'6
-a.. ~~-'C)~'C)~-""\.'C\~ 'Q.~e;,'(\.," \ '\::)'fU.~·4"\ ~~'t'~~v-'\'o.l:\ \ .
bU\y\ oleate \Q'RG C;\E.M) C2iH.202 A. uUlyi ester 0\ oielC
acid; used as a plasticizer. I 'byiid'\ """,,,,,&"''''''''-'i', .,..","<",S'i', \\\"- '>UTI":"'''-, "'"<"'l
..."''''m\i~"''''':,,,,,,"'\ 'i\",,,, s"."'it"·r""':",,,...,,'" ~",,,,'&-,,,.,..,,'" ""<>\~<>""'"\'>.\'"
surface. ICONi SYS) See uit'ner. \H..ECl....1 The conuitlOn 0\
a combinatorial circuit with feedback that has undergone a tran­
sition, caused by the inputs, from an unstable state to anew state
thal.·iS also unstable. \.n. MECHI \n sU\lerwnlC \l\lluser aeto­
d':jt\\m\\c'!;, a nOt\'!;\ea(\.'j '!;hoc\<"mo\\.ot\and ai.rl\o'N a'!;wc\.a\