Ex Parte 5982921 et al

Board of Patent Appeals and Interferences

Jun 1, 2010

90007691 (B.P.A.I. Jun. 1, 2010)

1
UNITED STATES PATENT AND TRADEMARK OFFICE
____________________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________________

Ex parte APPLIED MATERIALS, INC. and APPLIED MATERIALS
ISRAEL, LTD.1
Appellant

Appeal 2010-002218
Merged Reexamination Controls 90/007,577, 90/007,691, and 90/008,690
Patent No. 5,982,9212
Technology Center 3900
____________________

Decided: June 1, 2010
____________________

Before JOSEPH F. RUGGIERO, SCOTT R. BOALICK, and KARL D.
EASTHOM, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL

1 Applied Materials, Inc. and Applied Materials Israel, Ltd. is the real party
in interest.
2 The patent under reexamination [hereinafter ‘921 patent] issued (Nov. 9,
1999) to David Alumot, Gad Neumann, Rivka Sherman, and Ehud Tirosh.
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Appellant appeals under 35 U.S.C. §§ 134(b) and 306 from a final
rejection of claims 1-5, 8, 14, 15, 17, 66, 68 and 69. Claims 6, 7, 9-13, 16,
18-65, 67, and 70-80 have been confirmed as patentable. No other claims
are pending. (See App. Br. 23; Fin. Rej. 64; Advisory Action (Feb. 19,
2009); Office Action (mailed Mar. 4, 2009)). We have jurisdiction under 35
U.S.C. §§ 134(b) and 306.
We affirm-in-part.
STATEMENT OF THE CASE
This reexamination proceeding arose from two third-party requests for
ex parte reexamination filed by Negevtech, Ltd. and another by Robert A.
Saltzberg, Esq. of the ‘921 patent, all of which have been merged into the
current proceeding. According to Appellant, the ‘921 patent under re-
examination is involved in litigation styled as Applied Materials, Inc. and
Applied Materials Israel, Ltd. v. Negevtech Ltd. and Negevtech, Inc., case
No. C04-03656 SI (N.D. Cal.). The litigation has been stayed pending the
results of these merged reexamination proceedings. (App. Br. 2.)
The Disclosed Invention
Appellant’s disclosed invention inspects the surface of wafers and
chips for defects by comparing different portions of the wafer or chip. (See
‘921 Patent, Abstract, Fig. 1.)

3 This opinion refers to the following abbreviations: Final Rejection (mailed
Aug. 5, 2008) (“Fin. Rej.”), the Examiner’s Answer (mailed Apr. 24, 2009)
(“Ans.”), the Appeal Brief (filed Mar. 5, 2009) (“App. Br.”), and the Reply
Brief (filed June 24, 2009) (“Reply Br.”).
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The Claims
Appellant’s arguments initially focus on claim 1. Claim 1
immediately follows, with other claims appearing later in the opinion:
1. An inspection device for inspecting a patterned substrate,
comprising:
a light source providing a light beam;
an optical system for directing the beam to impinge upon a defined
spot on the substrate;
a plurality of detectors spaced apart from each other but concurrently
directed at the defined spot, said plurality of detectors providing a first and a
second reflection data streams corresponding to reflected light from the spot
to first and second directions;
a memory having a first and a second reference data streams, wherein
each of the first and second reference data streams comprises data
corresponding to a location on a patterned substrate;
a comparator comparing said first reflection data stream to said first
reference data stream and providing a first comparison signal, and
comparing said second reflection data stream to said second reference data
stream and providing a second comparison signal.
Prior Art and Rejections
The prior art relied upon by the Examiner in rejecting the claims
follows:
Levy 4,579,455 Apr. 1, 1986
Suda 4,731,855 Mar. 15, 1988

Claims 1-5, 8, 14, 15, 17, 66, 68 and 69 stand rejected under 35
U.S.C. § 103(a) as obvious based on Suda and Levy.
ISSUES
Appellant’s responses to the Examiner’s stated positions present the
following issues:
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1. Did the Examiner err in finding that Suda teaches reference data
streams and in finding and concluding that Suda and Levy render obvious
the storage of the streams in a memory as set forth in claim 1?
2. Did the Examiner err in finding and concluding that Suda and Levy
render obvious the remaining claims on appeal?
FINDINGS OF FACT
The ‘921 Patent
1. The ‘921 patent refers to “reference patterns” as follows: “The
reference pattern may be a pattern on another like article (e.g., die-to-die
comparison), another like pattern on the same article (repetitive pattern
comparison), or data stored in a database (die-to-database comparison).
(Col. 2, ll. 50-53.) These comparisons are used to find wafer or chip circuit
defects. (Abstract, col. 2, ll. 38-49.)
2. The ‘921 further describes the repetitive pattern comparison:
The repetitive pattern illustrated in FIG. 32 consists of a
number of relatively small (e.g. a few microns in size)
comparable units. . . . As shown therein, each pixel along the
scanning line 202 is comparable to a pixel which is located at a
distance “d” either to its left or to its right. Since the two pixels
that have to be compared are contained in the same scanning
line, no registration has to be done between the “inspected” and
the “reference” image . . . .
(Col. 24, ll. 7-16.)
3. The ‘921 further describes the die-to-database comparison:
Instead of using, as a reference to be compared with the
data derived from the inspected article, data generated from real
images of another like article (in the die-to-die comparison), or
of another like pattern on the same article (repetitive pattern
comparison), the reference may be generated from simulated
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images derived from a database; such a comparison is called a
die-to-database comparison.
(Col. 27, ll. 44-51.)

In other words, reference images are modeled and compared against
images on an inspected article. (Col. 27, ll. 52-55.) The modeling is based
on at least two principles: “a) the pattern of an object consists of typical
features, such as corners and curves; and b) the modeling extracts these
features from the database and associates with each feature its corresponding
scattering signal.” (Col. 28, ll. 5-32.)
“A feature is part of the pattern . . . . The pattern on the inspected
object is described by a list of features. A feature may be either a corner or a
curve.” (Col. 28, ll. 13-16.) For example, modeled corners are compared
against actual imaged corners in an inspected article. (See col. 28, ll. 54-59;
Figs. 41, 43.)
Suda
4. Suda’s system inspects for pattern defects by comparing logic gate
thresholds representing known patterns for corners and other shapes to
actual image inputs of corners or other shapes using an array of detectors on
an inspected article. (Abstract, col. 11, ll. 28-35; col. 12, ll. 30 to col. 14, l.
49; Figs. 8A, 8B, 11, 12)
5. Suda’s circuit includes two main sub-circuits, one to detect for
abnormal direction light from the array, and another to detect for normal
direction light from the array. (See Figs. 7, 32; col. 20, ll. 31-40; col. 22, ll.
10-63.) In general, the abnormal circuit determines defects based on light
reflected from patterns (i.e., a line). The term abnormal refers to spatial
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areas where the reflected light does not normally reach, or is very weak, if
reflected from an ideal line or corner not having a defect. (Col. 2, ll. 48-68.)
On the other hand, the normal detection circuit classifies the pattern
(as a corner for example – see Fig. 12) and detects scattered light in a
direction, relative to an inspected pattern line, at 45, 90 and 135 degrees.
These directions are experimentally proven and theoretically based. (Col. 2,
ll. 35-47; Figs. 1A-1D (showing normal reflections);Fig. 2b (shaded line 4
showing an abnormal reflection, lines 1, 2, and 3 showing normal
reflections).)
Rounded corners or other slight edge deviations from an ideal pattern
also reflect detected light in an abnormal direction, but Suda’s system
accounts for this so that these minor deviations are not classified as a true or
fatal defect. (Col. 4, l. 53 to col. 5, l. 67; col. 20, ll. 33-40.)
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6. A block diagram of a portion of the abnormal detection circuit is
depicted below:

Figure 26 above depicts Suda’s floating threshold detection circuit 20
and 21 coupled to AND gate 1900. (Col. 18, ll. 44-46.)
In Figure 26, the digital input signals Ei electrically represent
abnormally reflected light scattered from (two of ) the detectors and input to
the shift register 600. (Col. 17, ll. 14-29; col. 18, ll. 44-61, col. 20, ll. 31-33)
The circuit compares an electrical signal (ej) (representing a point on a die)
to samples around that point the by successively comparing (and shifting)
electrical signals Ei (representing a scattering intensity for each adjacent
point in the region) to, inter alia, an average signal Ē (representing the
average scattered intensity for all local points in the region), a changing
threshold Esh, which varies as a function of the average, or a signal Emin. The
changing threshold Esh ultimately is used to eliminate background noise
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from the sample point represented by ej on the wafer to accurately determine
if the point represents a defect. (Col. 17, l. 14 to col. 18, l. 66; col. 19, l. 44
to col. 20, l. 40; col. 27, ll. 25-48; Figs. 23-26.)
7. “If a defect is present in the pattern, a pulse defect signal h is
produced at a time th corresponding to the defect position.” (Col. 17, ll. 27-
29; see Fig. 23.)
8. Figure 23 is reproduced below:

Figure 23 shows the defect pattern referenced supra showing the pulse
defect signal in relation to signals representing the region around the defect
h as the quotation in FF 7 indicates. The DC and pulsating AC wave signal
depicted above results from a reflected diffraction light from a pattern.
(Col. 17, ll. 14-27; col. 18, ll. 38-43.) The signal may include background
noise. (See Figs. 24A-24D; col. 17, ll. 38-47.)

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9. Figure 27 of Suda is reproduced below:

Figure 27 of Suda depicted above represents the floating threshold and
floating averages to which the signals ej = Eob are compared. (Col. 19, l. 44
to col. 20, l. 14, FF 6.)
10. “[S]hift register 600 . . . includes a plurality of shift registers
connected in series which are temporary storage circuits.” (Col. 18, ll. 47-
49; see FF 6.)
11. The averaging circuit 700 (FF 6) used to calculate Ē includes a
read-only memory (ROM). The ROM stores expected quotients. Different
quotients in memory are addressed depending on an added value of the
incoming bit stream and the bits of a divider N, where N represents the
number of inputs from the shift register. The ROM is used as an alternative
in place of hardware for a conventional divider circuit because it is less
complex than typical hardware. (Col. 19, ll. 10-25.)
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12. There are four identical circuits 20, 21 (FF 6), one for each of
four abnormal light directions. The four individual circuits each process one
of the four outputs Ei at terminals 17-1, 17-2, 17-3, and 17-4 (Fig. 9B) from
each of four summer circuits. Each of the four summer circuits sums two
paired inputs (e.g., 10-2, 10-10) from two of the eight detectors (on the same
axis, e.g., 11-2, 11-10 Fig. 8b).) Each produces an output Em1 through Em4
which is input into AND gate 1900 to produce output Em as seen above (FF
6). The output Em is input to the circuit represented in Figure 28 which
produces a final defect signal. (Col. 10, ll. 50-58; col. 18, ll. 56-66; col. 20,
ll. 31-33; col. 21, ll. 10-14; FF 6.)
13. Each multi-valued output Em1, Em2, Em3, and Em4 is stored in one of
four separate latches 1800 (corresponding to one of the four circuits 21
described supra (FF 6)). The latches 1800 are temporary memories. (Col.
18, ll. 59-62; col. 20, ll. 17-23.) “[A]ny one of Eob- Ē, Eob-Emin, or Eob -Esh is
produced by the multi-valued output Em1.” (Col. 20, ll. 13-14.) (Which of
the three values is produced depends on the position of the switch 1700.
(Col. 20, ll. 6-16; FF 6).)
Levy
14. Levy’s system compares photomasks having duplicate die
patterns to one another to determine if defects are present. (Abstract; col. 1,
ll. 8-14.)
15. In a die-to-die comparison, Levy employs temporary memories to
continuously inspect data streams corresponding to the die patterns and
avoid the “enormous amount of memory that would otherwise be required”
(col. 5, ll. 19-20):
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Memories 56 and 58 are first-in-first-out (FIFO) type memory
circuits that at any one point in time contain only a small
fraction of the total pixel representations of the die patterns. In
the preferred embodiment of the present invention, left and
right pixel memories 56 and 58, respectively, contain pixel
representations for the seven most recent scans of left and right
detectors, respectively.
(Col. 5, ll. 23-30.)
16. In a die to database comparison, Levy employs the same
temporary memories 56 and 58, but also employs a data base 55 which
stores a stored replica of a photomask to be inspected. The data base values
are then input into the left pixel memory 56. (Col. 5, ll. 9-13.)
17. Levy teaches varying an error threshold depending on results of
comparisons between the two dies to reduce actual defect detection while
reducing false defect detection. (Col. 3, ll. 23-46.)
18. As indicated supra, Levy’s system compares pixel data. “A pixel
is the rectangularly shaped element of which the pixel representations are
composed. Each pixel corresponds to a small rectangular area on of the
photomask.” (Col. 6, ll. 47-49.) Each pixel of analog light is assigned a
digital (multi-value) pixel value. (Col. 6, ll. 59-66.)

PRINCIPLES OF LAW
“[T]he examiner bears the initial burden, on review of the prior art or
on any other ground, of presenting a prima facie case of unpatentability.” In
re Oetiker, 977 F.2d 1443, 1445 (Fed. Cir. 1992). Appellant has the burden
on appeal to present arguments with respect to any ground of rejection.
Arguments not presented are deemed waived. See id.; 37 C.F.R.
§ 41.37(c)(1)(vii); MPEP 2275 VI (Rev. 7, July 2008)(37 CFR 41.37
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“requires that the brief must set forth the authorities and arguments relied on,
and to the extent that it fails to do so with respect to any ground of rejection,
that ground may be summarily sustained. A distinction must be made
between the lack of any argument and the presentation of arguments that
carry no conviction.” In the former case, summary affirmance is warranted,
while in the latter case, “a decision on the merits is made, although it may
well be merely an affirmance based on the grounds relied on by the
examiner.”)
A determination of obviousness can be based on a showing that “there
was an apparent reason to combine the known elements in the fashion
claimed . . . .” KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).

ANALYSIS
Claims 1, 8 and 14
With respect to claim 1, Appellant argues that the Examiner
incorrectly characterizes Suda’s signals, Ē, representing the average
scattered intensity for all local points in a die region, Esh, representing the
changing threshold which varies as a function of the average, or Emin (FF 6),
as the recited first and second reference data streams. (App. Br. 21-24.)
(One stream Ē (or Esh) from one circuit 20, 21 (FF 6, 12) corresponds to the
first reference data stream in claim 1, while another separate stream from
another circuit 20, 21 (of four) corresponds to the second reference data
stream in claim 1. (See Ans. 8.))
Appellant relies on language in the ‘921 patent to limit the scope of
the term “reference,” and states, inter alia, that “the reference comprises
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data corresponding to a location on an article, such as a patterned substrate
or semiconductor wafer.” (App. Br. 22.) Appellant also states that in the
‘921 patent, “reference data is from something other than the inspected
pattern,” and that “the comparison is performed between two like things
(patterns), where one is called a reference.” (Id.)
With respect to Suda, Appellant argues as follows:
The signal Ē is an average of N digital signals ej read
from the shift register 600 that receives the input signal. The
term “reference data stream” cannot reasonably be construed to
read on this average of samples of the input signal. While the
input signal may be compared to this average, construing the
term “reference data stream” to read on this average is
unreasonable because it strips the term “reference” of any
meaning. Further, this average is not data “corresponding to a
location.”
(App. Br. 23.)
The Examiner responds to these arguments by finding that in
Appellant’s repetitive-pattern-comparison embodiment (see FF 2), “both the
reference and reflection data stream [sic] are taken from the same general
spot upon the wafer via the use of a time shift register.” (Ans. 20.) The
Examiner also responds that claim 1 does not require the reference data to
include “‘something other than the inspected pattern.’” (Ans. 20 (quoting
Appellant).) Thus, according to the Examiner, interpreting Suda’s Ē (or one
of similar signals Esh and Emin) as a reference signal stream is reasonable.
(Ans. 20-21.)
The Examiner correctly notes that Appellant’s repetitive-pattern-
comparison does include reference data close to the inspected pattern. (FF
2.) In Suda, Appellant’s arguments notwithstanding, the average Ē similarly
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represents data close (and corresponding) to an inspected sample portion of a
pattern represented by, for example, a sample representing a defect h at a
specific location in the die pattern. (FF 7, 8; see also FF 9 (showing
possible defects at different sample times corresponding to wafer locations
and the varying average and thresholds).)4 The ‘921 patent’s disclosed
embodiments similarly include reference data representing small segments
or pixels, some of which are close to the inspected pattern. For example,
one simulated embodiment includes simulated portions of a pattern,
“features” (FF 3), while another compares patterns close to the inspected
pattern (FF 2).
Appellant’s Brief acknowledges that the reference data stream may be
simulated or stored in memory. (App. Br. 22.) Thus, claim 1 encompasses
the disclosed stored simulated data embodiment just described and which
data “correspond[s] to a location on a patterned substrate.” (In claim 1, the
phrase, “location on a patterned substrate,” does not necessarily refer to the
same location or substrate as either the spot or the substrate referenced in the
earlier recited claim phrase, “defined spot on the substrate.”)
Skilled artisans would have recognized that implicit in the ‘921 patent
simulation or die-to-die comparison scheme is the notion of expected normal
patterns. In such schemes, deviations from a normal expected stored pattern,

4 While Appellant argues that “the signal Esh is merely derived from the
abnormal reflected signal Ej to which it is compared,” (Reply Br. 11
(emphasis added), Appellant argues “[i]t is not a reflected signal.”
Appellant’s point fails to define any distinction, claimed or disclosed.
Appellant’s reference signals are also derived from reflected signals to
create electrical signals (FF 1-3) with one embodiment including
simulated/derived signals (FF 3).
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or from some other reference pattern portion (e.g., a stored data feature),
potentially indicates a defect is present. (See FF 1-3.) While Suda’s average
Ē includes the inspected sample point, it also includes close samples
representing the wafer around the inspected sample point.5 (FF 7-9.) These
samples include samples other than the currently inspected sample point ej,
much like Appellant’s system in the ‘921 patent. (FF 6-9.) Based in part on
experimental data (i.e., prior measurements), Suda’s abnormal circuit
detector system only expects a certain range of signal (an average) unless
there is a defect. (See FF 5-9, supra note 5.) Similarly, Appellant’s
simulation scheme implicitly includes a mathematical simulation of an
expected prior-inspected point; i.e., it models what is a normal (i.e.,
expected) “feature” which suggests an average of, or representative type of,
prior inspected points. (See FF 3).
A relevant plain meaning of the word “average” is “a representative
type.” The American Heritage Dictionary of the English Language 91
(1975). The ‘921 patent, like Suda, merely compares reflected sample
points to a representative type. In Suda, the representative type is embodied

5 In Suda’s system, a DC and pulsating AC wave (with possible noise) signal
results from a reflected diffraction light from a pattern and indicates that a
certain location corresponds to an ideal pattern as opposed to a defect. Also,
the abnormal signal detectors pick up minor signals (including perhaps
background noise) corresponding to rounded corner patterns or minor line
defect patterns. In either case, these signals “comprise[] data corresponding
to a location on a patterned substrate” as required by claim 1. (See FF 5, 7-
9.)
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in the average Ē (or Esh).6 Suda’s average includes data corresponding to an
ideal pattern (line or corner) near an inspected sample point on a die, and
also includes data corresponding to something close to the ideal pattern (e.g.,
a line having minor deviations or a rounded corner on the die). In these
cases no true defect is indicated at those locations near the inspected point
on the die because the system expects a certain average or range of outputs
for these known and predicted representative patterns. (See FF 5, 7-9, supra
note 5.) In the ‘921 patent, the representative type is similarly determined
from a desired or expected normal shape (e.g., a feature: an expected line, or
corner (FF 3)), in essence, an average shape.
Hence, in both the ‘921 patent and Suda, measured deviations from an
average or expected shape indicate a defect. (Compare FF 1 with FF 4, 8, 9,
12.) Nothing in claim 1 or the ‘921 patent precludes such an average from
constituting a reference data stream. In light of the ‘921 patent, skilled
artisans would have recognized the phrase “reference data stream” at least to
encompass a data stream representing the expected reflections corresponding
to patterned locations around the inspected data point.7 (See FF 1-3.)
Suda’s reference streams, as proposed by the Examiner, meet that definition.

6 Esh includes Ē such that both include and are determined by averaging data
points including and surrounding the area immediately near the inspected
compared point. (See Suda, Eq. 5, col. 18.)
7 An art-based definition of “reference level” shows that the term simply
signifies a starting point (which may include a noise floor) to which another
level is compared. See e.g., Newton’s Telecom Dictionary 691 (2004)
defining “reference level” as follows: “The measure of a value used as a
starting point for further measurements. In communications applications
this term usually refers to a power level of a signal or noise.”
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In the Reply Brief, Appellant stresses that the recited reference stream
is from another pattern. (Reply Br. 3.) However, as discussed supra, the
‘921 patent does not limit the reference to another pattern but includes
features (portions of a pattern) or data simulations. In any event, as also
discussed supra, Suda’s reference data corresponds to ideal patterns on the
inspected wafer and also includes data representing reflected light from
close to ideal patterns such as rounded corner patterns or line patterns having
slight deviations.
Assuming for the sake of argument that the claim 1 reference data
must correspond to another pattern, because the data in Suda’s reference
data streams comprise data corresponding to an ideal pattern on the wafer, it
follows that the same data also corresponds to another ideal pattern, the ideal
model pattern (corner or line) upon which the die pattern is based. In other
words, in the absence of a defect, the data would be expected to result from a
scan test of the model pattern. (See FF 5.) (Even if there is a local defect,
that defect is averaged so that the average still constitutes a reference. (See
FF 5-9, 11.))
Moreover, claim 1 does not recite another reference pattern. Rather,
claim 1 virtually defines the reference data stream by its wherein clause:
“wherein each of the first and second data streams comprises data
corresponding to a location on a patterned substrate” (emphasis added).
The claim only requires reference data to correspond to a location on a
patterned substrate, but the location need not be patterned or correspond to
another pattern. The claim is broader than any disclosed embodiments.
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As such, the ‘ 921 patent embodiments do not create as limited of a
definition as Appellant’s arguments imply, especially here where the claim
is broader than those embodiments and the plain meaning of the term
“reference” tracks the art-recognized meaning of the term and simply
signifies a comparison starting point or norm. See In re American Academy
of Science, 367 F.3d 1359, 1369 (Fed. Cir. 2004) (“We have cautioned
against reading limitations into a claim from the preferred embodiment
described in the specification, even if it is the only embodiment described,
absent clear disclaimer in the specification.”); accord In re Bigio, 381 F.3d
1320, 1325 (Fed. Cir. 2004) (“Absent claim language carrying a narrow
meaning, the PTO should only limit the claim based on the specification or
prosecution history when those sources expressly disclaim the broader
definition.”).
Appellant also characterizes the Examiner’s interpretation of a
“reference” as “meaningless” because it includes “any signal that is
compared to the reflected data stream in Suda.” (Reply Br. 6.) To the
contrary, pursuant to the discussion supra, Suda’s reference stream includes
an average which represents wafer locations and pertains to the expected
norm on a patterned substrate, and does not constitute “any signal.”
Appellant also challenges the Examiner’s finding that Suda and Levy
collectively suggest storing the two reference data streams in memory.
(App. Br. 23-24.) The Examiner found that while Suda “teaches storing a
portion of the reference data stream into memory via use of the shift register
as previously described, Suda fails to teach storing the entire reference
stream.” (Ans. 9.) The Examiner relied on Levy to teach storing entire
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reference streams into memory. (Id.) The Examiner also explained “that
certain embodiments of the [‘921] patent under reexamination store only a
portion of the reference stream (also using a shift register),” while other
embodiments store the entire reference stream into memory. (Id.)
Appellant points out that Suda actually only teaches storing the
signals Ei in the shift register 600 memories, as opposed to Ē, the average, or
Esh. (Reply Br. 8.) Appellant is correct. (FF 6.) However, Suda also
teaches storing one of Em1, Em2, Em3, and Em4 in each of four separate latches
1800 which are also temporary memories. Each signal Em1 through Em4
includes either Ē or Esh. (FF 12, 13.)8 In addition, Suda also teaches
separate read only (ROM) memories to obtain the average Ē. The expected
quotients representing expected averages (depending on the inputs and
number of data points) are stored in the ROM. (FF 11.)9

8 Claim 1 requires “a memory having first and second reference data
streams, wherein each of the first and second reference streams comprises
data corresponding to a location . . . .” The signals Em1, Em2, etc. each
comprise such reference data (i.e., Em1, Em2 = Eob- Ē, Eob-Emin, or Eob-Esh )
and are stored in separate memory latches 1800 as noted supra. (FF 12, 13.)
Claim 1 is broad enough to encompass this reading of Suda because claim 1,
an apparatus claim, does not require the memory to store the signals before
they are compared. This interpretation also involves treating separate
latches 1800 as one memory. In any case, as discussed further below, the
collective teachings of Suda and Levy satisfy the disputed phrase. (The
Examiner stated that the third party requestor asserted that Suda anticipates
or renders obvious the claims on appeal. However, it does not appear that
the Examiner clearly adopted an anticipation theory involving Suda. (See
Ans. 11.))
9 Similar to the discussion in note 6 supra, the separate ROMs of Suda
cumulatively satisfy the disputed memory in claim 1 because the selected
(and expected) stored quotients ultimately become first and second reference
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Thus, Suda teaches using memory to process live signals. Appellant
argues that Suda’s “signals Esh, Emin and Ē all operate on signals received
from the detectors. There would have been no reason to store these signals
in memory because they are live signals from the detectors, or are derived
therefrom during the detection process.” (App. Br. 20-21). This argument is
contradicted by the Examiner’s finding supported by the record that Suda’s
“live” signals are stored in memory explicitly, albeit on a temporary basis,
either in separate shift registers, ROMs, or latches. Appellant does not point
to any time frame for holding data as establishing what constitutes a
memory.
Moreover, Levy’s memory 56, 58 are also temporary (FIFO)
memories used on “live” signals, one of which corresponds to a reference
signal. (FF 15.) Levy employs these temporary memories to aid in
determining varying thresholds and Suda also uses similar varying
thresholds and temporary memories. (FF 4-17; compare Ans. 9, 10;
90/007,691 Reexamination Request 47-48 (incorporated by the Examiner at
Ans. 9-10).)10 Levy also notes that the smaller FIFO memories save from
the use of an otherwise “enormous amount of memory.” (FF 15.)

data streams Ē stored in this pair of ROMs (i.e., from two of Levy’s four
circuits 20, 21( see FF 11-13)).
10 The Examiner referred specifically to the database 55 in Levy’s database
to die comparison embodiment, and also referred to the third party
requestor’s findings as noted. (Ans. 9-10.) The third party requestor cited
Levy’s “‘left and right pixel memories.’” (90/007,691 Reexamination
Request 47-48.) In any event, the database 55 dumps memory into one of
the FIFOs 56. (FF 15-16.)
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Using a memory to store and process reference signals Ē, Emin, or Esh
as suggested by Levy would have predictably benefited Suda’s system by
allowing the replacement of portions of the hardware circuit and allowing
for processing to occur in a small memory. Suda suggests using memory to
replace complex hardware circuits (FF 11) and generally employs temporary
memories to store related signals and signals including the reference signals
(FF 10-12.)
While Appellant points to the various other differences between
Levy’s use of the memory and Suda’s circuit (App. Br. 16-21), and alleges
error in hindsight, claim construction, and determining what the references
describe, these arguments do not convincingly demonstrate that storing the
two recited reference signals into a memory as Levy suggests would have
involved an unpredictable use thereof and would have been beyond the skill
level of an ordinary artisan. Levy and Suda represent the ordinary artisan’s
skill level involved here and demonstrate collectively that using memory in
complicated circuits would have been well within that skill level.11
[I]f a technique has been used to improve one device, and a
person of ordinary skill in the art would recognize that it would
improve similar devices in the same way, using the technique is
obvious unless its actual application is beyond his or her skill.
. . . [A] court must ask whether the improvement is more than
the predictable use of prior art elements according to their
established functions.

11 See In re Oelrich, 579 F.2d 86, 91 (CCPA 1978) (“the PTO usually must
evaluate both the scope and content of the prior art and the level of ordinary
skill solely on the cold words of the literature”); In re GPAC Inc., 57 F.3d
1573, 1579 (Fed. Cir. 1995) (Board did not err in adopting the approach that
the level of skill in the art was best determined by the references of record).
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KSR, 550 U.S. at 417 (citation omitted).
Claim 8 differs from claim 1 primarily in that the former recites
“pixel” data. Appellant primarily relies on arguments presented against the
rejection of claim 1. Appellant also asserts that the “signals in Suda are not
reference pixel data.” (App. Br. 28.) The Examiner incorporated the third
party requestor’s findings. (Ans. 11 (incorporating pages 44-71 of the
90/007691 Reexamination Request).) Appellant does not explain why
Suda’s data does not constitute pixel data. Appellant does not assign any
particular meaning to a pixel or define it in a manner distinguishing over
Suda or Levy.
According to Levy, a pixel corresponds to an area on the surface of
the substrate. (FF 18.) Suda similarly processes reflected light
corresponding to areas on a substrate/wafer to create multi-valued outputs.
(FF 5-9.) Appellant’s pixels similarly appear to represent small inspected
areas on a wafer. (FF 2.) Appellant also does not explain why the
Requestors’ explanation (90/007691 Reexamination Request: 59-61) as
adopted by the Examiner, demonstrating how the combination of Suda and
Levy renders claim 8 obvious, is in error. “The problem in this case is that
the appellants failed to make their intended meaning explicitly clear.” In re
Morris, 127 F.3d 1048, 1056 (Fed. Cir. 1997). “It is the applicants’ burden
to precisely define the invention, not the PTO’s.” Id.
Claim 14 contains the “reference” limitations similar to those of claim
1 but is broader in that it does not recite a memory. Appellant relies on
arguments presented against the rejection of claim 1, arguments deemed
unpersuasive as explained supra. (App. Br. 28.) The argument that the
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Examiner used the same streams to represent both the reference and
reflection data streams lacks merit for reasons tracking those above. (Id.)
Two of the four reflection data portions of the stream, ej = Eob, are compared
to two reference data streams Ē (or Esh) in two separate circuits 20, 21. (FF
6, 9, 11-13.)
For the foregoing reasons, the Examiner has not erred in the rejection
of claims 1, 8, and 14 and we will sustain the Examiner’s rejection of these
claims.

Claim 2
Claim 2 follows: “The inspection device of claim 1, further
comprising a decision processor receiving said first and second comparison
signals and providing a global defect alarm.”
In addition to relying on arguments presented for claim 1 (App. Br.
24-25), Appellant argues as follows:
Moreover, the circuit in FIG. 28 in Suda receives the
output of the subtractor 1600, which is the result of one
comparison of a signal ej with signals Emin, Esh and Ē. It does
not receive the “first and second comparison signals” to provide
a “global defect alarm.” Note that the circuit in FIG. 26 is
provided “for each of the signals” 17-1, 17-2, 17-3 and 17-4.
Suda, Col. 18, lines 59-61.
(App. Br. 25.).
Appellant’s characterization of Suda’s Figures 26 and 28 appears
accurate to a certain extent; however, the characterization does not address
the AND gate 1900 in Figure 26 which receives all four outputs Em1, Em2,
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Em3, and Em4, signals produced at each of the four latches 1800 of the four
circuits for each of the signals 17-1, 17-2, 17-3 and 17-4. (FF 6, 12.)
The output of AND gate 1900, Em, constitutes the input signal of the
circuit represented in Figure 28. (Each separate latch 1800 output Em1
through Em4, is fed into the AND gate 1900 and is a multi-valued output
representing a comparison signal which in turn represents a magnitude of the
defect for each separate signal 17-1 through 17-4.) Ultimately, in the next
circuit stage, Em is used to determine whether there is a true defect,
corresponding to a global defect alarm as recited in claim 2. (FF 6, 12, 13.)
Considering the decision processor of claim 2 to include the AND
gate 1900 as well as the circuit represented in Figure 28 means that the
decision processor does receive “the first and second comparison signals,”
contrary to Appellant’s argument.
Based on the foregoing discussion of claim 1, and the discussion
here, Suda and Levy collectively satisfy the disputed elements of claim 2.
As such, we will sustain the Examiner’s rejection of claim 2.
Claims 3-5, 15, 17, 66, 68, and 69
Claim 3 follows:
3. An inspection device for inspecting a patterned substrate,
comprising:
a light source providing a light beam;
an optical system for directing the beam to impinge upon a defined spot on
the substrate;
a plurality of detectors spaced apart from each other but concurrently
directed at the defined spot, said plurality of detectors providing a first and a
second reflection data streams corresponding to reflected light from the spot
to first and second directions;
a memory having a first and a second reference data streams; a
comparator comparing said first reflection data stream to said first reference
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data stream and providing a first comparison signal, and comparing said
second reflection data stream to said second reference data stream and
providing a second comparison signal;
a pixel characterizer receiving said first and second reflection data
streams and assigning a corresponding pixel type to each inspected pixel of
said first and second reflection data streams, each pixel type having a
threshold associated therewith;
a subtractor receiving the first and second reflection data streams and
the first and second reference data streams and calculating a difference value
for each inspected pixel of said first and second reflection data streams; and
wherein for each inspected pixel in said first and second reflection
data stream said comparator compares the difference value to the threshold
associate with the pixel type assigned to said pixel, and issues a defect alarm
when the difference value exceeds the threshold. (Emphasis added.)

In addition to relying on similar arguments presented against the
rejection of claims 1 and 2, Appellant argues as follows:
Thus, regardless of what signal in Suda is found to be a
“reflection data stream,” Suda does not describe the “pixel
characterizer” that assigns a “pixel type to each inspected pixel”
or the “comparator” that “compares the difference value to the
threshold associated with the pixel type assigned to said pixel.”
[The Examiner] does not fully address this discrepancy
and suggests that Levy might make some unspecified
modification of Suda if these references are viewed through the
lens of the claims of the invention. [The Examiner] argues that
since Levy assigns types to reflection data, and then assigns
thresholds based on those types, that one could modify Suda to
assign types to rejection data, and assign thresholds based on
those types. Without an explanation of what the resulting
design is however, it is impossible to determine whether that
design would be encompassed by the claims.
(App. Br. 26-27 (emphasis added).)

The Examiner responded by noting that Suda refers to a pattern
classifier and thresholds, and indicates that these could be modified as
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suggested by Levy to constitute a pixel characterizer. The Examiner also
pointed to other passages in Levy describing a comparison threshold. The
Examiner also referred the reader to the third party requester’s remarks at
pages 24-26, 48 and 56 of the 90/007,691 Reexamination Request. (Ans.
22-23.) The Examiner explains that the requester discusses Levy’s “method
of setting comparison thresholds based on classifications” (Ans. 22) and
“explains Levy’s pattern classification teachings” (Ans. 23).
Absent from the Examiner’s findings is explicitly what Appellant
challenged supra; i.e., the question of what portion of the different circuit
stages in Suda would be modified to arrive at the recited elements such as
those emphasized in the passage supra highlighting Appellant’s argument.
In the Reply Brief, Appellant further emphasized one of the crucial
missing links by emphasizing a part of the third party requestor’s
explanation:
The four reflected data streams that are compared to the four
reference streams are generated by abnormal direction signal
detectors . . . And, as noted above the data streams from which
are determined the pixel types used to set compares thresholds
are generated by normal direction signal detectors. “Therefore,
the reflected streams that are compared to the reference
streams are not the same streams that are received by the
pixel characterizer and assigned a pixel type.”
(Reply Br. 9 (quoting the 90/007,691 Reexamination Request at p. 56).)
In other words, missing is a clear explanation of how one would
modify Suda’s circuit to include Levy’s pixel characterizer and compare the
streams as set forth in claim 3. Modifying Suda’s normal data stream to
assign a pixel characterizer to it to vary a threshold depending on that pattern
makes sense, but doing so would not satisfy claim 3, at least as far as the
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Examiner has proposed, and as the bolded passage supra implies.
Conversely, modifying Suda’s abnormal data stream to assign a pixel type
thereto to set a threshold based on a pattern classification does not make
sense, or appear obvious, because the abnormal data stream is not employed
to determine the pattern classification. (See FF 5, Suda, Fig. 32.) Rather,
that stream is employed to find defects, as discussed supra, and it is not clear
how the abnormal reflections, which represent defects, could be used to
identify expected patterns.
In other words, this does not appear to involve a simple modification
of employing memory like that involved in the discussion of claims 1 and 2
supra. As such, Appellant has pointed to error in the Examiner’s prima facie
demonstration of unpatentability based on obviousness. Claims 15 and 17
include limitations of similar scope to that of claim 3. Claims 4, 5, 66, 68
and 69 depend from claims 3 and 15. Accordingly, based on the foregoing
discussion, we will not sustain the rejection of claims 3-5, 15, 17, 66, 68,
and 69.
CONCLUSION
1. The Examiner did not err in finding that Suda teaches reference
data streams and in finding and concluding that Suda and Levy render
obvious the storage of the streams in a memory as set forth in claim 1.
2. The Examiner did not err in finding and concluding that Suda and
Levy render obvious claims 2, 8, and 14.
3. The Examiner did err in finding and concluding that Suda and
Levy render obvious claims 3-5, 15, 17, 66, 68, and 69.

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DECISION
The Examiner’s decision to reject claims 1, 2, 8, and 14 for
obviousness is affirmed.
The Examiner’s decision to reject claims 3, 15, 17, 66, 68, and 69 for
obviousness is reversed.
Requests for extensions of time in this ex parte reexamination
proceeding are governed by 37 C.F.R. § 1.550(c). See 37 C.F.R. § 41.50(f).
AFFIRMED-IN-PART

ack

cc:
FISH & RICHARDSON P.C.
P.O. Box 1022
Minneapolis, MN 55440-1022

Third Party Requester, 90/007,577 and 90/007691:

Douglas G. Hodder
MORRISON & FOERSTER LLP
755 Page Mill Road
Palo Alto, CA 95018

Third Party Requester, 90/008,690:

Robert A. Saltzberg
MORRISON & FOERSTER LLP
425 Market Street
San Francisco, CA 94105