Ex Parte 5953263 et al

Board of Patent Appeals and Interferences

Jan 27, 2012

90010574 (B.P.A.I. Jan. 27, 2012)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
90/010,574 08/10/2009 5953263 8963.002.RXUS00 8760
22852 7590 01/27/2012
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER
LLP
901 NEW YORK AVENUE, NW
WASHINGTON, DC 20001-4413
EXAMINER
ESCALANTE, OVIDIO
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
01/27/2012 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte RAMBUS, INC.
____________

Appeal 2011-013706
Reexamination Control No. 90/010,574
United States Patent 5,953,263
Technology Center 3900
____________

Before ALLEN R. MacDONALD, KARL D. EASTHOM, and
STEPHEN S. SIU, Administrative Patent Judges.

EASTHOM, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2011-013706
Reexamination Control 90/010,574
Patent 5,953,263

Appellant, patent owner Rambus, Inc., appeals under 35 U.S.C.
§§ 134(b) and 306 from a final rejection of claim 1-4. (App. Br. vii.) We
have jurisdiction under 35 U.S.C. §§ 134(b) and 306.
We REVERSE.

STATEMENT OF THE CASE
This proceeding arose from a third party request for ex parte
reexamination by Micron Technology Inc., of (now expired) U. S.
Patent 5,953,263, “Synchronous Memory Device Having a Programmable
Register and Method of Controlling Same.” Appellant’s Brief lists
numerous related judicial and other proceedings including inter partes and
ex parte reexaminations, International Trade Commission proceedings, and
Federal District Court and Circuit Court proceedings. (App. Br. iii-vii.) An
oral hearing of this appeal transpired at the BPAI on December 14, 2011.
Claim 1 follows:
1. A synchronous semiconductor memory device having at least one
memory section which includes a plurality of memory cells, the memory
device comprises:
a programmable register to store a value which is representative of a
delay time after which the memory device responds to a read request.

The Examiner rejected claims 1-4 under 35 U.S.C. 102(b) as
anticipated based on the iAPX Interconnect Architecture Reference Manual
(Intel Corp.) (1982) [hereinafter iAPX Manual].
ISSUE
The issue is whether the “synchronous semiconductor memory
device” recited in claim 1 reads on the memory module disclosed in the
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iAPX Manual. The central dispute turns on whether the claimed term
“synchronous semiconductor memory device” is limited to a single “chip.”
FINDINGS OF FACT (FF)
The ‘263 Patent
P1. The ‘263 patent states that “[o]ne object of the present invention
is to use a new bus interface built into semiconductor devices to support
high-speed access to large blocks of data from a single memory device”.
(Col. 3, ll. 11-14.)
P2. The ‘263 patent states that “each semiconductor device contains a
set of internal registers” and that “semiconductor devices . . . contain
registers 172 which specify the memory addresses contained within that
device.” (Col. 6, ll. 18-26.)
P3. The ‘263 patent also describes adding the “[n]ew bus interface
circuits” to “the internals of prior art DRAM devices.” (Col. 4, ll. 15-16.)
The iAPX Manual
I1. Figure 1-2 of the iAPX Manual follows:

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Figure 1-2 depicts a memory module comprising a memory storage
array and a MCU (Memory Control Unit).
“The storage arrays will typically be constructed with high-density
dynamic RAM (DRAM) components.” The MCU requires a “modest
amount of external logic . . . to interface the MCU to the storage array
RAMs - - for simple configurations, as few as 12 external TTL packages are
required.” (iAPX Manual 1-4.)
I2. The memory module constitutes “a memory confinement area.”
(iAPX Manual 1-8, 3-2.)
I3. A component level constitutes the lowest level of hardware in the
system, an example of which is a RAM chip. A module comprises a group
of interconnected components. (iAPX Manual 2-1.)
Trade Definitions
D1. A “semiconductor memory” is defined as “[a] device for storing
digital information that is fabricated by using integrated circuit technology.
Also known as integrated circuit memory; large-scale integrated memory;
memory chip; semiconductor storage; transistor memory. McGraw-Hill
Dictionary of Scientific and Technical Terms 1791 (5
th
Ed. Sybil E. Parker
1994).
The McGraw-Hill Dictionary also refers to a related definition:
“memory chip [s]ee semiconductor memory.” Id. at 1238.
D2. A “semiconductor device” is defined as “an electronic
component constructed on a small piece of semiconductor (the components
on the device are constructed using patterns of insulator or conductor or
semiconductor material whose properties can be changed by doping).”
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Dictionary of Computing (A & C Black Ed. 2004) (listing previous editions
under copyright to S.M.H. Collin at 1988, 1994, 1998, 2002) avail. at
http://www.credoreference.com/entry/acbcomp/semiconductor_device.
D3. A “semiconductor device” is also defined as “any of a wide
variety of devices that employ the electrical properties of semiconductor
materials, such as silicon, to control the flow of electrons; such devices
include diodes, photocells, and transistors.” Academic Press Dictionary of
Science and Technology (1992) avail. at
http://www.credoreference.com/entry/apdst/semiconductor_device.
LEGAL PRINCIPLES
In reexaminations of non-expired patents, claims are given the
“broadest reasonable construction consistent with the specification.” See In
re Yamamoto, 740 F.2d 1569, 1571 (Fed. Circ. 1984) (not addressing
expired patents). The Federal Circuit has “frequently stated that the words
of a claim ‘are generally given their ordinary and customary meaning.’”
Phillips v. AWH Corp., 415 F.3d 1303, 1312 (Fed. Cir. 2005) (en banc)
(citation omitted), with the caveat that claims “must be read in view of the
specification. . . . [T]he specification ‘is always highly relevant to the claim
construction analysis. Usually, it is dispositive; it is the single best guide to
the meaning of a disputed term.’” Id. at 1315 (citation omitted).
Because the meaning of a claim term as understood by persons
of skill in the art is often not immediately apparent, and because
patentees frequently use terms idiosyncratically, the court looks
to “those sources available to the public that show what a
person of skill in the art would have understood disputed claim
language to mean.”. . . Those sources include “the words of the
claims themselves, the remainder of the specification, the
prosecution history, and extrinsic evidence concerning relevant
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scientific principles, the meaning of technical terms, and the
state of the art.”
Id. at 1314 (citation omitted).

ANALYSIS
Rambus argues generally that a “memory device,” and particularly a
“synchronous semiconductor memory device,” as recited in claim 1, are
each limited to a single “chip.” (App. Br. 1-2, 14-17.) The general term,
“memory device,” is not at issue here even though Rambus devotes
considerable discussion to it and the Examiner correctly responds in kind.
With respect to the specific term at issue, Rambus maintains that “one
of ordinary skill in the art would understand . . . ‘a synchronous
semiconductor memory device’ to be a synchronous memory device
constructed with semiconductor material” (App. Br. 2) and as such, the
iAPX “memory module,” which includes several chips, does not satisfy the
claim term (id. at 1-2). (Accord Reply Br. 5 (“The ‘semiconductor’
limitation, which refers to material used to fabricate a chip, further makes
clear that a single-chip device is being claimed.”).) Rambus also relies on its
expert, Mr. Murphy, who opines that the iAPX’s “collection of 53 separate
and distinct integrated circuit devices is not an integrated circuit device,
much less a synchronous semiconductor memory device.” (Murphy Decl.
¶ 93 (cited at App. Br. 2).)
Apart from the claims, the term “synchronous semiconductor memory
device” does not appear to be in the ‘263 patent. However, the ‘263 patent
refers to a “semiconductor device[]” as “a single memory device” in terms
of “this invention” and refers to “a new bus interface built into
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semiconductor devices.” (P1 (emphasis added).) It also states that “each
semiconductor device contains a set of internal registers” and that
“semiconductor devices” have “memory addresses contained within that
device.” (P2 (emphasis added).) It similarly refers to the interface circuits
internal to a DRAM. (P3.) Discussing related patents claiming continuity
back to the same application as the patent here (App. No. 07/510,898, filed
Apr. 18, 1990), the Federal Circuit defined a similar claim term, “integrated
circuit device,” as a “circuit constructed on a single monolithic substrate,
commonly called a ‘chip’.” Rambus Inc. v. Infineon Technologies AG, 318
F.3d 1081, 1085-86, 1091 (Fed. Cir. 2003) (citations to trade dictionary
definitions to support the plain meaning omitted).
The term “semiconductor memory device” is a well-recognized term
of art which means a “memory chip.” (D1 (defining “semiconductor
memory” as a “memory chip”); accord D2 (defining “semiconductor
device” as a component constructed on a small semiconductor piece); D3
(similar definition and also showing examples of such devices which are
known as single chip devices (e.g., diodes, transistors).) Similarly, the
iRAM handbook at 1-1 states that an engineer using “semiconductor
memories had a simple choice of which memory to use. The 2102 Static
RAM for ease of use and the 1103 Dynamic RAM for low power were the
only devices available.”
1

In a related Rambus reexamination now on appeal to the Federal
Circuit (Appeal No. 2010-0011178, Reexamination No. 90/010420), the

1
Memory Components Handbook, Intel. Corp., Ch. 1, 3 (1985) (“iRAM”)
(cited in the Request for Ex Parte Reexamination at iv, 18).

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Board held that the term “memory device” is not limited to a single chip as
argued by Rambus there and here, but encompasses the two disclosed
embodiments also at issue here, the single chip semiconductor DRAM
embodiment (see ‘263 patent, col. 4, ll. 10-24, Fig. 8A) and the memory
stick embodiment comprising several chips (see id. at Fig. 9).
Of course, the term “synchronous semiconductor memory device” is
narrower than the term “synchronous memory device” (or “memory
device”). The first term, in light of the specification, which refers to the
term “semiconductor device[]” as “the invention” and as a “single memory
device” with internal circuits (see P1 (emphasis added), P2, P3), indicates a
chip, in line with the ordinary and customary meaning (D1, D2, D3) and in
line with the similar Rambus claim term “integrated circuit device” at issue
in Infineon, 318 F.3d at 1091. Mr. Murphy’s testimony is supported by
trade dictionary definitions and the ‘263 patent and is not rebutted here, the
expired ‘263 patent is not afforded “broadest reasonable” claim construction,
cf. Yamamoto, 740 F.2d at 1571, and the Examiner has not shown
persuasively that the claim term “synchronous semiconductor memory
device” embraces the ‘263 patent’s memory stick embodiment and thereby
reads on the iAPX’s memory module (see I1-I3.).
DECISION
The Examiner’s decision to reject appealed claim 1-4 is reversed.
REVERSED

Appeal 2011-013706
Reexamination Control 90/010,574
Patent 5,953,263

9
ak

Finnegan, Henderson, Farabow
Garrett & Dunner, LLP
901 New York Avenue, NW
Washington, DC 20001-4413

Third Party Requester:

Novak Druce & Quigg, LLP
(NDQ Reexamination Group)
1000 Louisiana Street
53
rd
Floor
Houston, TX 77002