Ex Parte 5867422 et al

Board of Patent Appeals and Interferences

Jun 22, 2011

90008853 (B.P.A.I. Jun. 22, 2011)

UNITED STATES PATENT AND TRADEMARKOFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
90/008,853 09/24/2007 5867422 PHJM0904-005 8618
26948 7590 06/23/2011
VENABLE, CAMPILLO, LOGAN & MEANEY, P.C.
1938 E. OSBORN RD
PHOENIX, AZ 85016-7234
EXAMINER
NGUYEN, LINH M
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
06/23/2011 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES
____________

Ex parte LIZY KURIAN JOHN
____________

Appeal 2011-006813
Reexamination Control 90/008,853
Patent 5,867,422
Technology Center 3900

____________

Before SALLY C. MEDLEY, SCOTT R. BOALICK, and STEPHEN C.
SIU, Administrative Patent Judges.

SIU, Administrative Patent Judge.

DECISION ON APPEAL
Appeal 2011-006813
Reexamination Control 90/008,853
Patent 5,867,422

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Patent owner (Appellant) appeals under 35 U.S.C. §§ 134(b) and 306
from a final rejection of claims 1, 5, 6, 8-10, and 18. Claims 2-4, 7, 11-17,
19, and 20 have been confirmed.1 We have jurisdiction under 35 U.S.C.
§§ 134(b) and 306.

STATEMENT OF THE CASE
This proceeding arose from a request for ex parte reexamination filed
by Lattice Semiconductor Corporation on September 24, 2007, of United
States Patent 5,867,422 (the ‘422 Patent) issued to Lizy Kurian John on
February 2, 1999. Presently, claims 1, 5, 6, 8-10, and 18 stand rejected, with
claims 2-4, 7, 11-17, 19, and 20 confirmed as patentable.
The ‘422 patent describes dynamically configuring a memory chip to
different bus widths (col. 1, ll. 9-10). Claim 1, which we deem to be
representative, reads as follows:
1. A field programmable memory cell array including a memory array
composed of a sea of N memory cells addressed by a row decoder and
a column decoder to input or output data by means of input/output
circuits, input data control circuits and output data control circuits as
determined by select/write enable logic, comprising in combination a
programmable address decoder and a programmable interconnect for
selective reconfiguration of the sea of N memory cells to N/k×k bits,
where k is a power of two.

1 Appellant states that claims 19 and 20 are “allowable if resubmitted and
rewritten to include limitations of claim 18” (App. Br.4). The Examiner
does not explicitly state the status of claims 19 and 20. We note, however,
that neither claim 19 nor claim 20 appears to be rewritten to include
limitations of claim 18. Since the Examiner does not indicate that claims 19
and 20 are rejected, we will assume that the Examiner finds claims 19 and
20 to be allowable.
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(App. Br. 7, Claims App’x.)

The Examiner listed and employed the following prior art references:
Yabusaki JP 61-59682 Mar. 27, 1986

Motorola, Product Preview: 1M x 4 / 2M x 2 Bit Fast Static Random Access
Memory with ECL I/O. Motorola Semiconductor Technical Data
publication, admitted by Patent Owner to be prior art (“Motorola”).

Claims 1, 5, 6, and 8-10 are rejected under 35 U.S.C. § 102(b) as being
anticipated by Yabusaki and claims 1, 8, and 18 are rejected as being
anticipated by Motorola.
ISSUE
Appellant’s arguments and the Examiner’s responses primarily
present the issue of whether the Examiner erred in finding that either
Yabusaki or Motorola discloses the claimed invention.

PRINCIPLES OF LAW
Anticipation is established when a single prior art reference discloses,
expressly or under the principles of inherency, each and every limitation of
the claimed invention. Atlas Powder Co. v. IRECO, Inc., 190 F.3d 1342,
1347 (Fed. Cir. 1999); In re Paulsen, 30 F.3d 1475, 1478-79
(Fed. Cir. 1994).

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ANALYSIS
Yabusaki reference
Claim 1
Claim 1 recites reconfiguration of memory cells “to N/k×k bits, where
k is a power of two” (App. Br. 7, Claims Appx.), which Appellant asserts
that Yabusaki fails to disclose (App. Br. 8-13). As indicated by the third
party requester (Req. for Ex Parte Reexamination 12-14 and 20) and the
Examiner (Ans. 11-12), Yabusaki discloses a “variable bit-length memory”
(p. 1, l. 1) in which bit lengths are variable to, for example, “bit lengths of 8,
16, and 32 bits” with corresponding word lengths of “4096, 2048, and 1024,
as shown in Figs. 2(a), (b), and (c)” (p. 4, ll. 27-28, Fig. 2). Since Yabusaki
discloses varying (i.e., “reconfiguring”) memory cells to a number of bits
corresponding to “N/k×k” (where k is equal to any of, for example, 8, 16, or
32, each being a power of two), we agree with the Examiner that Yabusaki
discloses this feature.
Appellant argues that the recited formula “N/k×k” “represents a
mathematical sequence” (App. Br. 9). However, claim 1 fails to recite a
“sequence.” Instead, claim 1 merely recites reconfiguration of memory cells
to “N/k×k bits,” which, as described above, Yabusaki discloses (where k=
any of 8, 16, or 32, for example).
Appellant also argues that claim 1 requires “the ability to select any
term in the sequence, i.e., to select any power-of-two word width” (App. Br.
11). First, as described above, claim 1 merely recites a formula from which
a number of bits may be calculated and does not recite a sequence. Second,
claim 1 recites reconfiguration of memory cells to “N/k×k bits” but does not
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recite or require “any” power-of-two word widths. We agree that claim 1
requires that “k is a power of two” and therefore k is required to be equal to
some value that is “a power of two” (such as, for example, 8, 16, or 32 as
disclosed by Yabusaki). However, we disagree with Appellant that claim 1
also recites and requires that k is equal to “any” (and all) value(s) that is/are
a power of two since Appellant has not sufficiently demonstrated that claim
1 contains such a limitation.
Appellant argues that claim 1 requires that k is “any” value that “is a
power of two” (i.e., not just 8, 16, or 32, for example) because, according to
Appellant, the Specification discloses reconfiguring a memory chip to
“‘N×1 bit, N/2×2 bits, N/4×4 bits, or in general, N/k×k bits, where k is a
power of two’” (App. Br. 9). We disagree with Appellant’s assertion
because the cited passage from the Specification merely restates the claim
limitation of reconfiguring cells to “N/k×k bits.” Appellant has not shown
how the addition of the term “in general” prior to the term N/k×k bits
indicates that any and all values of k in a non-specified “sequence” is
required since the Specification merely discloses that the number of bits is
equal to N/k×k bits, which, as described above, Yabusaki discloses (i.e.,
k=8, 16, or 32).
Claim 1 also recites a “programmable address decoder and a
programmable interconnect” (App. Br. 7, Claims Appx.), which Appellant
argues Yabusaki fails to disclose (App. Br. 19-25 and 28-30). As the third
party requester indicates, Yabusaki discloses an address converting circuit
17, a bit length modifying circuit 16 (p. 9), and a data line switch circuit 19
(p. 10) (Req. for Ex Parte Reexamination 13-14). Also as pointed out by the
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third party requester and the Examiner, Yabusaki discloses a row decoder, a
line decoder (Fig. 1) and that the bit length modifying circuit 16 is “a bit
length mode specifying circuit that selects the bit length of a single address
from among 8, 16, and 32 bits” (p. 4, ll. 18-19).
Appellant argues that a “rigid row decoder 14 and . . . a column
decoder 16 . . . comprises the programmable address decoder” (App. Br.
21). Hence, Appellant argues that Yabusaki fails to disclose a row decoder
and a column decoder, each of which, as implied by Appellant, are required
components of the programmable address decoder as recited in claim 1.
Appellant has not shown that claim 1 requires that the programmable
address decoder, as claimed, requires row and column decoders given that
claim 1 is silent as to what constitutes a “programmable address decoder”
much less that the “programmable address decoder” must include both a row
decoder and a column decoder. Nor does Appellant indicate an explicit
definition in the Specification of “programmable address decoder” as
requiring the inclusion of row and column decoders. For at least this reason,
we are not persuaded by Appellant’s argument. However, even assuming
that both a row and a column decoder are required components of the
programmable address decoder as recited in claim 1, we note (as described
above) that Yabusaki discloses a row decoder and a column decoder (i.e., a
row decoder and a “line decoder,” respectively).
Appellant argues that the “‘programmable address decoder’” as
recited in claim 1 “must decode addresses” (App. Br. 28). Hence, Appellant
implies that Yabusaki fails to disclose decoding addresses which, as implied
by Appellant, is a required function of the programmable address decoder as
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recited in claim 1. First, we find no recitation in claim 1 of “decoding
addresses” or any recited claim limitation that the “programmable address
decoder” decodes addresses. More importantly, however, one of ordinary
skill in the art would have understood “decoding addresses” to include
receiving an input and producing an output based on the input, the output
indicating a desired address or device (or memory cell). Since Yabusaki
discloses a system that “decodes addresses” (identifies a desired address or
memory cell via the row and line decoders, for example), we are not
persuaded by Appellant’s argument, even if we assume that the
programmable address decoder of claim 1 must decode addresses.
Appellant also argues that Yabusaki fails to disclose a programmable
interconnect (App. Br. 30) while the third party requester and the Examiner
state that the “data line switching circuit 19” of Yabusaki is the
“programmable interconnect” as recited in claim 1 (Ans. 5).
Appellant argues that the “data line switching circuit 19” of Yabusaki
is not the same as the “programmable interconnect” as recited in claim 1
because, according to Appellant, the “data line switching circuit 19” of
Yabusaki includes “data buffers” that “are not connected between respective
data lines to change the word width of the memory array” (App. Br. 30).
Hence, Appellant appears to argue that claim 1 requires that the
“programmable interconnect” lacks data buffers and that even if the
“programmable interconnect” may contain data buffers, claim 1 requires that
such data buffers are connected between respective data lines.
We note that claim 1 merely recites that the “programmable
interconnect” – and the programmable address decoder” – are “for
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reconfiguration” of memory cells and does not recite either the presence (or
absence) of data buffers or whether or not the “programmable interconnect”
is connected between respective data lines. Therefore, we are not persuaded
by Appellant’s argument.

Claim 5
Claim 5 recites that the programmable interconnect comprises
switches connected between respective data lines of the input/output circuits,
which Appellant argues Yabusaki fails to disclose (App. Br. 35-37). As the
third party requester (Req. for Ex Parte Reexamination 20) and the Examiner
(Ans. 6) point out, Yabasaki discloses a “data line switching circuit 19” (p.
5, l. 6) that contains switches (i.e., “desired switching is conducted” – p. 5, l.
26). In addition, the switching circuit of Yabusaki is connected between
data lines as illustrated in Figs. 1 and 4, for example. Appellant argues that
in Yabusaki, “it carries the same data and is the same data line” (App. Br.
36). However, as Yabusaki illustrates in Figs. 1 and 4, the switching circuit
is connected between input lines and output lines that appear to be different
(one set of lines being input lines (e.g., D0 to D31) and the other set of lines
being output lines (e.g., (I/O)0 to (I/O)31)).
In addition, Appellant appears to argue that claim 5 requires that
different data be carried on different data lines. We note that claim 5 merely
recites switches between respective data lines of circuits and does not recite
or require that the data on the data lines are specifically different (or the
same).

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Claim 6
Appellant argues that Yabusaki fails to disclose PASS transistors.
The third party requester (Req. for Ex Parte Reexamination 22) and the
Examiner (Ans. 16-17) state that the switches of Yabusaki inherently contain
PASS transistors. Appellant does not dispute this finding (see, e.g., Reply
Br. 12-13). Therefore, the Examiner did not err in rejecting claim 6.

Claim 8
Appellant provides similar arguments as for claim 1 regarding
“selective reconfiguration to the sequence N/k×k” (App. Br. 38). We
disagree with Appellant for at least the reasons set forth above for claim 1.
Claim 8 also recites programming an address decoder and an
interconnect to reconfigure memory cells. Appellant argues that Yabusaki
discloses “controlling” a device but does not disclose “programming” a
device (App. Br. 37-38). Appellant does not indicate a specific definition of
the term “programming” in the Specification. We decline to utilize
Appellant’s narrow and limiting definition of “programming” as requiring
control information to be stored “in advance” (App. Br. 37), particularly
since such usage is further limited only to Appellant’s cited textbook
reference by the authors of the cited textbook themselves (i.e., “We [the
authors] shall consider a system to be programmed . . .” (App. Br. Evid.
Appx 162)). In addition, we disagree with Appellant’s distinction between
“controlling” and “programming” given the disclosure in the Specification
of “programming” an interconnect to reconfigure memory cells as recited in
claim 8 as including data lines in an “interconnect” that “can be controlled
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by . . . control lines . . . to yield any word width. . . .” (col. 5, ll. 64-67)
(emphasis added).
Instead, in the absence of an explicit definition in the Specification,
we turn to a broad but reasonable interpretation of the term as would have
been understood by one of ordinary skill in the art in light of the
Specification as including providing a series or sequence of operations to be
performed to accomplish a task. Such a construction comports with the
Specification’s disclosure of inputting data into “mode control lines” (col. 5,
l. 9) that enable data input into “decoders” (col. 5, l. 28) which provide an
output to “control” data lines “to yield any word width from 16, 8, 4, 2 to 1,
which are powers of two” (col. 5, l. 65 – col. 6, l. 1). We agree with the
Examiner that Yabusaki discloses this feature since Yabusaki also discloses
inputting data into signal lines and selecting a “bit length mode . . . based on
these signal lines” for varying bit lengths (p. 4, ll. 22-28) and Appellant has
not sufficiently demonstrated any differences between Yabusaki and
“programming . . . to selectively reconfigure . . . memory cells” as recited in
claim 8.
Appellant does not provide additional arguments in support of
dependent claims 9 and 10, which depend from claim 8.

Motorola Reference
Claim 1
Appellant argues that “Motorola lacks the ability to reconfigure the
memory array within the sequence N/k×k bits. As set forth above, we
disagree with Appellant’s argument that claim 1 requires a “sequence.”
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Also, as the Examiner points out, Motorola discloses a memory “that can be
electrically reconfigured as 1,048,576 words of 4 bits or 2,097,152 words of
2 bits” (p. 1, ll. 1-2) which comports with the recited claim requirement of
“N/k×k bits.” We are therefore not persuaded by Appellant’s argument.
Appellant also argues that Motorola fails to disclose a programmable
address decoder and a programmable interconnect as recited in claim 1. As
described above, claim 1 merely requires that the programmable address
decoder and programmable interconnect are “for selective reconfiguration of
. . . memory cells to N/k×k bits” (App. Br. 7, Claims Appx.). Since we
agree with the Examiner that Motorola discloses an entity that reconfigures a
memory to N/k×k bits (where k is a power of two) as claimed, we also agree
with the Examiner that Motorola discloses an entity that performs this
function, given that the function is performed in the Motorola reference.

Claim 8
Appellant provides the same arguments in support of claim 8 as for
claim 1. For at least the reasons set forth above, we disagree with
Appellant’s narrow and limiting definition of the term “programming” as
requiring preparing and storing information “in advance . . . to be accessed
by the system when required” (App. Br. 37). We also agree with the
Examiner that Motorola discloses “programming” (i.e., providing a series or
sequence of operations to be performed to accomplish a task) since, as
described above, Motorola discloses performing operations with a random
access memory to reconfigure the memory to N/k×k bits.

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Claim 18
Claim 18 recites reconfiguration of memory cells to at least N x 1 bit,
N/2 x 2 bits, and N/4 x 4 bits. Motorola discloses reconfiguring cells to N/2
x 2 bits (2,097,152 words of 2 bits) or N/4 x 4 bits (1,048,576 words of 4
bits) (p. 2-74). The Examiner does not demonstrate that Motorola also
discloses reconfiguring cells to N x 1 bit as recited in claim 18. Thus, the
Examiner erred in rejecting claim 18 over Motorola.

CONCLUSIONS
We conclude that the Examiner did not err in rejecting claims 1, 5, 6,
and 8-10 as being anticipated by Yabusaki or claims 1 and 8 as being
anticipated by Motorola. We conclude that the Examiner erred in rejecting
claim 18 as being anticipated by Motorola.

DECISION
The Examiner’s decision to reject appealed claims 1, 5, 6, and 8-10 is
affirmed and the Examiner’s decision to reject claim 18 is reversed.
Requests for extensions of time in this ex parte reexamination
proceeding are governed by 37 C.F.R. § 1.550(c). See 37 C.F.R. § 41.50(f).

AFFIRMED-IN-PART
rvb

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Patent Owner

VENABLE, CAMPILLO, LOGAN & MEANEY, P.C.
1938 E. OSBORN RD
PHOENIX, AZ 85016-7234

Third Party Requester

MARK L. BECKER
LATTICE SEMICONDUCTOR CORP.
5555 NE MOORE COURT
HILLSBORO, OR 97124-6421