Ex Parte 5867422 et al

Patent Trial and Appeal Board

Oct 30, 2014

90012396 (P.T.A.B. Oct. 30, 2014)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
90/012,396 07/17/2012 5867422 71448-0006.US01 1015
26948 7590 10/31/2014
VENABLE, CAMPILLO, LOGAN & MEANEY, P.C.
1938 E. OSBORN RD
PHOENIX, AZ 85016-7234
EXAMINER
GE, YUZHEN
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
10/31/2014 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte LIZY K. JOHN
Appellant
____________

Appeal 2014-007900
Reexamination Control 90/012,396
Patent 5,867,422
Technology Center 3900
____________

Before STEPHEN C. SIU, DAVID M. KOHUT, and
JENNIFER L. MCKEOWN, Administrative Patent Judges.

SIU, Administrative Patent Judge.

DECISION ON APPEAL

STATEMENT OF THE CASE

This is an appeal under 35 U.S.C. § 134 from the Examiner’s rejection
of claim 18. Claims 2-4, 7, 11-17, and 19 are not subject to reexamination.
Final Rej. 2. Claims 1, 5, 6, and 8-10 were cancelled.
1
The Examiner
confirms the patentability of claims 20-29.
2
App. Br. 3. We have
jurisdiction under 35 U.S.C. § 6(b).

1
Reexamination Control 90/008,853.
2
The Examiner withdraws the rejection of claims 21-24 and 26-28 under
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The disclosed invention relates generally to configuring a memory
chip to different I/O bus widths. Spec. 1:8-10.
Independent claim 18 reads as follows:
18. A field programmable memory cell array composed of
a sea of N memory cells addressed by a row decoder and a column decoder
to input or output data by means of input/output circuits, input data control
circuits and output data control circuits as determined by select/write enable
logic, comprising in combination,
a programmable address decoder; and
a programmable interconnect; for selective reconfiguration of the sea
of N memory cells to at least N x 1 bit, N/2 x 2 bits, and N/4 x 4 bits.

The Examiner relies on the following references:
Gelsomini US 4,893,280 Jan. 9, 1990

Motorola, Semiconductor Technical Data, Product Preview, 1M x 4
Bit Fast Static Random Access Memory with ECL I/O, 1994 (“Motorola”).

The Examiner rejects claim 18 under 35 U.S.C. § 102(b) as
anticipated by Gelsomini and under 35 U.S.C. § 103(a) as unpatentable over
Gelsomini and Motorola.

ISSUE
Did the Examiner err in rejecting claim 18?

35 U.S.C. § 112, first paragraph and second paragraph. Ans. 2.
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ANALYSIS
Claim 18 recites a memory cell array and a programmable
interconnect for selective reconfiguration of the sea of N memory cells to at
least N x 1 bit, N/2 x bits, and N/4 x 4 bits.
As the Examiner points out, Gelsomini discloses a memory array
(e.g., “memory having 8192 cells” – col. 4, 10-11) and an “organizer” block
(or circuit) “interposed between terminals D1 to D8 and the memory array.”
Gelsomini, 5:13-15. Gelsomini also discloses that, via the organizer block,
“memory assembly is obtained that can be organized in four different
patterns” and that the 4 different exemplary patterns are “8-bit words,” “4-
bit words,” “2-bit words,” and “1-bit words.” Gelsomini, 7:46-47, 50, 55,
61; 7:66 – 8:4. In other words, Gelsomini discloses a memory array and a
“programmable interconnect” (i.e., an “organizer” block or circuit) for
selective reconfiguration of memory cells to 1 bit, 2 bits or 4 bits, as recited
in claim 18.
Patent Owner argues that “the Gelsomini reference was non-enabling
for a memory array that is reconfigurable to at least 1, 2, and 4 bit words
(i.e., claim 18)” because, according to Patent Owner, “Gelsomini’s design
was critically flawed” because memory cells supposedly “suffer from
floating bits” that allegedly result in “power consumption surges and will
ultimately destroy the device.” PO App. Br. 17-20 (citing Declaration of Dr.
Steven Guccione Declaration (’396 Reexam) (“Guccione Decl.”) at ¶¶ 23,
25, 29-31). We are not persuaded by Patent Owner’s arguments.
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Dr. Guccione avers that “because the input state can flip randomly as
a result of current leakage,” “the supply current may dramatically increase . .
. and destroy the device once the disconnected input picks up noise and
begins to oscillate.” Guccione Decl. ¶ 24. Neither Patent Owner nor Dr.
Guccione provides sufficient evidence supporting the contention that the
Gelsomini reference discloses a system that must exhibit “current leakage,”
will necessarily suffer a “dramatic[ ] increase” in supply current, and will
invariably become “destroy[ed].” Nor does Patent Owner or Dr. Guccione
provide evidence or demonstrate sufficiently that current leakage or an
increase in supply current will, in fact, invariably result in destruction of the
circuit. Indeed, Gelsomini explicitly discloses that “words that are being
written in or read from the memory . . . are comprised of variable bit groups,
namely 8 or 4 or 2 or 1 bits” (Gelsomini, 7:66 – 8:1) and does not disclose
that the system will necessarily suffer from “current leakage,” a dramatic
increase in supply current, or will become destroyed.
We also note that claim 18 does not recite that the system never
experiences “current leakage,” that supply current never “dramatically
increase[s],” or that the device will never “pick[ ] up noise and begin to
oscillate.” Thus, even assuming that the system disclosed by Gelsomini
will, at least on occasion, experience current leakage, an increase in supply
current, noise, or oscillation (Patent Owner has not demonstrated this to be
the case, however), we are not still not persuaded by Patent Owner’s
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argument that Gelsomini is supposedly not enabling for the features recited
in claim 18.
In addition, even if the Gelsomini system would potentially
experience “power consumption surges” on occasion or would become
“destroy[ed]” at some point in time, the issue is whether the system
disclosed by Gelsomini would be enabling for a claimed system that
contains a programmable interconnect for selective reconfiguration of
memory cells, as recited in claim 18. Patent Owner or Dr. Guccione has not
demonstrated sufficiently that the possibility that the system of Gelsomini
might experience a “power consumption surge” would render the disclosure
of Gelsomini non-enabling for the claimed invention. For example, Patent
Owner or Dr. Guccione fails to demonstrate persuasively that prior to the
presumed destruction of the system, the system of Gelsomini would fail to
configure memory cells as recited in claim 18 or that one of ordinary skill in
the art would have had to engage in undue experimentation to achieve
reconfiguration of memory cells, as recited in claim 18. In fact, Gelsomini
explicitly discloses that the “memory assembly . . . can be organized in four
different patterns” including “8 or 4 or 2 or 1 bits.” Gelsomini, 7:44-46, 68;
8:1.
Dr. Guccione testifies that, in one embodiment, Gelsomini discloses
that “8-bit words (D1 to D8) can be applied through port B, by using ten
standard addresses (B0 to B9 . . .) to reach the memory through terminals E1
to E8” but that Gelsomini fails to “disclose a circuit or discuss a method for
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individually enabling each of the 8 memory cells intended for the 8 bit
word.” Guccione Decl. ¶ 23. We are not persuaded by Patent Owner’s
declarant’s (Dr. Guccione) argument.
Claim 18 recites “a programmable address decoder” and a
programmable interconnect “for selective reconfiguration of the sea of N
memory cells to at least N x 1 bit, N/2 x 2 bits, and N/4 x 4 bits.” Claim 18
does not recite a circuit “for individually enabling each of the 8 memory
cells intended for the 8 bit word.” As previously discussed, Gelsomini
discloses that “words . . . are . . . written in or read from the memory . . .
comprised of variable bit groups.” Gelsomini, 7:66-68. Hence, contrary to
Patent Owner’s declarant’s argument, Gelsomini discloses “selective
reconfiguration” of memory cells, as recited in claim 18. Even assuming
Patent Owner’s declarant’s statement to be correct that Gelsomini fails to
disclose a circuit “for individually enabling each of the 8 memory cells
intended for the 8 bit word,” Patent Owner does not demonstrate sufficiently
that such a feature is recited in claim 18.
Dr. Guccione testifies that “Gelsomini’s design will produce . . .
‘floating’ driver inputs” and that “[f]loating driver inputs values [are] not
recommended because they produce undefined values that will overwrite
previously written memory information.” Guccione Decl. ¶ 25. Patent
Owner further argues that “because Gelsomini’s organizer circuit and
ADDRESS DECODE will overwrite previously stored data . . . what was
previously written and stored data cannot be relied on and is now
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meaningless . . . [and] therefore [Gelsomini] fails of its essential purpose and
cannot be . . . ‘a memory device’.” App. Br. 16.
Patent Owner or Dr. Guccione does not provide sufficient evidence
supporting the contention that Gelsomini discloses ‘“floating’ driver inputs.”
Even if Gelsomini discloses ‘“floating’ driver inputs,” Dr. Guccione fails to
provide adequate evidence or demonstrate sufficiently that any such
‘“floating’ driver inputs” would “produce undefined values” or the
overwriting of “previously written memory information.” Even if Gelsomini
discloses the production of “undefined values” or overwriting information,
Dr. Guccione fails to provide adequate evidence or demonstrate sufficiently
that such would be “not recommended.” Even if any “undefined values” or
overwriting information in the system of Gelsomini would be “not
recommended,” Dr. Guccione fails to provide adequate evidence or
demonstrate sufficiently that such would indicate that Gelsomini is not
enabling for the invention recited in claim 18 – which recites none of a
preclusion of all floating driver inputs, a preclusion of overwriting
information, or the use of non-recommended values, for example.
While Patent Owner argues that a device that overwrites data cannot
be “a memory device,” Patent Owner and Dr. Guccione fail to provide
adequate evidence or demonstrate sufficiently a logical rationale as to why a
device that overwrites data over previously stored (and no longer desired)
data cannot be “a memory device,” particularly since such a device would
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use “memory” to “previously store[ ]” and currently “overwrite[ ]” (and
store) data.
Dr. Guccione testifies that “during x1 bit write operation,” the
“organizer circuit” of Gelsomini “will write one bit of the memory row.”
Dr. Guccione also proposes an example in which “the organizer circuit [of
Gelsomini] will enable T17 to transfer via E2 a ‘1’” but that “[o]n a
subsequent write to any cell . . . all stored data including previously written
data will be lost and overwritten.” Guccione Decl. ¶¶ 29, 30. Dr. Guccione
concludes that “[b]ecause Gelsomini loses or overwrites previously written
data for bit widths of less than 8 bits, it fails to function as its essential
purpose.” Guccione Decl. ¶ 31. We are not persuaded by Patent Owner’s
declarant’s argument.
Dr. Guccione does not provide sufficient evidence supporting the
contention that the system of Gelsomini “fails to function as its essential
purpose” or what Dr. Guccione believes the alleged “essential purpose” of
Gelsomini to be. In any event, the issue before us is whether Gelsomini is
an enabling reference for the claimed invention. As previously discussed,
Gelsomini discloses, for example, a programmable interconnect (or
“organizer”) that selectively reconfigures memory (i.e., organizes memory
assemblies to obtain different patterns of bit groups – see, e.g., Spec. 7:44-
49, 66-68), as recited in claim 18.
For example, Gelsomini discloses that “1-bit words (D1) can be
applied to port B, by using ten standard addresses (B0 to B9) plus three
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additional addresses B10, B11, B12 through pins D6, D7, D8, to selectively
reach the memory through any of terminals E1 to E8.” Gelsomini, 7:61-65.
By doing so, words “being written in or read from the memory” are
“comprised of variable bit groups, namely . . . 1 bit.” Id. at 7:66 – 8:1.
Patent Owner and Dr. Guccione do not demonstrate persuasively how
overwriting of undesired data (at “E2,” in Patent Owner’s example) would
interfere with this process. Hence, even assuming Dr. Guccione’s statement
to be correct that Gelsomini’s system would overwrite “previously written
data,” Dr. Guccione (or Patent Owner) does not demonstrate sufficiently
how overwriting previously written data would result in the inability to
reconfigure memory cells, as recited in claim 18.
Dr. Guccione further testifies that “Gelsomini’s [system] is useful
to . . . enable read-access to the memory for 1, 2, 4, and 8 bit widths, but it is
incapable of true read and write access for any bit width less than 8 bits”
and argues that “Gelsomini therefore fails to disclose a memory device
“. . . addressed by a row decoder and a column decoder to input or output
data.” Guccione Decl. ¶¶ 32, 33. Hence, Dr. Guccione states that
Gelsomini discloses (and enables) a memory device to input data but fails to
disclose that the memory device also outputs data. As previously discussed,
Dr. Guccione does not demonstrate persuasively that this is the case. In any
event, claim 18 recites a device “to input or output data.” Even assuming
Dr. Guccione’s contention to be correct that Gelsomini discloses a memory
device that inputs data (i.e., reads data), Dr. Guccione (or Patent Owner)
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does not demonstrate sufficiently a difference between this feature that is
undisputed to be disclosed by Gelsomini and the claim feature of a device to
input (or output) data.
Patent Owner argues that “Gelsomini fails to disclose that ADDRESS
DECODE has any other capability than selecting 8 bits at time,” that
Gelsomini “requires use of . . . the organizer circuit,” and, based on these
alleged observations, concludes that the “flaw renders Gelsomini inoperable
for bit widths other than 8 bits.” App. Br. 13.
Claim 18 recites “a programmable address decoder.” Claim 18 does
not recite that the programmable address decoder has a capability of
selecting 8 bits at a time, much less having additional capabilities above and
beyond selecting 8 bits at a time. In any event, Patent Owner does not
explain sufficiently how the programmable address decoder (or ADDRESS
DECODER of Gelsomini) having (or not having) the capability of selecting
different bits at a time would indicate that the Gelsomini’s system (that also
utilizes an “organizer circuit” for this purpose – see, e.g., Gelsomini, Fig. 1)
would be “inoperable.”
Patent Owner argues that “[o]nce properly challenged, the PTO can
no longer rest on conclusions drawn from the presumed operability of the
cited art” and that “the examiner failed to explain how one of skill in the art
‘could make or use [a device according to claim 18] without undue
experimentation based on the disclosure of [Gelsomini].’” App. Br. 18. For
at least the reasons previously discussed, we disagree that Patent Owner has
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“properly challenged” the operability of Gelsomini. Even assuming that
Patent Owner has, in fact, “properly challenged” the operability of
Gelsomini, we agree with the Examiner that Gelsomini would have been
enabling for the claimed invention. See, e.g., Ans. 3-12. Patent Owner does
not provide sufficient arguments or evidence pointing out the supposed
flaws in the Examiner’s reasoning.
Appellant does not provide additional arguments with respect to
Motorola.

SUMMARY

We affirm the Examiner’s rejection of claim 18 under 35 U.S.C. §
102(b) as anticipated by Gelsomini and under 35 U.S.C. § 103(a) as
unpatentable over Gelsomini and Motorola.

AFFIRMED

alw

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PATENT OWNER:
VENABLE, CAMPILLO, LOGAN & MEANEY, P.C.
1938 E. OSBORN RD.
PHOENIX, AZ 85016-7234

THIRD PARTY REQUESTER:

PERKINS COIE LLP
PATENT-SEA
P.O. BOX 1247
SEATTLE, WA 98111-1247