Ex Parte 4918645 et al

Board of Patent Appeals and Interferences

Sep 28, 2006

90007420 (B.P.A.I. Sep. 28, 2006)

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The opinion in support of the decision being
entered today was not written for publication
and is not binding precedent of the Board
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UNITED STATES PATENT AND TRADEMARK OFFICE

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BEFORE THE BOARD OF PATENT APPEALS
AND INTERFERENCES

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Ex parte LG ELECTRONICS, INC.

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Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420
Merged Reexamination Proceedings

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ON BRIEF
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Before BARRETT, LEE, and MEDLEY, Administrative Patent Judges.

BARRETT, Administrative Patent Judge.

DECISION ON APPEAL
This is a decision on appeal under 35 U.S.C. § 134(b) from
the final rejection of claims 1, 6, 12, and 17. Amended claims 2
and 13 have been determined to be patentable, and the
patentability of claims 3-5, 7-11, 14-16, and 18-20 has been
confirmed.
We reverse, but enter new grounds of rejection as to
claims 1, 6, 12, and 17.

REEXAMINATION
A first "Request for Ex Parte Reexamination," Control
No. 90/006,789 ('6789 Reexam), was filed October 14, 2003, by
Third Party Requester James S. Hsue, for reexamination of
U.S. Patent 4,918,645 (the '645 patent), entitled "Computer Bus
Having Page Mode Memory Access," issued April 17, 1990, to
inventor Brian E.J. Lagoy, Jr., based on Application 07/098,449,
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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filed September 17, 1987. The '645 patent is now assigned to LG
Electronics Inc. of the Republic of Korea (patent owner).
A second "Request for Ex Parte Reexamination," Control
No. 90/007,420 ('7420 Reexam), was filed February 14, 2005, by
Third Party Requester Mr. Hsue.
The '6789 and '7420 Reexam proceedings were merged pursuant
to 37 CFR § 1.565(c) (Paper entered April 5, 2005, p. 3: it is
noted that the decision summary mistakenly refers to the '7007
and '7371 Reexams).

LITIGATION
The '645 patent has been involved in numerous judicial
proceedings, as summarized on pages 3-4 of the brief. The most
recent decision is LG Electronics, Inc. v. Bizcom Electronics,
Inc., 453 F.3d 1364, 79 USPQ2d 1443 (Fed. Cir. 2006).

BACKGROUND
The invention of apparatus claim 1 is succinctly described
in LGE v. Bizcom, 453 F.3d at 1373, 79 USPQ2d at 1450:

The '645 patent discloses a digital computer system
that has devices called agents that are interconnected by a
system bus. The claimed system and corresponding method
require one agent, the requesting agent, to request access
to a memory stored on another agent, called the replying
agent. The requested data is organized as a matrix of
memory cells, having column and row coordinates. The
"memory controller" of the replying agent processes the
request from the requesting agent by asserting a plurality
of memory address control signals, including at least one
row address strobe ("RAS") signal and one column address
strobe ("CAS") signal. This "page mode memory access"
operates by the assertion of an entire row of data followed
by the assertion and deassertion of multiple column
addresses. By the RAS signal accessing an entire row
followed by the assertion and deassertion of particular
column addresses, this page mode memory access differs from
the conventional memory access, which separately accessed
each memory cell by asserting its individual row address and
column address. In the claimed invention, after the data is
accessed, it is then transferred to the requesting agent
over the system bus.

Dependent claims 2 and 6 of the '645 patent, which each depended
from claim 1, have been amended to put them in independent form
by incorporating the limitations of claim 1. Claim 2 adds
limitations regarding refreshing the memory and claim 6 adds
limitations regarding incrementing the row address when crossing
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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a memory page boundary. Method claims 12, 13, and 17 generally
correspond to apparatus claims 1, 2, and 6, respectively.
Claim 1 is reproduced below.

1. Memory control apparatus for use in a data processing
system having at least a requesting agent and said [sic]
replying agent electrically coupled together by a system
bus, the requesting agent requesting access to a memory on
the replying agent for storing and retrieving data therein
over the system bus, the apparatus comprising:

means, associated with a replying agent, for detecting
a request for initiating an access to a memory on the
replying agent, the request detecting means being coupled
to a system bus, and request being made over the system
bus by a requesting agent;

means, responsive to the request detecting means
detecting the request, for asserting a plurality of
memory address control signals for accessing a plurality
of times the memory on the replying agent, the control
signals comprising at least a row address strobe signal
associated with a memory row address and a column address
strobe signal associated with a memory column address;
and

means for detecting a completion of the access to the
memory, the completion detecting means being responsive
to an end of access control signal generated by the
requesting agent, the access completion detecting means
being coupled to the memory address control signal
asserting means for halting the operation thereof after
the end of access control signal is detected; and wherein

the memory address control signal asserting means
asserts the memory address control signals by asserting the
row address strobe in conjunction with a row address being
indicative of a page of data within the memory, and
thereafter asserts and deasserts a plurality of times the
column address strobe signal in conjunction with a plurality
of column addresses for performing a page mode type of
memory access.

THE REFERENCES

The examiner relies on the following references:

Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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Bruce 4,546,451 October 8, 1985

iSBC® 286/100 Multibus® II Single Board Computer,
Intel Corp., March 1985 ("286/100").

2164A Family, 65,536 x 1 Bit Dynamic RAM, April 1982,
Intel Corp., pages 3-267 to 3-279 ("2164A").

Multibus® II Bus Architecture Specification Handbook,
Intel Corp., 1984 ("Multibus II").

iSBC® MEM/312/310/320/340 Memory Boards User's Guide,
Intel Corp., February 1985 ("iSBC MEM/3XX").

THE REJECTIONS
Pages of the final rejection entered July 20, 2005, are
referred to as "FR " and pages of the examiner's answer entered
December 21, 2005, are referred to as "EA ." Pages of the
Patent Owner's brief received October 11, 2005, are referred to
as "EA " and pages of the reply brief received February 8, 2006,
are referred to as "RBr ."
Claims 1 and 12 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over "286/100" and "2164A." "Multibus II" and
"iSBC MEM/3XX" are used as extrinsic evidence to support inherent
features of the system described in "286/100."
Claims 6 and 17 stand rejected under 35 U.S.C. § 103(a) as
being unpatentable over "286/100," "2164A," and Bruce. Since
claims 6 and 17 contain the limitations of claims 1 and 12,
respectively, the rejection impliedly also relies on
"Multibus II" and "iSBC MEM/3XX."

DISCUSSION
Claim interpretation
We accept and incorporate by reference the definitions of
claim terms in Patent Owner's "Summary of Claimed Subject Matter"
(Br7-26) for purposes of this appeal. Because the definitions
are based on the Multibus II standard in the document High
Performance 32-Bit Bus Standard P1296 (unapproved draft), IEEE,
June 20, 1986, which is incorporated in the '645 patent (col. 3,
lines 51-56), which in turn is based on the Multibus II standard
in "Multibus II" in the rejection, the definitions are not at
issue.
With respect to apparatus claims 1, 2, and 6, Patent Owner
states that the means for performing the function of "detecting a
request for initiating an access to a memory on the replying
agent" is "circuitry within or associated with the memory
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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controller 66 alone or in combination with decoder 70, and
equivalents thereof" (Br9) and that the means for performing the
functions of "asserting a plurality of memory address control
signals for accessing a plurality of times the memory of the
replying agent" and "detecting a completion of the access to
memory" is "the circuitry within or associated with the memory
access control portion of the memory controller 66, and
equivalents thereof" (Br9; Br10). No circuitry is disclosed in
connection with the block diagram of the memory controller 66 in
Fig. 5. This raises a potential question of whether the claims
are indefinite under 35 U.S.C. § 112, second paragraph, for
failing to adequately disclose structure corresponding to the
claimed functions since the memory controller is the invention
and, unlike a block corresponding to a commercially available
unit, presumably would not have been understood by a person
skilled in the art to disclose structure capable of performing
the recited function. See Medical Instrumentation and
Diagnostics Corp. v. Elekta AB, 344 F.3d 1205, 1213-1214,
68 USPQ2d 1263, 1270-71 (Fed. Cir. 2003). This is not the same
as enablement. However, since claim 1 is an original patent
claim and claims 2 and 6 incorporate the subject matter of
claim 1, the § 112 issue is not appropriate for consideration in
a reexamination proceeding. See 37 CFR § 1.552. It is proper to
note the existence of the issue. See § 1.552(c).
Since no structure is disclosed for the block diagram, we
assume that any structure for performing the claimed functions is
at least an equivalent of the "means."
There is a claim interpretation issue as to whether
apparatus claims 1, 2, and 6 are directed to a "memory control
apparatus" alone or in combination with a data processing system.
Claims 2 and 6 share the limitations of claim 1, so we limit the
discussion to claim 1. The preamble recites a "[m]emory control
apparatus for use in a data processing system having at least a
requesting agent and said [sic] replying agent electrically
coupled together by a system bus, the requesting agent requesting
access to a memory on the replying agent for storing and
retrieving data therein over the system bus, the apparatus
comprising: . . . ." The preamble seems to indicate that what is
being claimed is the memory control apparatus and that the
limitations following "for use in" are statements of intended
use, which only limit the claims to the extent that the memory
control apparatus must be capable of being used in such an
environment. See Boehringer Ingelheim Vetmedica, Inc. v.
Schering-Plough Corp., 320 F.3d 1339, 1345, 65 USPQ2d 1961, 1965
(Fed. Cir. 2003) ("An intended use or purpose usually will not
limit the scope of the claim because such statements usually do
no more than define a context in which the invention operates.").
The body of the claim is mostly consistent with this "intended
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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use" interpretation, e.g., the "memory address control signal
asserting means" in the last paragraph produces row and column
address strobe signals, but does not positively require that the
signals access a memory. However, the first subparagraph of the
claim body recites "the request detecting means being coupled to
a system bus, and request being made over the system bus by a
requesting agent," which positively recites at least a system bus
in combination with the memory control apparatus and requires
that the request come from a requesting agent as defined in the
preamble. A similar issue exists with respect to whether method
claims 12, 13, and 17 claim the method for controlling a memory
alone or as part of a method on a data processing system. To
avoid these claim interpretation issues, we assume that the
memory controller apparatus and method for controlling a memory
require a requesting agent and replying agent electrically
coupled together by a system bus. That way, if the claims
require less, they are still met.

Examiner's rejection
The "286/100," "Multibus II," and "iSBC MEM/3XX" references
collectively describe a data processing and memory system using
the Multibus II bus architecture and protocols. "Multibus II"
describes the terminology, structure, and bus protocol of the
Intel Multibus II Parallel System bus iPSB shown in "286/100,"
and "iSBC MEM/3XX" describes the structure of the iSBC MEM/3XX
memory board shown in "286/100." A claim chart comparing claim 1
to the system collectively described in "286/100," "Multibus II,"
and "iSBC MEM/3XX" is shown below.

Claim 1

Collective teachings of
"286/100," "Multibus II,"
and "iSBC MEM/3XX"

1. Memory control apparatus for
use in a data processing system
having at least a requesting
agent and said [sic] replying
agent electrically coupled
together by a system bus,
"Multibus II" teaches
"requesting agents" and
"replying agents" electrically
coupled by an iPSB Parallel
System bus (Figure 1-2;
sheet 2-6).

Figure 1 of "286/100" teaches a
"requesting agent" (286/100
single board computer) and a
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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"replying agent" (iSBC MEM/3XX
memory board) "electrically
coupled together by a system
bus" (Multibus II Parallel
System bus iPSB).

"iSBC MEM/3XX" teaches a
"Controller Subsystem" that
controls access to the "DRAM
subsystem" and the "Cache
Subsystem" and corresponds to a
"memory control apparatus."
Figure 2-1. "[T]he Controller
Subsystem provides the control
logic necessary to perform
transfer cycles on the iPSB and
iLBX buses." Page 2-5.

the requesting agent requesting
access to a memory on the
replying agent for storing and
retrieving data therein over
the system bus, the apparatus
comprising:

"Multibus II" teaches that the
"requesting agent" sends an
address and request for access
to memory over the system bus.
See description of transfer
cycle at sheets 2-44 through
2-49. During the request phase
of the transfer cycle, the
requesting agent puts command
signals on the system bus for
memory access, e.g., SC0*
indicates a request, SC4* and
SC5* indicate a memory access,
and SC6* indicates whether the
operation is a read or a write
(sheet 2-22), and address
signals on the address/data bus
lines AD31* through AD0*
(sheet 2-17). During the reply
phase of the transfer, data is
transferred over the
address/data bus (sheet 2-17).

means, associated with a
replying agent, for detecting a
request for initiating an
access to a memory on the

"Multibus II" teaches that the
"replying agent," which is
coupled to the system bus,
detects a command for
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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replying agent, the request
detecting means being coupled
to a system bus, and request
being made over the system bus
by a requesting agent;
initiating access to memory on
the replying agent. E.g.,
Sheet 2-10. The request for
access is made over the system
bus by a requesting agent using
the bus system control signals
SC9* through SC0* (sheets 2-17
through 2-22) and the bus
address/data signals AD31*-AD0*
(sheet 2-17).

means, responsive to the
request detecting means
detecting the request, for
asserting a plurality of memory
address control signals for
accessing a plurality of times
the memory on the replying
agent, the control signals
comprising at least a row
address strobe signal
associated with a memory row
address and a column address
strobe signal associated with a
memory column address; and

"286/100" and "Multibus II" do
not teach specifics of how a
"replying agent" performs a
memory access.

In "iSBC MEM/3XX," "the
Controller Subsystem provides
the control logic necessary to
perform transfer cycles on the
iPSB and iLBX buses" (p. 2-5),
where "transfer cycles" include
memory accesses. The cache
memory controller (CMC) gate
array logic controls the iPSB
and iLBX II bus interfaces, and
controls and initializes the
cache and DRAM arrays
(Figure 2-1; p. 2-6). The DRAM
arrays are controlled using row
address strobe logic and column
address strobe logic
(Figure 2-1; p. 2-3).

means for detecting a
completion of the access to the
memory, the completion
detecting means being
responsive to an end of access
control signal generated by the
requesting agent, the access
completion detecting means
being coupled to the memory
address control signal
asserting means for halting the

"Multibus II" teaches that the
"replying agent" detects an
"end of cycle (EOC)" signal
from the "requesting agent"
during the reply phase and
thereafter halts access to the
memory. See signal SC2*
(sheet 2-23) and description of
transfer cycle at sheets 2-44
through 2-49.
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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operation thereof after the end
of access control signal is
detected; and wherein

the memory address control
signal asserting means asserts
the memory address control
signals by asserting the row
address strobe in conjunction
with a row address being
indicative of a page of data
within the memory, and
thereafter asserts and
deasserts a plurality of times
the column address strobe
signal in conjunction with a
plurality of column addresses
for performing a page mode type
of memory access.

The iSBC MEM/3XX memory board
in "286/100" uses 2164 DRAMs.
See "iSBC MEM/3XX," Fig. 10-2,
p. 10-29. 2164 DRAM chips have
a page mode of memory access.

Difference: None of "286/100,"
"Multibus II," and
"iSBC MEM/3XX" discloses a
memory controller controlling
DRAMs in a page mode of access.

The examiner finds and addresses the difference between the
collective teachings of "286/100," "Multibus II," and
"iSBC MEM/3xx" as follows (FR5):

"286/100" (as supported by "[iSBC MEM/3XX]") does not
specifically teach that the 2164 DRAM chips of the iSBC®
MEM/3xx memory board are selected to be utilized in the page
mode (wherein page mode [operates as claimed]). However, it
would have been obvious to one of ordinary skill in the art
to have utilized the page mode operation of the 2164 DRAM
chip on the iSBC® MEM/3xx memory board in the system of
"286/100" because "2164A" teaches on page 3-278, right
column, second paragraph under "Page Mode Operation" that
page mode operation allows a maximum data transfer rate.

"2164A" is used only for its description of the advantage of a
page mode of operation. There is no dispute that 2164 DRAMs have
the same page mode as in "2164A.".
Patent Owner argues that the examiner errs in finding that
"286/100" and "2164A" teach the follow elements (Br30):

(1) "memory address control signal asserting means . . . for
performing a page mode type of memory access"
(claim 1), or "asserting a plurality of memory address
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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control signals . . . for performing a page mode type
of memory access" (claim 12).

(2) a "requesting agent requesting access to a memory on the
replying agent for storing and retrieving data therein
over the system bus" (claims 1 and 12). Claim 1 also
recites a "request being made over the system bus by a
requesting agent."

We reject Patent Owner's second argument. "Multibus II"
discloses memory access between a requesting agent and a replying
agent over the Parallel System bus iPSB (e.g., Figure 1-2,
sheet 1-9; Figure 1-2, sheet 2-6). "iSBC MEM/3XX" discloses that
memory access can take place over either the Parallel System bus
iPSB or the Local Extension bus iLBX II (Figure 2-1, page 2-2).
Although Patent Owner argues that memory access would take place
over the iLBX II, which is not a system bus, the references
clearly teach that memory access can take place over the system
bus iPSB.
As to the Patent Owner's first argument, the examiner
responds that modifying "286/100" to provide page mode operation
"would not be beyond the knowledge of one of ordinary skill in
the art, particularly given the numerous patent documents
available at the time of the invention which show the use of a
page mode operation" (EA9), which we interpret to mean that it
would have been obvious to modify the memory controller inherent
in "286/100" to perform page mode operation given the advantage
of page mode operation. The issue is whether it would have been
obvious to modify the cache memory controller on the iSBC MEM/3XX
memory board in "286/100" to utilize the page mode. See, e.g.,
Br37 ("A critical question is whether there is any teaching or
suggestion in the references of record to modify the 286/100
system board by adding a page mode memory controller capable of
accessing the 2164 DRAM in page mode."); Br38 ("The issue is not
whether the cited references teach that it is possible to use a
2164 DRAM in a system they describe, but whether it would have
been obvious to modify such a system to support page mode access
to that DRAM.").
We agree with the examiner that one of ordinary skill in the
art would have been motivated, in general, at the time at the
time of the invention to design a memory controller for page mode
operation to achieve the advantage of a maximum data transfer
rate, i.e. to use a known element for its intended purpose and
advantage.
The weak point in the examiner's rejection is that the
iSBC MEM/3XX board is a "cache-based" memory. Patent owner
argues that a person of ordinary skill in the art would not have
had a reasonable expectation of success of modifying "286/100" to
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Reexamination Control Nos. 90/006,789 and 90/007,420

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use page mode access (Br41). It is argued that a person
attempting to redesign the iSBC MEM/3XX board for a page mode of
memory access "would face substantial complexities stemming from,
and incompatibilities between the new circuitry and the existing
memory board" (Br42). "One such source of incompatibility is
within the cache memory subsystem on the iSBC MEM/3xx memory
board" (id.) because if the 2164 DRAMs are accessed in page mode
the memory board must ensure that the cache access method is
compatible or the cache subsystem may function improperly. It is
also argued that the Hoffman declaration states that cache allows
the use of inexpensive and relatively slow DRAM and that a person
skilled in the art would have "realized that choice by the memory
board manufacturer of using a cache implied that adding faster
DRAM or page mode DRAM would have had little or no effect on
performance" (id.). It is argued that timing and programming for
page mode control signals are not taught and "[w]ithout any such
teaching, a person of ordinary skill in the art would be left
simply to guess at a correct timing sequence for page mode
operations to provide a 'memory address control signal asserting
means' that is capable of 'performing a page mode type of memory
access'" (Br43). It is argued that "the re-design would have to
avoid interfering with the chip's capability to access and
interface properly with other components on the memory board as a
whole" (id.). It is lastly argued that page mode access requires
storage functionality that is not taught by the references (id.).
The examiner responds (EA14-15):

[O]ne of ordinary skill in the art would not face
substantial complexities in adding the functionality of
accessing the 2164A DRAM memories of the iSBC MEM/3xx memory
board. The fact that the memory board may perform other
functions (i.e. caching, as cited in the Hoffman
declaration) does not create a barrier to adding the
functionality of page mode accessing the 2164A DRAMs.

The examiner responds that patent owner's arguments "seem to
suggest that one of ordinary skill in the art could have easily
identified the necessary modification(s) to the iSBC memory board
that would have been required to add the page mode access
functionality" (EA15).
Patent owner replies that the examiner improperly uses the
appeal brief as evidence to suggest that there would have been a
reasonable expectation of success (RBr10).
Initially, we think that "reasonable expectation of success"
is a concept limited to unpredictable arts, such as chemistry and
biotechnology, and does not apply the electrical or mechanical
arts where whether something will work as designed is almost
never in issue. Thus, we interpret patent owner's arguments as
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Reexamination Control Nos. 90/006,789 and 90/007,420

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going to the question of motivation. The memory board in
Figure 2-1 of "iSBC MEM/3XX" shows that the data lines go to and
from the "Cache Subsystem" and the "DRAM Subsystem." However,
memory accesses are to the "cache" memory and not to the DRAM
array directly. When data is not found in a line of the cache,
it is retrieved from the DRAM array and put in the cache. The
cache array and DRAM array both have 32-bit data fields
(Figure 8-1, p. 8-2), so it is not apparent that any more than
one memory transfer would be performed at a time from the DRAM
array to the cache to make a page mode worthwhile. We tend to
agree with the statement in the Hoffman declaration that "a
person of skill in the art would have also realized that choice
by the memory board manufacturer of using a cache implied that
adding faster DRAM or page mode DRAM would have had little or no
effect on performance" (Br43), which tends to show no motivation.
The complexity of adding a page mode without interfering with the
cache system is a consideration. The interconnections between
the cache memory system and the DRAM memory system makes it
difficult to explain what modifications would have to be made to
a page mode of access. Furthermore, it is not clear, even if the
memory controller was modified to allow it to perform a page mode
of access to the DRAM, that the memory controller would perform a
page mode of access in response to detection of a request from a
requesting agent since memory requests go first to the cache.
These considerations are not addressed in the rejection. While
it may have been obvious to eliminate the cache memory and access
the DRAM memory directly, i.e., to use a less complex system,
this modification is not presented. For these reasons, the
rejection does establish a prima facie case of obviousness. The
rejection of claim 1 is reversed. Apparatus claim 6 contains
common limitations with claim 1 and the rejection of claim 6 is
also reversed. Method claims 12 and 17 have limitations
corresponding to claim 1 and, therefore, the rejection of
claims 12 and 17 is reversed.

NEW GROUND OF REJECTION UNDER 37 CFR § 41.50(b)
The following references are applied in new grounds of
rejection:

Bruce 4,546,451 October 8, 1985

82C08 CHMOS Dynamic RAM Controller, Intel Corp., pages 3-1
through 3-33, June 1985 ("82C08").

Multibus® II Bus Architecture Specification Handbook,
Intel Corp., 1985 ("Multibus II").

Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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Interfacing Dynamic RAM to iAPX 86, 88 Systems Using the
Intel 8202A and 8204, Application Note AP-97A, Intel Corp.,
April 1982, pages 3-110 to 3-145 ("AP-97A").

51C64H High Performance Ripplemodeâ„¢ 64K x 1 CHMOS Dynamic
RAM, Intel Corp., pages 2-1 to 2-20, June 1984 ("51C64H").

iSBC® MEM/312/310/320/340 Memory Boards User's Guide,
Intel Corp., February 1985 ("iSBC MEM/3XX").

Claims 1, 6, 12, and 17 are rejected under 35 U.S.C.
§ 103(a) as unpatentable over "Multibus II," "82C08," "51C64H,"
and Bruce. "iSBC MEM/3xx" are applied as evidence of the level
of ordinary skill in the art.

Obviousness
Factual findings
Scope and content of the prior art
Scope
The "scope" of the prior art relates to whether references
are from analogous art. See In re Deminski, 796 F.2d 436, 442,
230 USPQ 313, 315 (Fed. Cir. 1986) (the reference must either be
in the field of the applicant's endeavor or, if not, then be
reasonably pertinent to the particular problem with which the
inventor was concerned); Stratoflex, Inc. v. Aeroquip Corp.,
713 F.2d 1530, 1535, 218 USPQ 871, 876 (Fed. Cir. 1983) ("The
scope of the prior art has been defined as that 'reasonably
pertinent to the particular problem with which the inventor was
involved'.").
The field of inventor's endeavor is memory controllers for
"page mode" access of DRAMs in a system having "requesting agents
and "replying agents" connected to a "system bus," in particular,
the Multibus II standard. "Multibus II" and "iSBC MEM/3XX" both
relate to memory access in the Multibus II system and are within
the field of endeavor. "82C08" relates to a memory controller
with "page mode" and "51C64H" is a DRAM with page mode, which can
be controlled by "82C08"; thus, both are within the field of
endeavor.
Patent Owner argues in connection with the examiner's
rejection that Bruce is nonanalogous art (and, therefore, not
within the scope of the prior art) (Br48-50). These arguments
are addressed in detail in connection with the rejection of
claims 6 and 17. However, the short answer is that Bruce
discloses apparatus for detecting and crossing a page boundary
in "page mode" memory accesses and is at least reasonably
pertinent to the same problem facing the inventor. The apparatus
is, in fact, identical. Since Bruce also describes memory
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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controllers for page mode DRAMs (e.g., Fig. 3), we also find that
Bruce is within the inventor's field of endeavor.

Content
Multibus II
Architecture
"The Multibus II bus architecture consists of the Parallel
System (iPSB) Bus, the Local Bus Extension (iLBX II Bus), the
Serial System (iSSB) Bus, and two busses carried over from the
Multibus I architecture -- the iSBX I/O Expansion Bus and the
Multichannel DMA (Direct Memory Access) I/O Bus (Figure 1-1)"
(sheet 1-1). The Multibus II specification defines the iPSB,
iLBX, and iSSB bus structures (sheet 1-1). The busses can be
used in different combinations depending on the requirements,
including a basic system with the iPSB alone (Figure 1-2,
sheets 1-9; and Figure 1-2, sheet 2-6), which is relied on here.
The iPSB Parallel System bus has a "burst" transfer mode that
maximizes the bus bandwidth (sheet 1-4): "The burst is
implemented as a single address cycle followed by multiple data
transfers which maximize the bus bandwidth."
"Multibus II" defines the following terms, which will be
helpful in the discussion and rejection (sheets 2-2 to 2-4):

Agent A physical unit which has an interface
to the Parallel Systems bus. For
example, a single-board computer.

Transfer Cycle A bus cycle in which a bus owner
transfers data on the Parallel System
bus. The transfer cycle is subdivided
in two phases, the request phase and
the reply phase.

Request Phase The initial phase of a transfer request
in which the bus owner requests a data
transfer operation. The bus owner
places command and address information
on the Parallel System bus.

Reply Phase The final phase of a transfer cycle.
The phase consists of one or more
consecutive data and/or status
transfers on the Parallel System bus.

Requesting Agent The agent that initiates the
arbitration cycle and transfer cycles.
The requesting agent places a request
Appeal No. 2006-2217
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for a specific operation onto the
Parallel System bus.

Replying Agent The agent or agents with which the
requesting agent performs a transfer
cycle. Replying agents respond to a
requesting agent during the transfer
cycle.

Read Operation The transfer of data from a replying
agent to a requesting agent.

Write OperationThe transfer of data from a requesting
agent to replying agents.

A block diagram of the iPSB Parallel System bus interface is
shown in Figure 1-2 (sheet 2-6). The "requesting agent" and the
"replying agent" are electrically coupled together through the
iPSB Parallel System bus.
Agents perform one of three types of bus cycles on the
Parallel System bus: an "arbitration cycle" is a time period in
which agents arbitrate and decide which one will have exclusive
access to the system bus; the "transfer cycle" is a subsequent
time period in which the agent that has won control of the bus
performs addressing and data transfer cycles to move data to or
from another agent; and an "exception cycle" is an
error-reporting time period that occurs only when an error is
sensed (sheets 2-8 through 2-12).
Only the transfer cycle is relevant here. The transfer
cycle includes a request phase and a reply phase. The transfer
cycle is described as follows (sheet 2-10):

The request phase is controlled by the bus owner. During
the request phase, the requesting agent places address and
control information onto the bus. The address and control
information defines the replying agent(s), the type of
operation, and the type of address space involved in the
transfer cycle.

After the requesting agent transmits the address and control
information, the reply phase of the transfer cycle begins,
in which the replying agent(s) satisfies the request.

During the reply phase, the requesting and replying agents
engage in a close handshake that synchronizes the data
transfer sequence. The requesting and replying agents may
perform one or more data transfers in a reply phase. The
final data transfer is accompanied by an end-of-cycle (EOC)
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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indication. With the EOC, the requesting agent releases
ownership of the bus if other agents request access to the
bus. Otherwise, the agent keeps ownership of the bus.

Signal descriptions
The Parallel System bus contains five groups of signals over
which the requesting and replying agents can enact the protocol
(sheet 2-15). Only the "Address/Data Bus Signal Group" and the
"System Control Signal Group" are relevant here; note that all
groups are discussed in the '645 patent at column 4, line 37 to
column 5, line 22. "Only the requesting agent that is the bus
owner and the selected replying agent(s) use the address/data
signals on the Parallel System bus." (Sheet 2-16.) The
address/data bus signal group includes two sets of signals:
address/data signals and parity signals. We only discuss the
address/data signals. Address/data signals AD31* through AD0*
serve a dual purpose depending on the phase of the transfer
cycle. During the request phase of the transfer, the signals
contain the address for the ensuing transfer cycle, and during
the reply phase of the transfer, the signals contain either 8,
16, 24, or 32 bits of data (sheet 2-17).
The system control signal group consists of a set of ten
signals, SC9* through SC0*, that provide control between agents
during a transfer cycle (sheet 2-17). During the request phase,
the requesting agent drives SC9* through SC0* to provide command
information to the replying agent(s) (sheet 2-18). During the
reply phase of a transfer cycle, the requesting agent drives the
SC9*, SC3*, SC2*, SC1*, and SC0* signals and the replying agent
drives the SC8* through SC4* signals to provide handshake and
status signals (id.). For example, during the request phase,
SC0* indicates a request, SC3* and SC2* identify the width of the
data as 8-, 16-, 24-, or 32-bit transfers, SC4* and SC5* indicate
a memory access, and SC6* indicates whether the operation is a
read or a write (sheet 2-22). During the reply phase, SC2*
indicates an end-of-cycle (EOC) when low and not EOC when high,
SC3* provides a requesting-agent-ready indication on the bus
(part of the reply phase handshake), and SC4* provides a
replying-agent-ready indication on the bus (part of the reply
phase handshake) (sheet 2-23). An agent recognizes the
difference between a one-transfer operation and a sequential
transfer operation by inspecting the handshake signals on SC2*,
SC3*, and SC4* (sheet 2-48).

Bus protocol
The Parallel System bus protocol supports both a
"single-transfer operation" (sheets 2-45 through 2-47) for a
single data transfer, and a "sequential-transfer operation"
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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(sheets 2-48 through 2-49), for multiple data transfers. "The
sequential transfers are terminated by an end-of-cycle indication
from the requesting agent." (Sheet 2-48.)
The tasks of the replying agent during sequential access are
described as follows (sheet 2-58):

4) The replying agent must increment the initial address
given by the requesting agent to obtain the address for
subsequent accesses of data when performing a transfer
cycle that requires sequential accesses of memory.

5) For sequential-access operations, the address
incrementing algorithm varies depending on the data
width that is required by the requesting agent. For an
8-bit transfer, the address is incremented by one at
each access; for a 16-bit transfer, the address is
incremented by two at each access, and so on. Refer to
Figure 3-20.

82C08
"82C08" describes the 82C08 DRAM controller. "The Intel
82C08 Dynamic RAM Controller is a microcomputer peripheral device
which provides the necessary signals to address, refresh, and
directly drive 64K and 256K dynamic RAMs." (page 3-4 under
"General Description"). "The 82C08 supports Sequential Bus
Extension (SBE) systems. By taking advantage of the Intel DRAM
Ripplemode and SBE it performs high rate block data transfer
which increases the bus bandwidth by about three times the
iAPX 186 bandwidth." (Id.) "82C08" states that "[t]he 82C08 has
control circuitry capable of supporting one of several possible
bus structures" (page 3-4 under "Processor Interface").The SBE is
a "superset" of the iAPX 80186/188 (186/188) bus, i.e., it
contains elements in addition to those the 186/188 bus, but
components designed for the 186/188 bus will also operate with
the SBE. The advantages of SBE transfer are (page 3-15, under
"Introduction"):

The SBE transfer allows consecutive words (bytes) of data to
be transferred on consecutive clock cycles. The SBE aims to
increase the bus bandwidth by 2.91 to 3.36 times the 186/188
bus, and to allow block transfer between MULTIBUS II and the
186/188 bus. SBE will support the 51XX CMOS DRAM's [sic,
DRAMs] .... For READ cycles, the SBE will support the
RIPPLEMODE feature of the 51XX family ....

Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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Ripplemode is a page mode type of memory access where the row
address strobe is asserted for the entire block transfer and the
column address strobe is activated alternately.
The 82C08 automatically detects an SBE transfer by sensing
the 186/188 status lines: "status lines active means SBE transfer
is requested" (page 3-15 under "Description and Features"),
whereas "status inactive indicates SBE cycle termination" (id.).
"The SBE signal will be deactivated upon detection of the status
lines inactive, or upon column address overflow." (page 3-15
under "SBE Mode Decoding").
The input address is automatically incremented during SBE
transfer (page 3-15 under "Address Counter and Address Latch"):

The main function of this block is to generate the addresses
for the DRAM's [sic, DRAMs] in SBE mode. The ROW address
(AIH0-8) is internally latched, and upon detection of SBE,
will stay latched for the entire SBE cycle. The COLUMN
address (AIL0-8) will be latched internally by the SBE
signal, into an internal counter which supplies the column
address during SBE cycle.

The timings of the row and column address strobes are
automatically modified during an SBE transfer (page 3-15 under
"RAS/CAS Generator"):

The SBE signal will switch the timings of RAS/CAS generators
to perform the required SBE timings. RÌ„AÌ„SÌ„0,1 will be forced
low for the entire SBE transfer and CÌ„AÌ„SÌ„0,1 will be activated
alternately during the SBE transfer (corresponds to the 51XX
family Ripple Mode).

Read and write cycle timing diagrams (pages 3-31 and 3-32) show
the row address strobe asserted and the column address strobe
asserted and deasserted to read and write.

51C64H
"51C64H" describes a 51C64H 64K x 1 bit CHMOS DRAM with a
Ripplemode mode of operation. The 51C256H is one of the 51XX
family of DRAMs supported by the 82C08 DRAM controller.
Ripplemode is a page mode type of memory access. "Ripplemode
operation permits all 256 columns within a selected row of the
device to be randomly accessed at a high data rate. Maintaining
RÌ„AÌ„SÌ„ low while successive CÌ„AÌ„SÌ„ cycles are performed, retains the
row address internally, eliminating the need to reapply it."
(Page 2-19). "Ripplemode operation provides a sustained data
rate of over 18 MHz for applications that require high data rate
such as bit mapped graphics or high speed signal processing."
(Pages 2-19 to 2-20.)
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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iSBC MEM/3XX
"iSBC MEM/3XX" describes the iSBC MEM/312, /310, /320, and
/340 memory boards (collectively referred to as the iSBC MEM/3XX
boards). The iSBC MEM/3XX board is a high-speed, dual port,
cache-based memory expansion board, which is physically and
electrically compatible with Intel's Multibus II Bus Architecture
Specification (page 1-1). The iSBC MEM/3XX acts as a "replying
agent."
The four versions of the iSBC MEM/3XX board have from 512K
to 4M of DRAM (p. 1-2). Each version of the board has 8 Kbytes
of cache SRAM (static RAM) and 32-bit port interfaces to the
Parallel System bus (iPSB bus) and the Local Bus Extension Bus
(iLBX II bus) (id.). The DRAM subsystem consists of memory
address and write enable logic, row address strobe (RAS) logic,
column address strobe (CAS) logic, and parity detection logic
(pp. 2-3 to 2-4). The controller subsystem generates the control
signals and timing for the iSBC MEM/3XX board, provides the
control logic necessary to perform transfer cycles on the iPSB
and iLBX II buses, and performs on-board functions, such as
refresh and initialization (p. 2-5). The memory uses 2164 DRAMs
(e.g., Fig. 10-2, p. 10-29, identified as "DR 2164").

Bruce
Bruce discloses that DRAMs have the advantages of "low cost,
large number of storage locations or 'bits,' small size, low
power consumption and reasonable read and write access times"
(col. 1, lines 65-68). Bruce discloses that DRAM manufacturers
have provided a "page mode" of access where "[o]nce any memory
location within the page has been accessed at normal access
speeds, any other memory location on the same page can be
accessed at significantly higher speeds than a normal access to
an arbitrary memory location by changing only the column address"
(col. 2, lines 12-17). The problem with using page mode in
raster graphics memory systems is that graphics information is
two dimensional while pages are arranged in only one dimension
(col. 2, lines 17-23). Bruce discloses an addressing technique
to that storage locations on a page form a contiguous "cell"
corresponding to a region of the displayed image, which allows
writing using the high speed page mode of operation (col. 3,
lines 35-44).
Bruce discloses a page boundary crossing technique during a
page mode of operation (col. 3, lines 44-51):

When a page boundary is crossed, one slower memory access is
required to get on the new page, and the invention provides
a technique for detecting the crossing of a page boundary to
allow the initial full memory cycle required to gain access
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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to the new page of memory location into which data can be
written again at high speeds.

The page boundary is detected from a carry bit as the addresses
are incremented, after which a full memory cycle is caused to
occur, providing a new row and column address (col. 4,
lines 3-11; col. 7, lines 28-41; col. 8, lines 50-68; col. 12,
line 63, to col. 13, line 5; Fig. 3 "carry" provides "row cycle
request" for incrementing row; Fig. 9). Bruce also discloses a
page mode memory controller (Figs. 3 and 8, described throughout
the patent), which is responsive to a page crossing detection,
and states that "many different suitable logic circuits for
performing the same functions could be designed by a person
skilled in the art" (col. 11, lines 32-34).

Differences
The differences are described in the analysis.

Level of ordinary skill in the art
The level of ordinary skill in the art is evidenced by the
references. See In re Oelrich, 579 F.2d 86, 91, 198 USPQ 210,
214 (CCPA 1978) ("the PTO usually must evaluate both the scope
and content of the prior art and the level of ordinary skill
solely on the cold words of the literature"); In re GPAC Inc.,
57 F.3d 1573, 1579, 35 USPQ2d 1116, 1121 (Fed. Cir. 1995) (the
Board did not err in adopting the approach that the level of
skill in the art was best determined by the references of
record); Okajima v. Bourdeau, 261 F.3d 1350, 1355,
59 USPQ2d 1795, 1797 (Fed. Cir. 2001) ("[T]he absence of specific
findings on the level of skill in the art does not give rise to
reversible error 'where the prior art itself reflects an
appropriate level and a need for testimony is not shown.'").
Skill in the art is presumed. See In re Sovish, 769 F.2d 738,
743, 226 USPQ 771, 774 (Fed. Cir. 1985).
"82C08," "51C64H," and Bruce indicate that those of ordinary
skill in the art knew the advantages of page mode memory access
and knew how to design page mode DRAMs and page mode DRAM memory
controllers. Persons of ordinary skill had sufficient skill to
implement the requesting and replying agents to carry out the
transfer protocols described in "Multibus II." For example,
"iSBC MEM/3XX" discloses a memory requesting agent board
including dual ports for access to iPSB and iLBX II buses, and a
memory controller for a access to a cache-based memory; the
claims are directed to a simpler replying agent with a single bus
and no cache memory.
The level of skill in the art is also evidenced by the level
of disclosure in the '645 patent. Figure 5 of the '645 patent
shows Multibus II signals going into a block for the memory
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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controller 66 with an internal decoder 70 and a memory access
control (timer 78, counter 80, compare 82, and refresh control
are not relevant to claim 1) with no circuitry showing how the
signals are used to perform the functions. Since the '645 patent
provides no circuit details of memory controller 66, decoder 70,
and memory access control, it must be assumed that the level of
ordinary skill in the computer art was sufficiently high to
enable implementation of a page mode memory controller using
Multibus II control knowing only the Multibus II protocol and the
necessary page mode control signals.

Objective evidence of nonobviousness
No objective evidence of nonobviousness has been presented.

Claims 1 and 12
The following claim chart shows that "Multibus II" and
"82C08" disclose all elements of claim 1.

Claim 1

"Multibus II" and "82C08"

1. Memory control apparatus for
use in a data processing system
having at least a requesting
agent and said [sic] replying
agent electrically coupled
together by a system bus,

"Multibus II" teaches
"requesting agents" and
"replying agents" electrically
coupled by an iPSB Parallel
System bus (e.g., Figure 1-2,
sheet 2-6). "Replying agents"
with memory inherently have to
have a memory controller.

"82C08" is a memory controller.

the requesting agent requesting
access to a memory on the
replying agent for storing and
retrieving data therein over
the system bus, the apparatus
comprising:

"Multibus II" teaches that the
"requesting agent" sends a
request for access to memory
over the system control lines
of the system bus (e.g., SC0*
indicates a request, SC4* and
SC5* indicate a memory access,
and SC6* indicates whether the
operation is a read or a write,
see sheet 2-22) as well as the
address in memory over the
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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address/data lines AD31*
through AD0* of the system bus.
The "replying agent" responds
by sending or receiving data
over the address/data lines of
the system bus. See
description of transfer cycle
at sheets 2-44 through 2-49.

"82C08" receives a request for
access to memory and can
support a bus. See 3-4.

means, associated with a
replying agent, for detecting a
request for initiating an
access to a memory on the
replying agent, the request
detecting means being coupled
to a system bus, and request
being made over the system bus
by a requesting agent;

"Multibus II" teaches that the
"replying agent" detects a
command for initiating access
to memory on the replying
agent. E.g., Sheet 2-10. The
"replying agent" is coupled to
the system bus (Figure 1-2,
sheet 2-6). The request for
access is made over the system
bus by a requesting agent using
the bus system control signals
SC9* through SC0* (sheets 2-17
through 2-22) and the bus
address/data signals AD31*-AD0*
(sheet 2-17).

"82C08" detects a request for
access to memory when status
lines become active. See
Page 3-15.

means, responsive to the
request detecting means
detecting the request, for
asserting a plurality of memory
address control signals for
accessing a plurality of times
the memory on the replying
agent,

The "replying agent" in
"Multibus II" inherently must
have means for asserting memory
address control signals for
sequentially accessing memory a
plurality of times. See
Sheet 2-58.

"82C08" asserts row and column
address strobe signals and
column memory address signals.
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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See Page 3-15.

the control signals comprising
at least a row address strobe
signal associated with a memory
row address and a column
address strobe signal
associated with a memory column
address; and

"82C08" asserts row address
strobes, RÌ„AÌ„SÌ„0 and RÌ„AÌ„SÌ„1, for two
banks, and column address
strobes, CÌ„AÌ„SÌ„0 and CÌ„AÌ„SÌ„1, for two
banks. See Page 3-15.

means for detecting a
completion of the access to the
memory, the completion
detecting means being
responsive to an end of access
control signal generated by the
requesting agent, the access
completion detecting means
being coupled to the memory
address control signal
asserting means for halting the
operation thereof after the end
of access control signal is
detected; and wherein

"Multibus II" teaches that the
"replying agent" detects an
"end-of-cycle (EOC)" signal
from the "requesting agent"
during the reply phase and
thereafter halts access to the
memory. See signal SC2*
(sheet 2-23) and description of
transfer cycle at sheets 2-44
through 2-49.

"82C08" detects completion of
the SBE transfer cycle when the
status lines become inactive.
See Page 3-15.

the memory address control
signal asserting means asserts
the memory address control
signals by asserting the row
address strobe in conjunction
with a row address being
indicative of a page of data
within the memory, and
thereafter asserts and
deasserts a plurality of times
the column address strobe
signal in conjunction with a
plurality of column addresses
for performing a page mode type
of memory access.

"82C08" describes an SBE
transfer, which is the same as
a "page mode" access, by
asserting the row address
strobe during the entire SBE
transfer cycle and asserting
and deasserting the column
address strobe. See
Pages 3-15, 3-16, 3-32, & 3-33.
"82C08" also automatically
increments the column address
internally (page 3-15), as is
required by a "replying agent"
in "Multibus II" (sheet 2-58).

Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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It is noted that claim 1 does not require a DRAM, but only
requires the memory control apparatus to provide control signals
to perform a page mode access.
The differences between the subject matter of claim 1 and
"Multibus II" are that while the "replying agent" taught by
"Multibus II" must inherently have "memory address control signal
asserting means" (i.e., a memory controller) to sequentially
access memory, it does not teach utilizing "control signals
comprising at least a row address strobe signal ... and a column
address strobe signal" and therefore also does not teach that it
"asserts the memory address control signals by asserting the row
address strobe ... and thereafter asserts and deasserts a
plurality of times the column address strobe signal ... for
performing a page mode type of memory access." Not all types of
memories require row and column address strobe control signals.
Row and column address strobe signals and the claimed "page mode"
type of memory access inherently imply a DRAM.
"82C08" describes a DRAM memory controller which detects
when the status lines become active, indicating the beginning of
an SBE transfer mode for initiating an access to memory; provides
page mode memory access control signals (i.e., asserting the row
address strobe and asserting and deasserting the column address
strobe) during the SBE transfer mode; and detects when the status
lines become inactive, indicating an end of access control
signal. Since the '645 patent does not disclose any structure
for performing the functions of the "means-plus-function"
limitations, but only shows a memory controller block 66 and a
memory access control block, any structure is "the corresponding
structure ... described in the specification and equivalents
thereof" under 35 U.S.C. § 112, sixth paragraph. Thus, "82C08"
meets the "means-plus-function" limitations of claim 1. The
differences between the subject matter of claim 1 and "82C08" are
that "82C08" does not teach that the memory controller is
associated with a "replying agent" which is coupled to a system
bus to receive the request from a "requesting agent."
One of ordinary skill in the art would have been motivated
to utilize the "82C08" DRAM memory controller in the memory
"replying agent" in Figure 1-2 (sheet 1-9) of "Multibus II" to
provide for "page mode" memory access for several reasons.
First, "Multibus II" describes a bus protocol, but leaves it to
designers of ordinary skill in the art to design the requesting
agent and replying agent hardware to implement the protocol: one
of ordinary skill in the art seeking to design a memory replying
agent would have been motivated to use any commercial type of
memory, such as the "51C64H" DRAM, and any commercial type of
memory controller, such as the "82C08." **Those of ordinary
skill in the art of computer system architecture had sufficient
knowledge and skill to implement the Multibus II requesting agent
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and the replying agent, as evidenced by "iSBC MEM/3XX."** Thus,
the motivation derives from the need to select a memory and
memory controller to implement the memory replying agent.
Second, one skilled in the art would have been motivated, in
particular, to use the "82C08" and its SBE transfer mode,
corresponding to a "page mode," for the memory controller because
the SBE transfer mode has the known advantage that "it performs
high block data transfer which increases the bus bandwidth by
about three times" ("82C08," page 3-4). The '645 patent uses
page mode DRAMs for the same reason (col. 7, lines 63-66): "it
can be appreciated that the page mode type of memory access,
which is a feature of the invention, advantageously provides for
a high bus bandwidth." The page mode of operation was manifestly
designed to be used to increase the data transfer rate and one
skilled in the art would have been motivated to use a page mode
DRAM and a page mode DRAM memory controller for this advantage.
The motivation is based on using a known device for its known
purpose and advantages.
Third, one of ordinary skill in the art seeking to implement
the "Multibus II" sequential transfer protocol would have been
motivated to use the "82C08" memory controller, in particular,
because the "82C08" has structure that supports features of the
Multibus II standard. "Multibus II" indicates initiation of a
sequential transfer when the SC2* signal is not asserted by the
requesting agent during the first reply phase, and indicates the
"end-of-cycle (EOC)" when SC2* is asserted by the requesting
agent during the final reply phase (sheet 2-48). "82C08" has an
"SBE Mode Decoding" block which detects an SBE transfer mode (a
request to initiate a page mode access) when status lines are
active and detects the termination of page mode when the status
lines are inactive (pages 3-15 to 3-16); thus, "82C08" has
structure "for detecting a request for beginning an access to a
memory" and "for detecting a completion of the access to the
memory ... responsive to an end of access control signal," as
claimed. "Multibus II" discloses that "[t]he replying agent must
increment the initial address given by the requesting agent to
obtain the address for subsequent accesses of data when
performing a transfer cycle that requires sequential accesses of
memory" (sheet 2-58). "82C08" discloses that it latches the
initial address and has an "internal counter which supplies the
column address during SBE cycle" (page 3-15); thus, "82C08" has
structure to automatically increment the column addresses
(although this is not claimed). The added motivation is the
support for the Multibus II standard.
Fourth, both "Multibus II" and "82C08" are Intel Corp.
references and one skilled in the art seeking to implement a
"Multibus II" memory replying agent would have been motivated to
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Reexamination Control Nos. 90/006,789 and 90/007,420

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look to Intel products, such as the "82C08," because they are
more likely to have been designed to work together.
We find that the level of knowledge of those of ordinary
skill in the art was sufficient to enable one skilled in the art
to interface the "82C08" memory controller to the "Multibus II"
system bus and replying agent. The best evidence of this is that
the '645 patent does not provide any circuit details of the
memory controller: it merely shows Multibus II signals going into
a block for the memory controller 66 having an internal
decoder 70 and a memory access control (timer 78, counter 80,
compare 82, and refresh control are not relevant to claim 1) with
no circuitry showing how the signals are used to perform the
functions. Since the '645 patent provides no details of the
memory controller 66, decoder 70, and memory access control, it
must be assumed that one of ordinary skill in the computer art
possessed the required knowledge to implement a page mode memory
controller using Multibus II control signals or patent owner's
own disclosure would be nonenabling. See In re Epstein,
32 F.3d 1559, 1568, 31 USPQ2d 1817, 1823 (Fed. Cir. 1994)
("Rather, the Board's observation that appellant did not provide
the type of detail in his specification that he now argues is
necessary in prior art references supports the Board's finding
that one skilled in the art would have known how to implement the
features of the references and would have concluded that the
reference disclosures would have been enabling."); In re Fox,
471 F.2d 1405, 1407, 176 USPQ 340, 341 (CCPA 1973) (appellant's
specification "assumes anyone desiring to carry out the process
would know of the equipment and techniques to be used, none being
specifically described"); Constant v. Advanced Micro-Devices,
Inc., 848 F.2d 1560, 1569, 7 USPQ2d 1057, 1063 (Fed. Cir. 1988)
("The disclosure in Exhibit 5 is at least of the same level of
technical detail as the disclosure in the '491 patent. If
disclosure of a computer program is essential for an anticipating
reference, then the disclosure in the '491 patent would fail to
satisfy the enablement requirement of 35 U.S.C. § 112, First
¶.").
In addition, however, we find that the level of ordinary
skill in the Multibus II and memory controller arts was very
high, as evidenced by the references, and that those skilled in
the art had the knowledge and experience to interface the "82C08"
with the "Multibus II" replying agent and system bus. Those
skilled in the art of the "Multibus II" bus architecture knew how
to design requesting agents, replying agents, system bus, and
memory to satisfy the electrical, mechanical, and protocol
interface requirements of the Multibus II standard, as evidenced
by "Multibus II" and "iSBC MEM/3XX." "Multibus II" indicates
initiation of a sequential transfer when the SC2* signal is not
asserted by the requesting agent during the reply phase, and
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indicates the EOC when SC2* is asserted by the requesting agent
during the final reply phase (sheet 2-48).
"82C08" detects an SBE multiple transfer with the status lines
are active and detects an end of SBE transfer when the status
lines are inactive. Thus, the only interface that seems to be
required is logic to convert detection of SC2* being inactive
during a first reply phase to active status lines in "82C08," and
to maintain the status lines active until an EOC signal is
received. One skilled in the art had to knowledge to interface
very complicated signals given the interface specifications
between the two devices.

Arguments
The examiner entered a rejection over "Multibus II" and
"82C08" in the Office action of May 5, 2004, in the '6789 Reexam,
which are the same references primarily being relied upon in the
new grounds of rejection. Patent Owner replied with Request for
Reconsideration (pages referred to as "RR__") on June 30, 2004,
after which examiner changed the rejection. We have considered
the Patent Owner's arguments.
Patent Owner argued that the combination of "Multibus II"
and "82C08," even if proper, does not teach "means for detecting
a completion of the access to the memory" (claim 1) and
"detecting a logic state of an end of access bus control signal"
(claim 12) (RR4-6). In response to the rejection that it would
have been obvious to one of ordinary skill in the art to have
utilized the "82C08" memory controller in the memory "replying
agent" in Figure 1-2 (sheet 2-6) of "Multibus II", the same basic
reasoning used in the present new ground of rejection, Patent
Owner argued that "82C08" does not show inputs for the
Multibus II control signals (RR5-6):

However, despite the isolated reference to Multibus II in
the 82C08 (page 3-15), one of ordinary skill in the art
would have appreciated that the interface described in the
82C08 (at pages 3-2 and 3-3) does not detect signals from
the iPSB, including the SC0* and SC2*, described (e.g., at
pages 2-17 to 2-24) in the Multibus II Handbook. Therefore
and as discussed at the personal interview, the combination
of the iPSB bus in the Multibus II Handbook and the 92C08
controller, as suggested by the Office Action, does not
establish a prima facie case of obviousness, as required
under Section 103.

More particularly, the signal lines of the 82C08
interface are WRITE (WÌ„RÌ„), READ (RÌ„DÌ„), and Port Control (PCTL)
[See the 82C08 at page 3-3.] The interface of the 82C08
controller supports: (a) the Multibus; (b) Intel 8086 /
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80186 processors; and (c) Intel 80286 processors. [See the
82C08 at pages 3-3, 3-4, 3-9 and 3-10.] It should be noted
that Multibus (a.k.a. Multibus I), which is referred to
throughout the 82C08, has a different bus architecture from
Multibus II and does not include the iPSB bus referenced by
the Office Action. [See, e.g., Multibus II Handbook at
sheet 1-1.] There is no teaching whatsoever in the 82C08
that the 82C08 detects commands or signals from the iPSB of
the Multibus II. For example, the SC2* signal (cited in the
Office Action as corresponding to the "end of access control
signal recited in the claims) from the system control signal
group SC0*-SC9* of the iPSB is not any one of the input
control signals of the 82C08 controller.

Further, page 3-1 of the 82C08 illustrates the pin-outs
and pages 3-2 to 3-3 describes the signals or connections of
each pin-out. As described therein, none of the pin-outs
detect signals from the iPSB bus, including the SC0* and
SC2*, described (e.g., at pages 2-17 to 2-24) in the
Multibus II Handbook.

It is true that "82C08" does not describe how to connect the
82C08 memory controller directly to an iPSB Parallel System bus
and replying agent, as taught in "Multibus II"; e.g., none of the
input pin descriptions (pages 3-2 to 3-3) describe accepting the
SC2* "end of cycle" signal from a "Multibus II" iPSB system bus.
We do not contend that "82C08" could be directly connected to a
system bus in a "Multibus II" memory replying agent without any
interface circuitry. The rejection is based on obviousness and
therefore must take into account the level of skill of a person
of ordinary skill in the art at the time the invention was made.
We have found that a person of ordinary skill in the art had
sufficient knowledge and design experience to enable him or her
to interface the "82C08" to a "Multibus II" memory replying agent
for two reasons. First, the '645 patent itself provides no
details of the memory controller circuitry to convert Multibus II
control signals into page mode control signals: Fig. 5 merely
shows a block diagram of a memory controller 66. This implies
that design of the whole memory controller was within the level
of ordinary skill in the art or the '645 patent would not be
enabled. By contrast, "82C08" discloses a commercial page mode
memory controller and the only design modifications needed are to
interface the inputs to the signals of a replying agent and
system bus. Second, the level of ordinary skill in the
electronics and computer arts was very high, as demonstrated by
the references, and we find that those persons skilled in the art
knew how to interface electrical signals given the interface
specifications despite the fact that the signal names may be
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different. One of ordinary skill in the art had the knowledge
and experience necessary to design a replying agent to detect a
request for a sequential transfer from the requesting agent (SC2*
not asserted during a first reply phase) and the end of a
sequential transfer (the EOC signal on SC2* during a final reply
phase) and to interface these signals with the status lines in
"82C08."
Patent owner notes that there are several versions of the
82C08 data sheet besides the June 1985 version relied upon, and a
previous November 1984 version of the data sheet, and subsequent
updated versions of the data sheet in February 1986 and
November 1986 do not include any reference to the SBE mode or
Multibus II (RR6-7). It is argued that these other versions of
the data sheet teach away from the SBE mode (RR6-8).
The June 1985 version of the 82C08 data sheet is prior art,
good for all that it teaches. The fact that earlier and later
versions do not contain references to the SBE mode is irrelevant
to the June 1985 version's status as prior art and is not a
teaching away. A reference "teaches away" when it states that
something cannot be done. See In re Gurley, 27 F.3d 551, 553,
31 USPQ2d 1130, 1131 (Fed. Cir. 1994). Absence of mention of an
SBE mode does not imply that the SBE mode will not work.
Patent Owner argues that the combination of "Multibus II"
and "82C08" impermissibly analyzes the invention by parts (RR9):

To reject claims 1 and 12, the Patent Office suggests
using the 82C08 controller in the Memory "replying agent" in
Figure 1-2 of the Multibus II Handbook. The last paragraph
on sheet 2-10 of the Multibus II Handbook relates to a
replying agent and an EOC indication. However, the
Multibus II Handbook does not show (or suggest) how the EOC
(SC2*) signal could be coupled to or detected by a memory
controller, such as the 82C08 controller, in order to halt
access to the DRAM. Further, there is no suggestion in
either the Multibus II or the 82C08 of how to couple the EOC
(SC2*) signal to the 82C08 DRAM controller. Indeed, as
discussed above, the 82C08 controller, which the Office
Action suggests using in the "replying agent," does not
detect the EOC (SC2*) signal on the iPSB bus. [See
generally the 82C08 at pages 3-2 and 3-3.] As such, the
Patent Office compares each part of the claimed features
with principles of bus architecture and memory controller
although there is no teaching of the claimed invention.

Such analysis is improper. As stated in Custom
Accessories Inc. v. Jeffrey-Allan Industries Inc.,
1 U.S.P.Q.[2d] 1196 (Fed. Cir. 1986), casting an invention
as "a combination of old elements" leads improperly to an
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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analysis of the claimed invention by the parts, not by the
whole. That is what seems to have happened here.

Again, the issue is obviousness, not whether "82C08"
discloses how to directly couple an 82C08 memory controller to
the memory replying agent and system bus in "Multibus II." Since
there is motivation for combining "82C08" with "Multibus II," the
analysis is proper.
Patent owner argued that the rejection improperly relies
upon picking and choosing and involves impermissible hindsight
(RR10):

For example, the Patent Office relies upon a general
statement of principle indicated in the 82C08 Advance
Datasheet that "the SBE aims to increase the bus bandwidth"
and an isolated" statement from a datasheet having numerous
other sections "to allow block transfer between the
MULTIBUS II and the 186 / 188 bus." [See the 82C08 at
page 3-15 (INTRODUCTION).] However, since the command
signals, including the SC2*, on the iPSB are not detected by
the 82C08 controller, the SC2* signal (which allegedly
corresponds to the "end of access system bus control
signal") on the iPSB would not, and could not, be used to
cause the 82C08 controller to end access to DRAM.

Since the Patent Office picked and chose parts of
references allegedly corresponding to the elements recited
in claims 1 and 12, while excluding other parts necessary to
the full appreciation of what such references fairly suggest
to one of ordinary skill in the art, the Patent Office has
relied upon impermissible hindsight, especially in light of
the fact that this patent application was filed nearly 16
years ago. It is respectfully submitted that at the time of
filing this patent application, there is no motivation,
other than impermissible hindsight, for one of ordinary
skill in the art to arrive at the claimed invention.

Patent owner apparently argues that the teaching of using an
SBE mode (page mode) to increase bus bandwidth would not have
been motivation for the combination because the SC2* end-of-cycle
(EOC) signal could not be used to end access to DRAM. Yet again,
the issue is obviousness: would one of ordinary skill in the art
had sufficient skill to interface the "Multibus II" signals to
the "82C08" page mode memory controller? Patent owner's
arguments do not address the level of skill in the art. "82C08"
teaches detecting the beginning and end of SBE mode (page mode)
access using the status lines. The SC2* line in "Multibus II"
indicates a non-final transfer when deasserted (inactive) and an
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EOC signal when asserted (active). One of ordinary skill would
have had sufficient skill to interface these two sets of signals.
Patent Owner also argued that the rejection improperly
reduces the invention to a mere "idea" (RR11):

Further, relying on the isolated reference to
Multibus II (page 3-15) and general description of
advantageous features in the 82C02 [sic] (page 3-1) to
support the particular combination of the 82C02 [sic] with
the iPSB, despite no teaching of a detection of the signal
(SC2*) that allegedly corresponds to the end of access
signal, improperly reduces the claimed invention to an [sic]
mere "idea" of an end of access signal and a page mode, and
thus, does not consider the claimed invention as a whole.
Reducing a claimed invention to an "idea," and then
determining patentability of that "idea" is an error. Jones
v. Hardy, 727 F.2d 1524, 1528, 220 USPQ 1021, 1024 (Fed.
Cir. 1984); W.L. Gore & Associates, Inc. v. Garlock, Inc.,
727 F.2d 1524, 1528 [sic, 721 F.2d 1540, 1547-48],
220 USPQ 303, 308-09 (Fed. Cir. 1983).

The rejection is not based on finding the page mode and an
end of access signal to be the "gist" or "thrust" of the
invention. "Multibus II" discloses the protocol for a memory
replying agent, which detects non-final and final (end-of-cycle)
memory accesses with the SC2* signal, but does not disclose how
the memory and memory controller is implemented. One of ordinary
skill in the art seeking to implement a memory and memory
controller for a memory replying agent in "Multibus II" would
have been motivated to select a commercial memory and memory
controller with a page mode of access, such as "51C64H" and
"82C08," for the known speed advantages of page mode. "82C08"
detects the start and end of page mode access.

Claims 6 and 17
Claim 6 contains all of the limitations of claim 1, plus the
following limitations:

means for detecting a memory page boundary having
inputs coupled to the memory column address and an output
expressive of a state of the memory column address that is
indicative of a memory page boundary; and

means, responsive to the output of the memory page
boundary detecting means, for deasserting the row address
strobe signal, providing a memory row address expressive of
another page of data, and reasserting the row address strobe
signal.
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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"82C08" discloses that during the SBE transfer mode
(corresponding to the claimed "page mode"), the column address is
incremented by an internal address counter (page 3-15 and
"Address Latch and Address Counter" on page 3-16). "An overflow
of the COLUMN address counter will generate an overflow signal
which will disable SRDY and SBE signals (it will actually
terminate the SBE transfer)." (Page 3-15.) The overflow signal
indicates a page address boundary (i.e., the end of a row).
Thus, "82C08" teaches structure "for detecting a memory page
boundary." However, "82C08" teaches that the SBE transfer mode
(page mode) is terminated upon reaching page boundary.
Bruce discloses a page boundary crossing technique during a
page mode of operation. The page boundary is detected from a
carry bit as the addresses are incremented, after which a full
memory cycle is caused to occur, providing a new row and column
address (e.g., col. 4, lines 3-11; col. 8, lines 50-68). Bruce
discloses how the page boundary hardware in interfaced to a page
mode memory controller and actually discloses a page mode memory
controller (Figs. 3 and 8). This hardware is the same or
equivalent to the structure corresponding to the "means for
detecting" and "means for deasserting and reasserting" in the
'645 patent. One of ordinary skill in the art would have been
motivated to modify "82C08" to provide structure deasserting the
row address strobe signal, changing the memory row address, and
reasserting the row address strobe signal in order to achieve the
advantage of crossing a page boundary as taught in Bruce.
Patent Owner argues that Bruce teaches one to reorganize
data so that a row or page of the DRAM stores the data
corresponding to a two-dimensional cell of a display, instead of
the customary single row of pixels, which requires extensive and
complex additional circuitry (Br48). It is argued (id.):

Bruce teaches expressly that its invention becomes useful
only after this non-trivial reorganization. See id. at
col. 8:6-10 Thus, Bruce teaches away from using its page
boundary detection technique in a non-graphics display DRAM
system . . . (i.e., in systems where a page is not mapped to
a system using a two-dimensional region on a display
screen).

Bruce's teaching of page boundary detection and page
boundary crossing during a page mode memory operation is
described as general solution for page mode operation. Nowhere
does Bruce state or imply that the page crossing technique only
is useful when used with the particular memory organization.
Patent Owner argues that Bruce is not analogous art that can
properly be combined because it relates to graphics constraints
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and performance constraints that differ radically from the
general purpose systems described in "286/100" and
"2164A" (Br48-50). It is argued (Br49):

Bruce discusses a method for page boundary detection
that is specific to a graphics system for raster display
refresh. Bruce at col. 1:7-10. In fact, Bruce explicitly
teaches away from considering page mode memory access in
graphics/raster display applications generally, explaining:

[P]age mode has not heretofore been considered useful
in raster display refresh memory systems because of the
low probability that memory locations which need to be
accessed sequentially by the graphics computation
device will fall on the same "page" since the "page"
extends only in one dimension of the display memory.

Id. at col. 2:17-24.

A reference is analogous prior art if it is in the field of
the inventor's endeavor or reasonably pertinent to the particular
problem with which the inventor was concerned. See
Deminski, 796 F.2d at 442, 230 USPQ at 315. The scope of the
prior art is a finding of fact. The field of inventor's endeavor
is memory controllers for "page mode" access of DRAMs in a system
having "requesting agents and "replying agents" connected to a
"system bus," in particular, a Multibus II system. Bruce
describes memory controllers for page mode DRAMs (e.g., Fig. 3)
and is within the inventor's field of endeavor. The particular
problem the inventor was concerned with in claims 6 and 17 was
crossing a page (row) boundary during a page mode of operation.
Bruce discloses apparatus for detecting and crossing a page
boundary in "page mode" memory accesses as part of its overall
invention and thus addresses the same problem facing the
inventor. Bruce teaches the same solution recited in claims 6
and 17. Bruce is within the scope of the prior art.
Bruce does not state that the method for page boundary
detection and crossing is limited to the disclosed graphics
system. The page boundary detection and crossing technique
described as a general technique (see col. 3, lines 29-51) and
can be applied to any page mode memory system. Bruce's statement
that page mode has not been considered to be useful in raster
display memory systems does not constitute a teaching away from
the use of the page mode, in general. Bruce teaches that the
page mode has the advantage of allowing memory locations on the
same page to be accessed at a significantly higher speed than a
normal access to an arbitrary memory location (col. 2, lines
12-17), which is motivation for using a page mode. Bruce also
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contains general page mode memory controller teachings (e.g.,
Fig. 3). One of ordinary skill in the art seeking to implement a
page mode of memory access would have been led to consider the
page mode teachings of Bruce.
Patent Owner argues (Br49):

Bruce teaches clearly that the utility of its specific page
boundary detection methods depends on the unique
characteristics of graphics display systems. See Bruce at
col. 1:47-60. Therefore, the Bruce patent - according to
its own disclosure - does not address the needs of
non-graphics display systems for the detection of page
boundaries.

We disagree. The cited portion of Bruce does not state that
the method for page boundary detection and crossing is limited to
the disclosed graphics system. One of ordinary skill in the art
would have found Bruce highly relevant to the inventor's problem
of page boundary detection and crossing and, therefore, within
the scope of the prior art.

Claims 2-5, 7-11, 13-16, and 18-20
The examiner has determined amended claims 2 and 13 to be
patentable and confirmed the patentability of claims 3-5, 7-11,
14-16, and 18-20 over the additional reference to Churchward,
U.S. Patent 4,691,303. For completeness, and because we find
patent owner's arguments unpersuasive, we explain why independent
claims 2 and 13, and, hence, their dependent claims, are not
taught by Churchward, relied upon by the reexamination requester.
Patent owner's arguments that one skilled in the art would not
have been motivated to modify the refresh technique of "2164A"
because it teaches its own refresh schemes and the technique of
Churchward is incompatible therewith (Br44-46), are not
persuasive. One of ordinary skill in the art would have been
motivated to substitute a known refresh technique for its
disclosed advantages.
Claim 2 contains all of the limitations of claim 1, plus the
following limitations:

means for generating a memory refresh request signal at
predetermined intervals.

means for counting each of the refresh request signals;

means, coupled to the refresh request signal counting
means, for comparing a value of the counted refresh request
signals to a predetermined threshold value and for
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Reexamination Control Nos. 90/006,789 and 90/007,420

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determining when a number of counted refresh request signals
equals or exceeds the predetermined threshold value; and

means, responsive to the comparing means determining
that a number of counted refresh request signals at least
equals the predetermined threshold value, for refreshing a
plurality of memory rows, the number of memory rows being
refreshed being substantially equal to the counted value.

It is helpful to understand prior art refresh techniques,
which are described in "AP-97A" at page 3-116. Typically, each
row of a DRAM must be refreshed every 2 milliseconds (ms) or the
data in it will be lost. In a "distributed refresh" method for a
DRAM with 128 rows and 128 columns, a single refresh cycle is
performed every 2 ms/128 = 15.6 microseconds. "AP-97A" also
describes a "burst refresh" method:

Burst refresh means waiting almost 2 ms from the last time
refresh was performed, then refreshing the entire memory
with a "burst" of 128 refresh cycles. This method has the
inherent disadvantage that during the time refresh is being
performed (more than 40 microseconds for 128 rows) no read
or write cycles can be performed. This severely limits the
worst case response time to interrupts and makes this
approach unsuitable for many systems.

The refresh technique of the '645 patent is "burst refresh"
of less than all of the rows. The '645 patent explains that a
timer generates a refresh request at predetermined intervals.
The refresh requests are counted by a refresh request counter and
a comparator determines when the count equals or exceeds a
predetermined threshold value, such as 24, at which time it will
attempt to burst refresh all of the pending 24 requests. This is
recited in claims 2 and 13. The prior art "burst refresh" does
not need to count memory refresh request signals because all rows
are refreshed. If a bus transfer is in progress, the memory
controller will attempt to wait until the bus transfer is
completed. But, if some maximum number of requests are pending,
such as 41, the bus transfer is interrupted and a burst refresh
of the number of requests in the count is performed. This
"blocked refresh" technique is in claims 4 and 15. See Col. 8,
lines 35-61. The technique has the advantage of not tying up the
memory as long as the prior art "burst refresh" of all rows.
Churchward discloses that a nominal read-write access memory
cycle is on the order of 450 nanoseconds, but certain memory
cycles may require up to 10 microseconds which is a large
fraction of the normal refresh time of 15.6 microseconds (col. 3,
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lines 24-30). The invention is summarized in Churchward as
follows (col. 3, lines 31-48):

In order to allow for such relatively long memory
access cycle times, and to prevent the refresh cycle
requirements from unduly interfering with the access to the
memory for normal reading and writing, a stockpile counter
is employed which "stores" up to eight refresh cycle counts.
During times that the memory is "busy", (i.e. while a
requestor device is requesting memory access for either
reading or writing), the counter counts down toward zero.
Thus, if a refresh request occurred immediately prior to the
time that the memory became busy, the next refresh requests
at 15.6 microseconds apart are ignored, for as long as the
memory remains busy up to a total of eight. However, upon
the occurrence of the ninth refresh request, refreshing
becomes mandatory and continues every 15.6 microseconds as
long as the memory remains busy. If the memory becomes not
busy before a zero count is reached, it counts back towards
a count of eight at a 450 nanosecond rate.

With this timing cycle, there will be a delay period of
up to 125 microseconds, during which time if the memory
remains busy the refresh requests will be initiated, but
ignored, until such time that the counter that stores the
refresh bank has counted down to zero, at which count
refreshing becomes mandatory.

The refresh scheme is illustrated in Fig. 2. Normally, rows
are refreshed every 15.6 microseconds shown by the equally spaced
hash marks. A refresh takes about 450 nanoseconds to read and
write a row. When the memory becomes busy, the refresh cycle is
locked out for up to eight cycles (8 cycles x
15.6 microseconds/cycle = 124.8 microseconds) indicated by the
"count." When the count equals zero, refreshing becomes
mandatory at the 15.6 microsecond rate; note that, although not
shown, memory access is suspended during the refresh time. When
the memory becomes not busy, a number of rows equal to the stored
count are refreshed at the 450 nanosecond rate.
Churchward has a refresh counter 62 which recycles every
15.6 microseconds in response to clock 51 (Fig. 1b; col. 6,
lines 13-15), which corresponds to the "means for generating a
memory refresh request signal at predetermined intervals."
Churchward has a stockpile up/down counter 96 (Fig. 1c), but
it only counts refresh requests signals when the memory is busy.
The structure corresponding to the "means for counting,"
counter 80 if Fig. 5, counts every refresh request signal, so a
circuit which only counts when the memory is busy is not
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equivalent to the "means counting each of the refresh request
signals." This is one difference.
Churchward has structure to determine when the count in
counter 96 reaches zero from eight, where zero represents a
"predetermined threshold value" of eight counts. Thus, in
isolation, Churchward seems to have "means, coupled to the
refresh request signal counting means, for comparing a value of
the counted refresh request signals to a predetermined threshold
value and for determining when a number of counted refresh
request signals equals or exceeds the predetermined threshold
value." However, since the value of the counted signals is not
the count of each of the refresh request signals, but only the
count of the refresh request signals when the memory is busy,
this limitation is not met when the claim is considered as a
whole. This is another difference.
The last limitation of claim 2 recites:

means, responsive to the comparing means determining
that a number of counted refresh request signals at least
equals the predetermined threshold value, for refreshing a
plurality of memory rows, the number of memory rows being
refreshed being substantially equal to the counted value.

Churchward does not refresh a plurality of memory rows "equal to
the counted value" "responsive to the comparing means determining
that a number of counted refresh request signals at least equals
the predetermined threshold value." Churchward burst refreshes a
number of rows equal to the count responsive to the memory
becoming not busy. When the counter reaches zero (representing a
count of eight), the only value that could be considered a
"predetermined" threshold value, Churchward starts refreshing
rows one at a time at a 15.6 microsecond rate if the memory is
still busy: it does not refresh eight rows. The number of memory
rows refreshed depends on the memory busy time, not the count.
"If the memory becomes not busy before a zero count is reached,
it counts back towards eight at a 450 nanosecond rate." (Col. 3,
lines 46-48.) Thus, if the memory was only busy for 3 counts,
the system would perform a burst refresh of 3 rows (each refresh
taking 450 nanoseconds) when the memory became not busy; i.e.,
the system performs a burst refresh of "up to" eight refresh
cycles (e.g., col. 8, lines 44-51). The burst refresh is not
dependent on the count being a predetermined value. This is a
further difference.
For these reasons, we find that Churchward does not teach
the added limitations of claims 2-5, 7-11, 13-16, and 18-20.
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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CONCLUSION
The rejections of claims 1, 6, 12, and 17 are reversed.
New grounds of rejection of claims 1, 6, 12, and 17 are
entered under 35 U.S.C. § 103(a) pursuant to 37 CFR § 41.50(b).
This decision contains new grounds of rejection pursuant to
37 CFR § 41.50(b) (2005). 37 CFR § 41.50(b) provides that "[a]
new ground of rejection pursuant to this paragraph shall not be
considered final for judicial review."
Regarding any affirmed rejection, 37 CFR § 41.52(a)(1)
provides:
(a)(1) Appellant may file a single request for
rehearing within two months of the date of the original
decision of the Board. . . .

37 CFR § 41.50(b) also provides that the appellant, WITHIN
TWO MONTHS FROM THE DATE OF THE DECISION, must exercise one of
the following two options with respect to the new ground of
rejection to avoid termination of the appeal as to the rejected
claims:
(1) Reopen prosecution. Submit an appropriate
amendment of the claims so rejected or new evidence relating
to the claims so rejected, or both, and have the matter
reconsidered by the examiner, in which event the proceeding
will be remanded to the examiner. . . .

(2) Request rehearing. Request that the proceeding be
reheard under § 41.52 by the Board upon the same
record. . . .

No time period for taking any subsequent action in
connection with this appeal may be extended under 37 CFR
§ 1.136(a)(1)(iv) (2004).
REVERSED - 37 CFR § 41.40(b)

LEE E. BARRETT )
Administrative Patent Judge )
)
)
)
) BOARD OF PATENT
JAMESON LEE ) APPEALS
Administrative Patent Judge ) AND
) INTERFERENCES
)
)
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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)
SALLY C. MEDLEY )
Administrative Patent Judge )
SIDLEY AUSTIN LLP For Patent Owner
ATTN: DC PATENT DOCKETING
1501 K STREET, N.W.
WASHINGTON DC 20005

JAMES S. HSUE For Third Party Requester
PARSONS HSUE & DE RUNTZ LLP
665 MONTGOMERY STREET
SUITE 1800
SAN FRANCISCO, CA 94111

We also accept and incorporate by reference Patent Owner's
identification of the disclosure in the specification
corresponding to the claimed "means-plus-function" limitations.
It is noted, however, that the only "structure" disclosed in the
specification consists of functional blocks, such as the memory
controller 66, and decoder 70 and memory access control
(unnumbered) within the memory controller in Fig. 5. Since the
'645 patent does not disclose any structure for performing the
functions of the "means-plus-function" limitations, but only
shows a memory controller block 66 and a memory access control
block, any structure is "the corresponding structure ...
described in the specification and equivalents thereof" under
35 U.S.C. § 112, sixth paragraph.

-->> any case law on this??

* circuitry to accomplish such page mode type of memory access
cannot be simply "plugged in" to the memory board reference.
A person of ordinary skill in the art attempting such a
redesign would face substantial complexities stemming from,
and incompatibilities between the new circuitry and the
existing memory board.

* One such source of incompatibility is within the cache
memory subsystem on the iSBC MEM/3xx memory board. . . . If
the 2164 DRAMs are accessed in page mode, however, the
memory board must ensure that the cache access method is
compatible with this faster page mode access. Otherwise,
Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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the cache subsystem may function improperly due to differing
access speeds.

* It is also argued that the Hoffman declaration states (Br42):

* One of ordinary skill in the art around the 1987 time frame
would have realized that one advantage to using such a cache
would be that a large amount of relatively slow and inexpensive
DRAM could be used on the memory board without impacting
performance. Such a person of skill in the art would have also
realized that choice by the memory board manufacturer of using a
cache implied that adding faster DRAM or page mode DRAM would
have had little or no effect on performance and would likely have
required the use of more expensive

**d the rejection does not recognize or address these
difficulties.

-->> is this really challenged?? -->> what is argued?

A person of ordinary skill in the art would have been enabled to
design a memory controller to perform page mode operation. The
'645 patent acknowledges that page mode DRAMs were well known
(col. 6, lines 3-19) and, since the '645 patent provides no
details of the memory controller circuitry, enablement of a page
mode memory controller must be presumed to be within the level
of skill in the art or the '645 patent would not be enabled.

First, "Multibus II" does not describe how a memory and memory
controller for the replying agent are constructed; therefore, one
of ordinary skill seeking to design a memory replying agent would
have motivated to use any commercial type of memory, such as the
"51C64H" DRAM, and any commercial type of memory controller, such
as the "82C08." The motivation derives from the simple fact that
some kind of memory is required. "Multibus II" describes a bus
protocol for conducting memory transfer operations, but leaves it
to designers of ordinary skill in the art to design the
requesting agent and replying agent hardware to implement the
protocol. Those of ordinary skill in the art of computer system
architecture had sufficient knowledge and skill to implement the
Multibus II requesting agent and the replying agent, as evidenced
by "iSBC MEM/3XX."

Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

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The motivation springs from the fact that some kind of memory and
memory controller must be used...

** One of ordinary skill in the art seeking to design a memory
replying agent would have been motivated to use DRAM for its
known advantages (higher packaging density, lower cost per bit,
and lower power), as taught by "AP-97A" (page 3-111), and because
"iSBC MEM/3XX" expressly discloses DRAM memory in a Multibus II
memory replying agent. "51C64H" was a known DRAM chip and
"82C08" was a known DRAM memory controller for this chip.

Although it is evidently presumed by the inventor of the '645
patent that one of ordinary skill in the art had sufficient
knowledge to enable him or her to build a page mode memory
controller, because no memory controller circuitry is described,
"82C08" nevertheless teaches a memory controller for page mode
DRAMs.

In particular, "Multibus II" presumes that one of ordinary skill
in the art had the knowledge necessary to design a replying agent
to detect a request for sequential transfer from the requesting
agent during the request and reply phases, and to detect the end
of a sequential transfer (the EOC signal on SC2*) from the
requesting agent during a reply phase in order to conduct the
Multibus II protocol.

* "82C08" teaches that "[t]he 82C08 has control circuitry
capable of supporting one of several possible bus structures"
(page 3-4)

AP-97A
"AP-97A" discloses that DRAMs have many advantages: four
times the density (number of bits per device) of static RAMs,
which allows four times as many bytes to be put on a board; the
cost per bit is roughly one-fourth that of static RAMs; they use
about one-sixth the power of static RAMs, so power supplies may
be smaller and less expensive (page 3-111: note that "Third,
static RAMs ..." should be "Third, dynamic RAMs ...).

***??
* In a sequential-transfer operation the requesting agent
provides the address on address/data lines AD31* to AD0* and
commands for a transfer, a number of data transfers take place
between the replying agent and the requesting agent **** and "

Appeal No. 2006-2217
Reexamination Control Nos. 90/006,789 and 90/007,420

- 42 -

** Claims 6 and 17 are rejected under 35 U.S.C. § 103(a) as
unpatentable over "Multibus II," "82C08," "51C64H," "AP-97A," and
"iSBC MEM/3xx," further in view of Bruce.

* Whether there is motivation to combine the references is a
question of fact drawing on the factors of Graham v. John Deere
Co., 383 U.S. 1, 17-18, 148 USPQ 459, 467 (1966). See McGinley
v. Franklin Sports, Inc., 262 F.3d 1339, 1351-52, 60 USPQ2d 1001,
1008 (Fed. Cir. 2001). Motivation ***