Ex Parte 4624737 et al

Patent Trial and Appeal Board

Nov 5, 2013

90009508 (P.T.A.B. Nov. 5, 2013)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
90/009,508 07/27/2009 4624737 051700-5013-US 1451
9629 7590 11/05/2013
MORGAN LEWIS & BOCKIUS LLP (WA)
1111 PENNSYLVANIA AVENUE NW
WASHINGTON, DC 20004
EXAMINER
NGUYEN, TUAN H
ART UNIT PAPER NUMBER
3992
MAIL DATE DELIVERY MODE
11/05/2013 PAPER
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________
BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________
Ex parte LG DISPLAY COMPANY, LTD.
Appellant
____________
Appeal 2013-009636
Reexamination Control No. 90/009,508
U.S. Patent No. 4,624,737
Technology Center 3900
____________

Before DAVID M. KOHUT, ERIC B. CHEN, and
STANLEY M. WEINBERG, Administrative Patent Judges.

CHEN, Administrative Patent Judge.

DECISION ON APPEAL
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Reexamination Control No. 90/009,508
U.S. Patent No. 4,624,737

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This is an appeal under 35 U.S.C. §§ 134(b) and 306 from the final
rejection of claim 1. We have jurisdiction under §§ 134(b) and 306. We
affirm.

STATEMENT OF THE CASE
Reexamination Proceedings
A request for ex parte reexamination of U.S. Patent No. 4,624,737
(the ’737 patent) was filed on July 1, 2009 and assigned Reexamination
Control No. 90/009,636. Requester did not seek reexamination of dependent
claims 2-4 and they are therefore, not subject to reexamination. (Req. 1;
Ans. 2.)
The ’737 patent, entitled “Process for Producing Thin-Film
Transistor,” was issued on November 25, 1986, to Masafumi Shimbo, based
on Application No. 06/743,092, filed June 10, 1985. The ’737 patent is now
expired.
The ’737 patent is said to be assigned to LG Display Company, Ltd.
(formerly, LG Philips LCD Company, Ltd.), said to be the assignee and real
party in interest. (Br. 2.)1

Appellant’s Invention
Appellant’s invention relates to a thin-film transistor that includes a
gate insulating film, a high-resistivity semiconductor film, a low-resistivity

1 See also Assignment Abstract of Title, Reel 021147 Frame 0009 recorded
June 19, 2008 and entered into the record of this proceeding as “Title
Report” on July 17, 2009.
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semiconductor film, and a conducting film that are successively deposited in
lamination without exposure to an oxidizing atmosphere. The source and
drain electrodes are then selectively formed. (Abstract; see also col. 1, ll. 6-
7.)

Related Litigation
Requester has informed us that the ’737 patent has been the subject of
at least the following litigation matters: LG Philips LCD Co. v. NEC Corp.,
No. 99-cv-726 (D. Del. 1999), LG Philips LCD Co. v. Tatung Co. of
America, No. 02-cv-6775 (C.D. Cal. 2002), LG Philips LCD Co. v. Jean
Co., No. 03-cv-2866 (C.D. Cal. 2003), LG Philips LCD Co. v. Lite-On
Technology Corp., No. 03-cv-2884 (C.D. Cal. 2003), LG Philips LCD Co. v.
TPV Technology, Ltd., No. 03-cv-2885 (C.D. Cal. 2003), LG Philips LCD
Co. v. Viewsonic Corp., No. 03-cv-2886 (C.D. Cal. 2003), LG Philips LCD
Co. v. Chi Mei Optoelectronics Corp., No. 06-cv-726 (D. Del. 2006), AU
Optronics Corp. v. LG Philips LCD Co., No. 07-cv-357 (D. Del. 2007), and
Chi Mei Optoelectronics Corp. v. LG Philips LCD Co., No. 08-cv-355 (D.
Del. 2008). (Req. 2.)
Appellant has also informed us that as of January 11, 2012, the filing
date of the Appeal Brief in this reexamination proceeding, three of the
above-entitled matters had been consolidated by the Delaware District
Court: Nos. 06-cv-726, 07-cv-357, and 08-cv-355. (Br. 2.)

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The Claim
Independent claim 1 is exemplary and reproduced with minor
formatting and disputed limitations in italics:
1. A process for producing a thin-film transistor
comprising[:]
a first step for forming a gate electrode on an insulating
substrate,
a second step for continuously depositing on said gate electrode
and substrate a gate insulating film, a high-resistivity semiconductor
film and a conducting film containing at least a low-resistivity
semiconductor film without exposing them to an oxidizing
atmosphere,
a third step in which said high-resistivity semiconductor film
and said conducting film are selectively etched so that they are partly
left as an island region on said gate electrode,
a fourth step for selectively forming a source electrode and a
drain electrode both contacting a part of the surface of said island
region and spaced apart from each other,
a fifth step for selectively removing said conducting film
exposed on said island region with said source and drain electrodes
serving as at least a part of the mask,
a sixth step for depositing a surface passivation film, and
a seventh step for selectively removing said surface passivation
film and exposing a part of each of said source electrode, drain
electrode and gate electrode.

The Rejections
Claim 1 stands rejected under 35 U.S.C. § 102(b) as being anticipated
by Kawasaki (Japanese Patent Office Application No. S59-68975; April 19,
1984).
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Claim 1 stands rejected under 35 U.S.C. § 103(a) as obvious over
Kawasaki and Okubo (U.S. Patent No. 4,470,667; Sept. 11, 1984).
Appellant relied upon the following2 in rebuttal to the Examiner’s
rejection:
Declaration under 37 C.F.R. § 1.132 of Gary W. Rubloff,
Ph.D., dated June 16, 2010 (“Rubloff Declaration”).

ANALYSIS
§ 102 Rejection
We are unpersuaded by Appellant’s arguments (Br. 10-13) that
Kawasaki does not describe the limitation “a seventh step for selectively
removing said surface passivation film and exposing a part of each of said
source electrode, drain electrode and gate electrode,” as recited in
independent claim 1.
The Examiner found that the first metallic layer of Kawasaki
corresponds to the limitation “a gate electrode.” (Ans. 4, 7; Kawasaki,
fig. 2a.) The Examiner further found that forming opening areas in the
passivation film of Kawasaki corresponds to the limitation “a seventh step
for selectively removing said surface passivation film and exposing a part of
each of said source electrode, drain electrode and gate electrode.” (Ans. 5-6,
Kawasaki, p. 6.) In particular, the Examiner found that Kawasaki “discloses
the step of forming an ‘insulating layer as a passivation film, . . . Thereafter

2 This opinion only addresses arguments made by Appellant. Arguments
not made are considered waived. See 37 C.F.R. § 41.37(c)(1)(vii). We have
considered the declaration evidence to the extent raised by Appellant’s
arguments.

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opening areas are formed on the insulating layer and the aforementioned
wiring paths are exposed . . . and established as bonding pad areas’” and that
“[t]he ‘aforementioned wiring paths’ as referred to would clearly include
source, drain and gate wiring paths formed previously.” (Ans. 7.) We agree
with the Examiner.
Kawasaki3 relates to “a semiconductor device of non-single crystalline
silicon” (p. 3, “Industrial application field”), for example, a metal insulator
semiconductor (MIS) transistor switching array forming an image display
(p. 3, “Constitution of prior art and problems thereof,” para. 1). Figures 2a-
2d of Kawasaki illustrate a cross-section view of a process for
manufacturing an amorphous silicon MIS-type transistor including forming
a first metallic layer 2 (i.e., the claimed “a gate electrode”) on an insulative
substrate 1. (Id., para. 2.) Kawasaki explains that the “amorphous silicon
layer 4’ without impurity was partially removed accompanying the selective
removal of the amorphous silicon layer 5’ with impurity” (i.e., the claimed
“high-resistivity semiconductor film” and “conducting film,” respectively)
and that “an adequate passivation film must be formed, and the amorphous
silicon layer 12 forming the channel must be protected from the external
air.” (Id., p. 4, para. 4.) Kawasaki further explains that “the insulating layer
is formed as a passivation film or an interlayer insulating film” (i.e., the
claimed “surface passivation film”) and that “[t]hereafter opening areas are
formed on the insulating layer, and the aforementioned wiring paths are

3 Reference is made to the English-language translation supplied by the
third-party requester, filed July 1, 2009 and cited by Appellant (see, e.g.,
Br. 11).
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exposed and established as bonding pad areas.” (P. 6, “Description of the
preferred embodiments,” para. 4.) Thus, because Kawasaki explains that
opening areas are formed in the passivation film to expose wiring paths,
Kawasaki teaches the limitation “a seventh step for selectively removing
said surface passivation film and exposing a part of each of said source
electrode, drain electrode and gate electrode.”
Appellant argues that “the gate wiring 9 [in] Kawasaki is formed after
and on the gate insulating layer 3” and that “the gate wiring 9 in Kawasaki[]
cannot be the claimed ‘gate electrode’ because gate wiring 9 is formed after
and on the gate insulating layer 3.” (Br. 11.) Contrary to Appellant’s
arguments, the Examiner found that the first metallic layer 2 of Kawasaki,
rather than the gate wiring 9 of Kawasaki, corresponds to the limitation “a
gate electrode.” (Ans. 4, 7.) Accordingly, Appellant’s argument does not
directly address the process step of Kawasaki (i.e., forming the first metallic
layer 2) cited by the Examiner.
Therefore, we agree with the Examiner that Kawasaki describes the
limitation “a seventh step for selectively removing said surface passivation
film and exposing a part of each of said source electrode, drain electrode and
gate electrode.”
We are further unpersuaded by Appellant’s arguments (Br. 13-17) that
Kawasaki does not describe the limitation “continuously depositing . . . a
gate insulating film, a high-resistivity semiconductor film and a conducting
film . . . without exposing them to an oxidizing atmosphere,” as recited in
independent claim 1.
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The Examiner found that the deposition method of Kawasaki for
depositing the gate insulating layer, the amorphous silicon layer, and the
amorphous silicon with impurities corresponds to the limitation
“continuously depositing . . . a gate insulating film, a high-resistivity
semiconductor film and a conducting film . . . without exposing them to an
oxidizing atmosphere.” (Ans. 4.) In particular, the Examiner found that:
[I]n Kawasaki [the] process of continuously depositing films by
a single deposition step with gases switching from ammonia to
without impurities to with impurities added into silane gas to
form various layers of silicon nitride layer 3, high and low
resistivity semiconductor layers 4, and 5 respectively in the
same chamber and the result as noted above clearly demonstrate
that the thin films are formed without exposing to oxidizing
atmosphere.
(Ans. 9; Kawasaki, p. 3.) We agree with the Examiner.
The Abstract of the ’737 patent discloses that “[a] gate insulating film,
a high-resistivity semiconductor film, a low-resistivity semiconductor film
and if necessary a conducting film are successively deposited in lamination
without exposing them to any oxidizing atmosphere including atmospheric
air.” (Abstract (emphasis added).) The “Background of the Invention”
section of the ’737 patent, in reference to a conventional process in which an
amorphous silicon film 4 is deposited, discloses that “[a]lthough such natural
oxide can be removed by an aqueous solution of hydrofluoric acid (HF) or a
similar substance, the possibility is still great that oxygen and its compounds
as well as other impurities can collect on the laminate surface as it is
exposed to the atmosphere.” (Col. 1, ll. 35-40 (emphasis added).)
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Furthermore, the “Detailed Description of Preferred Embodiments” section
of the ’737 patent describes that:
[S]uccessive deposition can be accomplished, for instance, by
forming a silicon nitride (SiNx) film as gate insulating film 3
from a mixed gas of SiH4 and NH3, forming a high-resistivity a-
Si:H film 4 by using SiH4 and forming a n+ a-Si:H film 20 from
a mixed gas of PH3 and SiH4 in the same evacuated chamber in
a plasma CVD [chemical vapor deposition] apparatus.
(Col. 2, ll. 23-30.) Therefore, reading the claim limitation “without
exposing them to an oxidizing atmosphere” in the context of the entire
patent, we interpret this claim limitation as processing the thin-film
transistor in a CVD (or similar) vacuum apparatus in the absence of an
oxygen-containing gas, while avoiding exposure to atmospheric air.
In reference to manufacturing of the amorphous silicon MIS-type
transistor, Kawasaki explains that:
Next, the following are deposited on the entire surface: the gate
insulating layer 3 composed of such material as silicon nitride,
the amorphous silicon layer 4, and said amorphous silicon 5
with impurities. Layer 4, which serves as a donor or an
acceptor, contains almost no impurity. The deposition method
of these thin films is facilitated by plasma deposition using
glow discharge of silane gas [SiH4]. If silicon nitride is desired
in the gate insulating layer 3, then ammonia [NH3] should be
added in the gas used for thin film fabrication. If amorphous
silicon with impurities is desired, then diborane [B2H6] or
phosphine [PH3] should be added.
(P. 3, “Constitution of prior art and problems thereof,” para. 2.)
Accordingly, because Kawasaki explains that the gate insulating layer 3, the
amorphous silicon layer 4, and the amorphous silicon 5 are deposited in a
glow discharge using silane, ammonia, and diborane or phosphine, we agree
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with the Examiner that Kawasaki teaches the limitation “continuously
depositing . . . a gate insulating film, a high-resistivity semiconductor film
and a conducting film . . . without exposing them to an oxidizing
atmosphere.”
Appellant argues that:
The Declaration of Dr. Gary Rubloff . . . gives significant
and extensive evidentiary support for the lack of inherency,
based on standard mid-1980’s practices. . . . . Moreover, the
glow discharge could be stopped, and the Examiner does not
assert that it must be performed without stopping. Therefore,
the glow discharge process is not necessarily performed without
stopping and, thus, not inherent.
(Br. 16.) However, as discussed previously, when claim 1 is construed in
view of the ’737 patent, we agree with the Examiner (Ans. 4, 9) that the
claim limitation “continuously depositing . . . a gate insulating film, a high-
resistivity semiconductor film and a conducting film . . . without exposing
them to an oxidizing atmosphere” is broad enough to encompass
manufacturing the amorphous silicon MIS-type transistor of Kawasaki,
which includes depositing the gate insulating layer 3, the amorphous silicon
layer 4, and the amorphous silicon 5 by glow discharge using silane,
ammonia, and diborane or phosphine (i.e., in the absence of an oxygen-
containing gas).
Appellant also argues that “it should be apparent to one skilled in the
art that adhesions to the chamber walls in a vacuum environment become
part of the internal ‘atmosphere’ during gassing processes,” with a citation to
paragraph 18 of the Rubloff Declaration. (Br. 16.) Similarly, Appellant
argues that “[s]imply stating that the process is under vacuum such as in a
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glow discharge CVD process does not assure that the deposited material is
not degraded by oxidation,” with a citation to paragraph 15 of the Rubloff
Declaration. (Br. 17.) However, Appellant’s arguments are not
commensurate in scope with claim 1 because the claim does not expressly
recite the degree of chemical purity with respect to the oxygen content or
degradation due to oxygen content. Furthermore, the statements from
paragraphs 15 and 18 of the Rubloff Declaration relied upon by Appellant
lack persuasive factual support because such paragraphs do not cite to any
persuasive corroborating documentation. See In re Beattie, 974 F.2d 1309,
1313 (Fed. Cir. 1992) (“[D]eclarations themselves offer only opinion
evidence which has little value without factual support.”).
Therefore, we agree with the Examiner that Kawasaki describes the
limitation “continuously depositing . . . a gate insulating film, a high-
resistivity semiconductor film and a conducting film . . . without exposing
them to an oxidizing atmosphere.”
Accordingly, we sustain the rejection of independent claim 1 under 35
U.S.C. § 102(b).

§ 103 Rejection
We are unpersuaded by Appellant’s arguments (Br. 17-23) that the
combination of Kawasaki and Okubo would not have rendered obvious
independent claim 1, which includes the limitation “continuously depositing
. . . a gate insulating film, a high-resistivity semiconductor film and a
conducting film . . . without exposing them to an oxidizing atmosphere.”
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In the alternative, the Examiner found that the manufacturing steps of
Okubo, in which semiconductor layers (e.g. silicon nitride, amorphous
silicon) are continuously formed in a vacuum vessel, correspond to the
limitation “continuously depositing . . . a gate insulating film, a high-
resistivity semiconductor film and a conducting film . . . without exposing
them to an oxidizing atmosphere.” (Ans. 6, 11-12; Okubo, col. 10, l. 66 to
col. 11, l. 2.) We agree with the Examiner.
Okubo relates to a thin film transistor array for a display apparatus, in
particular, using amorphous silicon as a semiconductor. (Col. 1, ll. 11-15.)
Figures 7A to 7H of Okubo illustrate the manufacturing process for forming
a thin-film transistor in a vacuum vessel. (Col. 10, ll. 61-65; see also col. 5,
ll. 25-27.) Okubo explains that “[w]hen an insulating layer is made of
silicon nitride, semiconductor amorphous silicon, and an n+ layer
amorphous silicon doped with phosphorus, arsenic, or the like, these
materials can be continuously decomposed by glow discharged in one
vacuum vessel.” (Col. 10, l. 66 to col. 11, l. 2.) Because Okubo explains
that silicon nitride, amorphous silicon, and doped amorphous silicon are
deposited by glow discharge in a vacuum vessel, Okubo teaches the
limitation “continuously depositing . . . a gate insulating film, a high-
resistivity semiconductor film and a conducting film . . . without exposing
them to an oxidizing atmosphere.”
First, Appellant argues that “Okubo discloses that the steps in FIGs.
7B through 7D, or FIGs. 7B through 7E, can be conducted continuously and
that a silicon nitride film, and an amorphous silicon film, and an n+
amorphous silicon film can be continuously decomposed in one vacuum
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vessel” and that “[t]his in no way implies that exposure to an oxidizing
atmosphere must be avoided,” with a citation to paragraph 21 of the Rubloff
Declaration. (Br. 18.) However, as discussed previously, when claim 1 is
construed in view of the ’737 patent, the claim limitation “continuously
depositing . . . a gate insulating film, a high-resistivity semiconductor film
and a conducting film . . . without exposing them to an oxidizing
atmosphere” is broad enough to encompass the exemplary manufacturing
steps of Okubo for the a thin-film transistor in which a “[silicon nitride]
insulating layer . . . , semiconductor amorphous silicon, and an n+ layer
amorphous silicon . . . can be continuously decomposed by glow discharged
in one vacuum vessel” (col. 10, l. 66 to col. 11, l. 2). Furthermore, the
statements from paragraph 21 of the Rubloff Declaration relied upon by
Appellant lack persuasive factual support because this paragraph does not
cite to any persuasive corroborating documentation. See Beattie, 974 F.2d at
1313.
Second, Appellant also argues that “Okubo . . . teaches that ‘SiO2,
Al2O3, and SiN3 may be preferably used as the material of the insulating
layer 9’, and other metallic oxide, or fluoride may be used’” and that “[i]t
should be clear that SiO2, Al2O3, and metallic oxides, by definition, contain
oxygen, and are formed using an oxidizing atmosphere.” (Br. 19.)
However, the Examiner cited the embodiment of Okubo, in which the
insulating layer 9’ is formed of silicon nitride, rather than silicon dioxide or
aluminum oxide, for teaching the limitation “continuously depositing . . . a
gate insulating film, a high-resistivity semiconductor film and a conducting
film . . . without exposing them to an oxidizing atmosphere.” (Ans. 6, 11-
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12.) Accordingly, Appellant’s argument does not directly address the
embodiment of Okubo (i.e., a silicon nitride insulating layer) cited by the
Examiner.
Third, to rebut the Examiner’s obviousness rejection, Appellant
argues that “in October 1999, LPL [LG Philips LCD] filed suit against NEC
for infringement of several patents including the ’737 patent” and that “[i]n
consideration for settling the pending infringement litigation brought by
LPL, the two parties entered into a cross-licensing agreement in April 2001.”
(Br. 21.) Similarly, Appellant argues that “in 2007, CPT [Chunghwa Picture
Tubes] entered into a settlement release agreement with LPL after the
adverse jury award involving the ’737 patent.” (Br. 22.) However, this
licensing activity may be due to factors unrelated to the unobviousness of
the claims of the ’737 patent such as the license being mutually beneficial or
less expensive than defending infringement suits. See EWP Corp. v.
Reliance Universal, Inc., 755 F.2d 898, 907-08 (Fed. Cir. 1985). Moreover,
Appellant has not established a nexus between the success of such licensing
activates and the claims of the ’737 patent.
Last, to rebut the Examiner’s obviousness rejection, Appellant argues
that “[t]he process of the ’737 patent is commercially successful” because
“LG Display’s use of the asserted claims of the ’737 patent enabled it to
provide a higher quality, more valuable product” and “[b]y improving the
electrical contact between the various layers of a TFT, the ’737 patent
improves the performance of the TFT and the operation of the LCD,” with a
citation to paragraph 27 of the Rubloff Declaration. (Br. 22.) However, the
statements in paragraph 27 of the Rubloff Declaration are conclusory
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statements that are based on insufficient evidence (e.g., a description of the
product sold, including features of the invention as claimed, a description of
the relevant market, and sales figures). Additionally, Appellant has not
established a nexus between the purported success of the LG TFT device
and the claims of the ’737 patent.
Thus, we agree with the Examiner that the combination of Kawasaki
and Okubo would have rendered obvious independent claim 1, which
includes the limitations “continuously depositing . . . a gate insulating film, a
high-resistivity semiconductor film and a conducting film . . . without
exposing them to an oxidizing atmosphere.”
Accordingly, we sustain the rejection of independent claim 1 under 35
U.S.C. § 103(a).

DECISION
The Examiner’s decision rejecting claim 1 is affirmed.
Requests for extensions of time in this ex parte reexamination
proceeding are governed by 37 C.F.R. § 1.550(c). See 37 C.F.R. § 41.50(f).

AFFIRMED

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Third Party Requester:

BILLY C. ALLEN III
WONG, CABELLO, LUTSCH RUTHERFORD & BRUCCULERI, LLP
20333 SH 249
6TH FLOOR
HOUSTON, TX 77070

Patent Owner:

RACHAEL LEA LEVENTHAL
MORGAN LEWIS & BOCKIUS LLP (WA)
1111 PENNSYLVANIA AVENUE NW
WASHINGTON, DC 20004