ELPIS TECHNOLOGIES INC.Download PDFPatent Trials and Appeals BoardOct 27, 20212021000004 (P.T.A.B. Oct. 27, 2021) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/796,121 10/27/2017 Lei Shan PAT 108545A-2 4300 139548 7590 10/27/2021 VanTek IP LLP 101-1001 West Broadway Suite 380 Vancouver, BRITISH COLUMBIA V6H4E4 CANADA EXAMINER LU, FARUN ART UNIT PAPER NUMBER 2898 NOTIFICATION DATE DELIVERY MODE 10/27/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): mail@vantekip.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte LEI SHAN Appeal 2021-000004 Application 15/796,121 Technology Center 2800 Before TERRY J. OWENS, JEFFREY T. SMITH, and N. WHITNEY WILSON, Administrative Patent Judges. SMITH, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1–6. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE. 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies the real party in interest as International Business Machines Corporation. (Appeal Br. 1.) Appeal 2021-000004 Application 15/796,121 2 CLAIMED SUBJECT MATTER The claims are directed to semiconductor structure useful as an interposer to spread a connection to a wider pitch or to reroute a connection to a different connection. (Spec ¶ 2.) Claim 1 reproduced below, is illustrative of the claimed subject matter: 1. A semiconductor structure comprising: a base layer with a first surface and a second surface; a capacitor located in the base layer, wherein the capacitor is substantially parallel to the first surface, and wherein the capacitor comprises a first electrical connection on a first side of a dielectric of the capacitor and a second electrical connection on a second side of the dielectric of the capacitor; a first laminate layer located on the first surface of the base layer, a second laminate layer located on the second surface of the base layer, and an intermediate laminate layer located between the base layer and the capacitor; a first plurality of conductive pads located on the first laminate layer, a second plurality of conductive pads located on the second laminate layer, and a plurality of conductive vias between the first plurality of conductive pads and the second plurality of conductive pads, wherein the first plurality of conductive pads and the second plurality of conductive pads are patterned on each side of the electrical connection of the capacitor, wherein each of the first plurality of conductive pads is in contact with only one conductive via of the plurality of conductive vias, wherein each of the first plurality of conductive pads is non-contiguous with another pad of the first plurality of conductive pads, wherein each of the second plurality of conductive pads is in contact with only one conductive via of the plurality of conductive vias, and wherein each of the second plurality of Appeal 2021-000004 Application 15/796,121 3 conductive pads is non-contiguous with another pad of the second plurality of conductive pads; and a first portion of a first conductive via of the plurality of conductive vias extending from a first conductive pad of the first plurality of conductive pads to the first electrical connection of the capacitor, and a first portion of a second conductive via of the plurality of conductive vias extending from a second conductive pad of the first plurality of conductive pads to the second electrical connection of the capacitor; a second portion of the first conductive via of the plurality of conductive vias extending from a first conductive pad of the second plurality of conductive pads to the first electrical connection of the capacitor, and a second portion of the second conductive via of the plurality of conductive vias extending from a second conductive pad of the second plurality of conductive pads to the second electrical connection of the capacitor; a first electrical path is formed by the first portion of the first conductive via, the first electrical connection, and the second portion of the first conductive via, wherein the first electrical path is substantially perpendicular to the first surface and the second surface forming a direct electrical path between the first surface and the second surface; and a second electrical path is formed by the first portion of the second conductive via, the second electrical connection, and the second portion of the second conductive via, wherein the second electrical path is substantially perpendicular to the first surface and the second surface forming a direct electrical path between the first surface and the second surface. (Appeal Br. 16–17, Claim Appendix.) REJECTIONS I. Claims 1–3 were rejected under 35 U.S.C. § 102(a)(1) as anticipated by Ogawa, US 2002/0011351. II. Claims 4 and 5 were rejected under 35 U.S.C. § 103 as obvious over Ogawa in view of Choi, US 2014/0287556. III. Claim 6 is rejected under 35 U.S.C. § 103 as obvious over Ogawa in view of Song, US 2015/0325375. Appeal 2021-000004 Application 15/796,121 4 OPINION After review of the respective positions the Appellant provides in the Appeal Brief and the Examiner provides in the Final Action and the Answer, we reverse the Examiner’s prior art rejections of claims 1–3 under 35 U.S.C. § 102(a)(1), and claims 4–6 under 35 U.S.C. § 103 for essentially the reasons Appellant presents. We add the following for emphasis. Independent claim 1 is directed to a semiconductor structure comprising a plurality of first and second conductive pads patterned on each side of an electrical connection of a capacitor, wherein each of the first and second plurality of conductive pads is in contact with only one conductive via of the plurality of conductive vias and wherein each of the first and second plurality of conductive pads is non-contiguous with another pad of the first and second plurality of conductive pads respectively. The dispositive issue on appeal is: Did the Examiner err in determining that Ogawa describes a semiconductor structure comprising a second plurality of conductive pads (105(b)) that is in contact with only one conductive via of the plurality of conductive vias as required by independent claim 1? We answer this question in the affirmative. The Examiner finds Ogawa discloses a semiconductor structure which anticipates the subject matter of independent claim 1. (Final Act. 2–6.) In support of the anticipation rejection the Examiner relies upon annotated Ogawa figure 5(a) which is reproduced below: Appeal 2021-000004 Application 15/796,121 5 Figure 5(a) depicts a semiconductor structure comprising wiring patterns connected to vias with annotations included by the Examiner identifying various portions of the structure. Appellant presented an annotation of the lower right portion of Ogawa figure 5(a) (the lower right portion) to further clarify the issue on appeal. Appellant’s-annotated version of Ogawa figure 5(a) is reproduced below: Appeal 2021-000004 Application 15/796,121 6 Ogawa figure 5(a) depicts a semiconductor structure comprising wiring patterns connected to vias with annotations included by the Appellant identifying various portions of the structure. The Examiner explains how Ogawa anticipates the claimed invention utilizing Appellant annotated figure 5 (a) as follows: the alleged claim limitations are interpreted as: the second plurality of conductive pads comprises the two pads 32, 34; a plurality of conductive vias comprises two vias 22, 24; each of the two pads 32, 34 is in contact with only one of the vias 22, 24; and wherein each of the two pads 32, 34 is noncontiguous with another of the two pads 32, 34. (Ans. 6.) We do not sustain the Examiner’s rejection. As is evident from reproduced annotated figure 5(a) above, the Examiner’s explanation that a portion of the conductive pad 34 is only connected to one via 24 is not supported. As shown by Appellant-annotated figure 5(a) the second conductive pad 34 is attached to two vias 24 and 26. The Examiner has failed to direct us to portions of Ogawa, or cite to other evidence, that establishes a person of ordinary skill in the art would have been in possession of an arrangement wherein the conductive pads are attached to a single via as required by the claimed invention. Therefore, the Examiner has not met the burden of making a prima facie case of anticipation, which requires pointing out where each and every element of the claimed invention, arranged as required by the claim, is described identically in the reference, either expressly or under the principles of inherency, in a manner sufficient to have placed a person of ordinary skill in the art in possession thereof. See In re Spada, 911 F.2d 705, 708 (Fed. Cir. 1990). Appeal 2021-000004 Application 15/796,121 7 The Examiner’s discussion of the §103 rejections does not provide an explanation addressing the obviousness of connecting conducting pads to a single via as required by independent claim 1. Accordingly, we reverse the prior art rejection of claims 1–3 under 35 U.S.C. §102(a)(1), and claims 4–6 under 35 U.S.C. § 103 for the reasons Appellant presents and those we provide above. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1–3 102(a)(1) Ogawa 1–3 4, 5 103 Ogawa, Choi 4,5 6 103 Ogawa, Song 6 Overall Outcome 1–6 REVERSED Copy with citationCopy as parenthetical citation