DELL PRODUCTS, LP

Patent Trials and Appeals Board

Jan 29, 2021

2020001215 (P.T.A.B. Jan. 29, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/484,735 04/11/2017 Mukund P. Khatri DC-108143 6334
114324 7590 01/29/2021
Larson Newman, LLP (Dell)
3575 Far West Blvd.
#30496
Austin, TX 78731
EXAMINER
BASHAR, MOHAMMED A
ART UNIT PAPER NUMBER
2824
NOTIFICATION DATE DELIVERY MODE
01/29/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
docketing@larsonnewman.com
jjordan@larsonnewman.com
jsmith@larsonnewman.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MUKUND P. KHATRI and
VADHIRAJ SANKARANARAYANAN

Appeal 2020-001215
Application 15/484,735
Technology Center 2800
____________

Before MICHAEL G. McMANUS, SHELDON M. McGEE, and
JANE E. INGLESE, Administrative Patent Judges.

McMANUS, Administrative Patent Judge.

DECISION ON APPEAL

Pursuant to 35 U.S.C. § 134(a), Appellant1 seeks review of the
Examiner’s decision to reject claims 1–20. We have jurisdiction under
35 U.S.C. § 6(b).
We AFFIRM.

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as Dell Products,
LP. Appeal Brief dated June 21, 2019 (“Appeal Br.”) 3.
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CLAIMED SUBJECT MATTER

The present application generally relates to “cost and power optimized
heterogeneous dual-channel DDR DIMMs [Dual In-Line Memory
Modules].” Specification dated April 11, 2017 (“Spec.”) ¶ 1. The
Specification teaches that a dual-channel DIMM may include two memory
elements. Id. ¶ 3. The first memory element is “configured to perform
memory transactions for first memory locations associated with the first
memory element via a first memory channel.” Id. The second memory
element is independent of the first and is “configured to perform memory
transactions for second memory locations associated with the second
memory element via a second memory channel.” Id.
A heterogeneous dual-channel DIMM is depicted in Figure 1 of the
drawings, reproduced below.

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Figure 1 illustrates information handling system 100 that includes processing
complex 110, fifth generation heterogeneous dual-channel DIMM 120, and
heterogeneous dual-channel DIMM 140. Spec. ¶¶ 11, 13.
Claim 1 is illustrative of the subject matter on appeal and is
reproduced below:

1. A dual-channel Dual In-Line Memory Module (DIMM),
comprising:
a first memory element configured to perform memory
transactions for first memory locations associated
with the first memory element via a first memory
channel of the dual-channel DIMM; and
a second memory element configured to perform
memory transactions for second memory locations
associated with the second memory element via a
second memory channel of the dual-channel
DIMM, wherein the first memory channel is
different than the second memory channel, and
wherein the first memory element is a different type
of memory element than the second memory
element.
Appeal Br. 11 (Claims App.).
REFERENCES
The Examiner relies upon the following prior art:
Name Reference Date
Tzeng US 2009/0198874 A1 Aug. 6, 2009
Ma et al. (“Ma”) US 2017/0206033 A1 July 20, 2017
REJECTIONS
The Examiner maintains the following rejections:
1. Claims 1, 2, 6, 8, 9, 11–14, and 16–19 under 35 U.S.C. §
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102(a)(1) as being anticipated by Tzeng. Final Office
Action dated Aug. 23, 2018 (“Final Act.”) 2–7.
2. Claims 3–5, 7, 10, 15, and 20 under 35 U.S.C. § 103 as
being unpatentable over Tzeng in view of Ma. Id. at 7–12.
DISCUSSION
Rejection 1. The Examiner rejects claims 1, 2, 6, 8, 9, 11–14, and
16–19 as anticipated by Tzeng. Id. at 2–7. In support of the rejection, the
Examiner finds that Tzeng teaches a first memory element where read
operations are performed through flash memory and a second memory
element where write operations are performed through DRAM memory. Id.
at 2–3. The Examiner relies, in part, on Figure 5 of Tzeng, reproduced
below.

Figure 5 of Tzeng shows dual channel memory architecture 500. Tzeng
¶ 35. Tzeng discloses that ASIC 510 communicates with a buffer memory
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of DIMM modules 520 over channel 530. Id. Tzeng further discloses that
second channel 540 communicates with FLASH memory 640 “in a DIMM
configuration.” Id.
The Examiner finds that Tzeng’s FLASH memory in a DIMM
configuration and channel 540 teach the claimed “first memory element
configured to perform memory transactions for first memory locations
associated with the first memory element via a first memory channel.” Ans.
2. The Examiner further finds that Tzeng’s DRAM memory (520) and
channel 530 teach the claimed “second memory element configured to
perform memory transactions for second memory locations associated with
the second memory element via a second memory channel.” Id.
Appellant argues independent claims 1, 11, and 16 collectively.
Appeal Br. 6. We select claim 1 as representative. See 37 C.F.R.
§ 41.37(c)(1)(iv). Appellant alleges error on several bases. Appeal Br. 6–9.
Appellant argues that Tzeng does not teach a dual-channel DIMM.
Id. at 6. Appellant further asserts that Tzeng teaches that the FLASH and
DRAM each have only a single connection (rather than two separate
connections) to the memory manager. Id. at 7–8. Appellant additionally
argues that Tzeng does not teach a single DIMM that includes two different
types of memory devices as required by claim 1. Id. at 8.
Appellant adds that, while its disclosure is made in the context of fifth
generation DDR memory (DDR5), which requires that DIMMs support
dual-channel operation, Tzeng concerns previous versions of the DDR
standard. Id. at 8. As a result, Appellant argues, one should construe Tzeng
as relating to DIMMs that are accessed by a single memory channel. Id. at
9.
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In the Answer, the Examiner maintains that Tzeng anticipates the
claims at issue. Examiner’s Answer dated Oct. 2, 2019 (“Ans.”) 3–6. The
Examiner compares Figures 1 and 2 of the drawings with Figures 5–7 of
Tzeng and determines that they are similar. Id. at 3–4.
The Examiner further determines that “dependent claims 3, 6, 7
clearly indicate that each memory element includes DIMM type of memory
element i.e. first memory element comprises NVDIMM (Non-volatile
DIMM) and second memory element comprises basic DIMM (UDRAM,
RDIMM etc.).” Id. at 4.
Claim 3 depends from claim 2. For reference, claims 2 and 3 are
reproduced below.
2. The dual-channel DIMM of claim 1, wherein the first
memory element comprises a nonvolatile DIMM
(NVDIMM) type of memory element.
3. The dual-channel DIMM of claim 2, wherein the first
memory element further comprises a JEDEC Standard
NVDIMM-N type NVDIMM.
Appeal Br. 11 (Claims App.) (emphasis added).
The Examiner construes claim 3 (and similarly structured dependent
claims) to require that the first memory element (a component of the dual-
channel DIMM) must include a nonvolatile DIMM. Ans. 4. Thus, the
Examiner concludes that the device of the claims, like that taught by Tzeng,
may have memory elements that are DIMM structures. Id. at 4–5.
In regard to the construction of the claim term “dual-channel Dual In-
Line Memory Module (DIMM),” the Examiner reasons as follows:
based on appellant’s figures, specification, and dependent
claims, as noted above, the limitation “A dual channel Dual In-
line Memory Module (DIMM)” or “a DIMM” clearly indicate a
combination of two DIMM elements which are coupled to two
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different channels. As the claims do not clarify how both
DIMM elements are to be specifically configured to have “a
DIMM”, the examiner has interpreted the limitation “a DIMM”
be simply referring to a combination of two DIMM elements.
Id. at 4.
The Examiner further cites to Tzeng’s teaching that “[m]emory can be
configured as a dual inline memory module (DIMM) for the ASIC, FLASH,
and/or DRAM buffer respectively” (Tzeng ¶ 26 (emphasis added)) in
support of the notion that “both DRAM DIMM and Flash DIMM can be
arranged together in a single DIMM configuration and can be referred to as
‘a DIMM.’” Id. at 5.
In its Reply Brief, Appellant asserts that Figure 1 of the drawings
teaches that dual-channel DIMMs 120 and 140 are each accessed by two
memory channels. Reply Brief dated Dec. 2, 2019 (“Reply Br.”) 2.
Appellant further asserts that Tzeng fails to disclose a single dual-channel
DIMM having two different types of memory elements that are each
accessed by a different memory channel. Id. at 2–4. In a similar vein,
Appellant argues that, because Tzeng teaches separate DIMMs for the
DRAM and FLASH, it does not disclose different types of memory on a
single DIMM. Id. at 4.
Appellant additionally responds to the Examiner’s determination that
dependent claims 3, 6, and 7 weigh in favor of a broad construction of
“DIMM.” Id. at 4–6. Appellant argues that claim 3 must be read in view of
claim 2, from which it depends. Id. at 5. Claim 2 depends from claim 1 and
further requires that “the first memory element comprises a nonvolatile
DIMM (NVDIMM) type of memory element.” Appeal Br. 11 (Claims
App.) (emphasis added). Claim 3 requires that “the first memory element
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further comprises a JEDEC Standard NVDIMM-N type NVDIMM.” Id.
(emphasis added).
Appellant argues that the claim 2’s use of the phrase “type of memory
element” limits the first memory element to a nonvolatile DIMM
(NVDIMM) type of memory element and that claim 3’s use of “a JEDEC
Standard NVDIMM-N type NVDIMM” merely narrows the memory
element further. Id. at 5. Appellant argues that claims 6 and 7 are similarly
structured. Id. Accordingly, Appellant reasons, neither claim 3 nor claim 7
should be interpreted as requiring separate DIMMs, but rather as requiring
types of memory devices that narrow the scope of the memory devices of the
preceding claims. Id.
In further support of its construction, Appellant refers to the
Specification’s teaching that “[d]ual-channel DIMM 120 represents a DIMM
device with heterogeneous storage element types, including non-volatile
DIMM (NVDIMM) storage elements that are connected to the memory
channel 0, and Dynamic Random Access Memory (DRAM) storage
elements that are connected to memory channel l.” Id. at 6 (citing Spec.
¶ 14).
Appellant additionally takes issue with the Examiner’s determination
that Tzeng teaches that both DRAM DIMM and Flash DIMM can be
arranged together in a single DIMM configuration and can be referred to as
“a DIMM.” Id. at 7. Similarly, Appellant asserts that Tzeng does not teach
a single dual-channel DIMM that includes two different types of memory
elements.” Id. at 7–8.
The central point at issue is the scope of the term “dual-channel Dual
In-Line Memory Module (DIMM).” The Examiner construes such term
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broadly so as to include a combination of two DIMM elements which are
coupled to two different channels (as taught by Tzeng). See Ans. 4. Under
this construction, the device of Tzeng would be a DIMM with two memory
channels. Appellant construes the term more narrowly such that a DIMM
would not encompass one or more other DIMMs and, thus, not encompass
the structure of Tzeng.
During examination, claim terms must be given their broadest
reasonable construction consistent with the Specification. In re ICON
Health and Fitness, Inc., 496 F.3d 1374, 1379 (Fed. Cir. 2007). “Giving
claims their broadest reasonable construction ‘serves the public interest by
reducing the possibility that claims, finally allowed, will be given broader
scope than is justified. In re Amer. Acad, of Sci. Tech Ctr., 367 F.3d 1359,
1364 (Fed. Cir. 2004) (citations omitted). “An essential purpose of patent
examination is to fashion claims that are precise, clear, correct, and
unambiguous. Only in this way can uncertainties of claim scope be
removed, as much as possible, during the administrative process.” In re
Zletz, 893 F.2d 319, 322 (Fed. Cir. 1989).
In the present case, claim 3 requires that “the first memory element
further comprises a JEDEC Standard NVDIMM-N type NVDIMM.”
Appeal Br. 11. The Examiner determines that this indicates that the
“memory element” limitation may include a DIMM structure (in this
instance, an NVDIMM). While this is disputed by Appellant, the language
of the claim provides sufficient support for the Examiner’s view as to render
it reasonable. The portion of the Specification cited by Appellant (¶ 14) is
unavailing as it 1) is limited to a specific embodiment, and 2) does not
clearly indicate that a DIMM may not be a “storage element.” See Spec.
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¶ 14. Nor has Appellant introduced evidence of plain meaning in the art
(e.g., technical dictionaries, technical standards) in support of its proposed
construction.
Reciting the phrase “further comprising” in dependent claim 3
suggests the NVDIMM is an additional structural element in the first
memory element, not a further identification of “what the NVDIMM type of
memory element is” as argued by Appellant. Reply Br. 5; see Exxon Chem.
Pats. Inc. v. Lubrizol Corp., 64 F.3d 1553, 1555 (Fed. Cir. 1995) (explaining
that the recitation of “comprising” means “containing at least” the elements
recited in the claim); In re Baxter, 656 F.2d 679, 686 (CCPA 1981) (“[T]he
term ‘comprises’ permits the inclusion of other steps, elements, or
materials.”).
In view of the foregoing, on the present record we determine that
Appellant has not shown error in the Examiner’s finding that Tzeng teaches
a dual-channel Dual In-Line Memory Module (DIMM) as claimed.

Rejection 2. The Examiner rejects claims 3–5, 7, 10, 15, and 20 as
obvious over Tzeng in view of Ma. Final Act. 7–12. On Appeal, Appellant
argues that this rejection should be reversed for the same reasons advanced
with respect to Rejection 1, supra. As we have found such arguments to be
unpersuasive, we determine that Appellant has not shown error with regard
to the rejection of claims 3–5, 7, 10, 15, and 20.

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CONCLUSION

In view of the findings and analysis set forth in the Final Office
Action, the Examiner’s Answer, and above, the Examiner’s rejections are
affirmed.
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/Basis Affirmed Reversed
1, 2, 6, 8, 9,
11–14, 16–
19
102(a)(1) Tzeng 1, 2, 6, 8, 9,
11–14, 16–
19

3–5, 7, 10,
15, 20
103 Tzeng, Ma 3–5, 7, 10,
15, 20

Overall
Outcome
1–20

No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a).

AFFIRMED