Crossbar, Inc.

Patent Trials and Appeals Board

Feb 19, 2021

2019006429 (P.T.A.B. Feb. 19, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
13/673,951 11/09/2012 George MINASSIAN A936SP-001000US/
CROSP175U
8559
129485 7590 02/19/2021
Wegman Hessler / Crossbar
6055 Rockside Woods Blvd
Suite 200
Cleveland, OH 44131
EXAMINER
LANIER, BENJAMIN E
ART UNIT PAPER NUMBER
2437
NOTIFICATION DATE DELIVERY MODE
02/19/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
intellectualproperty@wegmanlaw.com
mfclapper@wegmanlaw.com
whvipgroup@wegmanlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte GEORGE MINASSIAN
____________

Appeal 2019-006429
Application 13/673,951
Technology Center 2400
____________

Before JOHN A. JEFFERY, LARRY J. HUME, and CATHERINE
SHIANG, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Under 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s
decision to reject claims 1, 4–11, and 14–25. We have jurisdiction under
35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as Crossbar, Inc.
Appeal Br. 2.
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STATEMENT OF THE CASE
Appellant’s secure circuit device includes a logic layer with a logic
circuit, first and second memory layers, and connectors between the logic
layer and the memory layers. The logic circuit (1) executes logic operations
in an unlocked state when a security key is accessible, and (2) does not
execute logic operations in a locked state when the key is inaccessible. The
security key includes first and second key portions disposed in respective
memory layers. See Abstract. Claim 1 is illustrative:
1. A secure semiconductor chip comprising:
a logic layer that comprises a logic circuit formed within the
logic layer, wherein the logic circuit executes logic operations in
response to being in an unlocked state and that does not execute logic
operations in response to being in a locked state, wherein the logic
circuit is in the unlocked state in response to a security key being
determined to be accessible and is in the locked state in response to
the security key being determined to be inaccessible;
a first memory layer disposed over a second memory layer, the
first and second memory layers comprising non-volatile memory cells
disposed over the logic layer and integrated with the logic layer in a
monolithic structure embodying the secure semiconductor chip; and
a plurality of connectors within through hole vias provided
between the logic layer and the first and second memory layers
facilitating intra-chip communication within an interior of the
secure semiconductor chip, wherein the plurality of connectors
electrically and communicatively couple the logic circuit of the logic
layer and the first and second memory layers;
wherein the security key comprises:
a first security key portion disposed in the non-volatile memory
cells of the first memory layer, and
a second security key portion disposed in the non-volatile
memory cells of the second memory layer.
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THE REJECTIONS2
The Examiner rejected claims 1, 5, 7, 11, 15–17, 20–23, and 25 under
35 U.S.C. § 103 as unpatentable over Fischer (US 2006/0289658 A1;
published Dec. 28, 2006), Clark (US 8,860,197 B2; issued Oct. 14, 2014),
and Norman (US 2009/0182965 Al; published July 16, 2009). Final Act. 7–
15.3
The Examiner rejected claims 4 and 14 under 35 U.S.C. § 103 as
unpatentable over Fischer, Clark, Norman, and Appenzeller (US
2006/0095771 Al; published May 4, 2006). Final Act. 15.
The Examiner rejected claim 6 under 35 U.S.C. § 103 as unpatentable
over Fischer, Clark, Norman, and Amarilio (US 2014/0009995 Al; published
Jan. 9, 2014). Final Act. 16.
The Examiner rejected claim 8 under 35 U.S.C. § 103 as unpatentable
over Fischer, Clark, Norman, and Holtmanns (US 2012/0057697 Al;
published Mar. 8, 2012). Final Act. 16–17.

2 Because the Examiner withdrew rejections under § 112 (Ans. 3), those
rejections are not before us. Because the Examiner’s withdrawal renders
Appellant’s contentions regarding indefiniteness issues ostensibly implicated
by the Examiner’s claim objection (Appeal Br. 6–7) moot, we need not
consider the merits of those arguments here—arguments that pertain to
petitionable matters that are not before us in any event. See Manual of
Patent Examining Procedure (MPEP) § 706.01 (9th ed. Rev. 10.2019, June
2020) (“[T]he Board will not hear or decide issues pertaining to objections
and formal matters which are not properly before the Board.”); see also
MPEP § 1201 (“The Board will not ordinarily hear a question that should be
decided by the Director on petition . . . .”).
3 Throughout this opinion, we refer to (1) the Final Rejection mailed May 2,
2018 (“Final Act.”); (2) the Appeal Brief filed November 3, 2018 (“Appeal
Br.”); (3) the Examiner’s Answer mailed January 8, 2019 (“Ans.”); and (4)
the Reply Brief filed March 8, 2019 (“Reply Br.”).
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The Examiner rejected claim 8 under 35 U.S.C. § 103 as unpatentable
over Fischer, Clark, Norman, and Yamada (US 2004/0059908 Al; published
Mar. 25, 2004). Final Act. 17.
The Examiner rejected claims 9 and 18 under 35 U.S.C. § 103 as
unpatentable over Fischer, Clark, Norman, and Edelstein (US 2014/0042627
Al; published Feb. 13, 2014). Final Act. 17–18.
The Examiner rejected claim 24 under 35 U.S.C. § 103 as
unpatentable over Fischer, Clark, Norman, and Paul (US 2009/0065591 Al;
published Mar. 12, 2009). Final Act. 18–19.
THE REJECTION OVER FISCHER, CLARK, AND NORMAN
Regarding independent claim 1, the Examiner finds that Fischer’s
secure semiconductor chip has a logic layer with a logic circuit that
(1) executes logic operations responsive to being in an unlocked state when
a security key is determined to be accessible, and (2) does not execute logic
operations responsive to being in a locked state when the security key is
determined to be inaccessible. Final Act. 7–8. The Examiner also finds that
Fischer’s chip includes first and second memory layers in connection with
respective parts of non-volatile memory 12b in Figure 1, where a first
security key portion is disposed in non-volatile memory cells of the first
memory layer. See Final Act. 8.
Although the Examiner acknowledges that Fischer does not disclose
(1) disposing the first memory layer over the second memory layer; (2) the
recited connectors within through hole vias between the logic and memory
layers that facilitate intra-chip communication within the chip’s interior; and
(3) a second security key portion disposed in non-volatile memory cells of
the second memory layer, the Examiner cites Norman for teaching element
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(1), and Clark for teaching elements (2) and (3) in concluding that the claim
would have been obvious. Final Act. 8–10.
Appellant argues that the cited prior art does not teach or suggest the
recited logic circuit functionality that, among other things, does not execute
logic operations responsive to being in a locked state when the security key
is determined to be inaccessible. Appeal Br. 16–17. According to
Appellant, Fischer does not contemplate the disclosed key’s inaccessibility,
but rather reads the key from memory for verification. Id. Appellant adds
that the Examiner’s reliance on Clark is also misplaced, for not only is Clark
not a monolithic integrated device, but rather a compilation of disparate
components soldered together with solder balls, Clark’s vias are said to be
external to the chip thus facilitating inter-chip communication—not intra-
chip communication within the chip itself. Id. 17–18; Reply Br. 2–3, 5.4
Norman is also said to be deficient because, among other things, Norman
does not transfer security keys between the disclosed memory and logic
layers, but rather transfers keys to an obfuscation layer manager in a
memory access circuit that is adjacent to—but does not underly—memory
storage layers. Appeal Br. 17–18; Reply Br. 3.
ISSUE
Under § 103, has the Examiner erred in rejecting claim 1 by finding
that Fischer, Clark, and Norman collectively would have taught or suggested
a secure semiconductor chip with (1) a logic layer comprising a logic circuit

4 Although the Reply Brief is unpaginated (unlike the Appeal Brief), we
nonetheless refer to the Reply Brief’s pages in the order they appear in the
record.
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that (a) executes logic operations responsive to being in an unlocked state
when a security key is determined to be accessible, and (b) does not execute
logic operations responsive to being in a locked state when the security key
is determined to be inaccessible; (2) a first memory layer disposed over a
second memory layer, where the memory layers comprise non-volatile
memory cells disposed over the logic layer and integrated with the logic
layer in a monolithic structure embodying the chip; and (3) connectors
within through hole vias between the logic and memory layers that facilitate
intra-chip communication within the chip’s interior?
ANALYSIS
As noted above, a key aspect of the claimed invention is the logic
circuit being in (1) an unlocked state responsive to a security key being
determined as accessible, and (2) a locked state responsive to the key being
determined as inaccessible. The Examiner finds these limitations are taught
by Fischer’s verification functionality in Figure 3. See Final Act. 7–8;
Ans. 3–4. As shown in Fischer’s Figure 3, a result read from a chip’s
memory is verified in step 32 by reading out a key “k” from the chip’s first
memory area 120a—a non-volatile memory illustrated in Figure 1. See
Fischer ¶¶ 22–23, 28. A positive verification allows initiating further steps
in step 34, including continuing booting the chip’s central processing unit
(CPU). Fischer ¶ 28.
On this record, we see no error in the Examiner’s reliance on this
functionality in Fischer for at least suggesting a chip logic circuit that
executes logic operations, namely booting the chip’s CPU, in an unlocked
state when a security key is accessible, namely when the stored key is
retrieved and used for verification. See Ans. 4. Although Fischer does not
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say what happens when the key is inaccessible, Fischer does say that a
“negative result” from step 32’s verification results in taking various
security measures, including output interruptions, error messages, etc.
Fischer ¶ 28. Although this “negative result” can occur after reading the key
from memory, we nonetheless see no reason why it cannot also occur if the
key is inaccessible by, among other things, damage, data corruption, or any
other anomaly that would preclude, or otherwise compromise, a positive
verification—an obvious variation given Fischer’s functionality. To the
extent Appellant contends otherwise (see Appeal Br. 16–17), there is no
persuasive evidence on this record to substantiate such a contention.
Nor do we find error in the Examiner’s reliance on Fischer for at least
suggesting the recited memory layers comprising non-volatile memory cells
disposed over the logic layer and integrated with the logic layer in a
monolithic structure embodying the chip. See Final Act. 7–8. Although
Appellant refers to Fischer’s logic chip 12 that is separate from memory chip
14 and connected to a printed circuit board in Figure 1 (Appeal Br. 18),
Appellant ignores the structure of the logic chip itself that, as shown in the
partial detail view below, is depicted as a logic circuit 12A that overlies non-
volatile memory 12B, where the memory’s first part 120A includes key “k”
and overlies second part 120B. See Fischer ¶ 22.
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Partial detail view of Fischer’s Figure 1 showing logic chip
As shown above, the chip’s region with logic circuit 12A overlies the
region with non-volatile memory 12B with its first memory part 120A (that
contains the key “k”) disposed over second memory part 120B. This
structural depiction provides at least some factual basis to support the
Examiner’s finding that Fischer at least suggests the recited memory layers
comprising non-volatile memory cells integrated with the logic layer in a
monolithic structure embodying the chip. See Final Act. 7–8. We reach this
conclusion even in light of Appellant’s proffered definition of the term
“monolithic integrated circuit” on pages 2 and 3 of the Reply Brief, for
Appellant does not squarely address—let alone persuasively rebut—the
Examiner’s reliance on Fischer’s Figure 1 for at least suggesting the recited
monolithic structure (see Final Act. 8), or that such a structure would have
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been at least an obvious variation given the logic chip’s structural depiction
in Figure 1.
Notably, Appellant’s arguments regarding the alleged shortcomings of
Norman and Clark regarding the recited monolithic structure (Appeal
Br. 17–18; Reply Br. 2–3, 5) are inapposite to the Examiner’s reliance on
Fischer for teaching that feature. See Final Act. 8. Although Fischer does
not refer to the respective regions corresponding to those with the chip’s
logic circuit 12A and non-volatile memory 12B in Fischer’s Figure 1 as
layers, this structural depiction nonetheless at least suggests as much. To the
extent Appellant contends otherwise, there is no persuasive evidence on this
record to substantiate such a contention.
To be sure, Fischer’s memory “layers” 120A and 120B in Figure 1 are
disposed under—not over—the “layer” with logic circuit 12A.
Nevertheless, we see no error in the Examiner’s reliance on Norman’s
Figure 1A and 1B for at least suggesting that disposing memory layers 114
over a logic layer 120 is known in the art, and, in light of this teaching, it
would have been obvious to dispose the layers of Fischer’s chip similarly.
See Final Act. 10. Such an enhancement uses prior art elements predictably
according to their established functions—an obvious improvement. See KSR
Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 417 (2007).
Nevertheless, the Examiner’s reliance on Clark for teaching the
recited connectors within through hole vias between the logic and memory
layers that facilitate intra-chip communication within the chip’s interior is
problematic on this record. Final Act. 9; Ans. 5–6. First, a key aspect of the
recited connectors is their facilitating intra-chip communication within the
chip’s interior. The Examiner, however, admits that Clark does not disclose
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the recited intra-chip communication, but nonetheless concludes, without
evidentiary support, that selecting “well known and widely used” intra-chip
connectivity instead of other known connectivity types, including inter-chip
connectivity, would have ostensibly been “an obvious matter of design
choice” and within the knowledge of ordinarily skilled artisans. Final
Act. 9–10. The Examiner adds that the recited facilitating intra-chip
communication within the chip’s interior is also ostensibly directed to the
connectors’ “intended use.” Ans. 6.
We disagree. First, as Appellant explains, Clark’s vias facilitate inter-
chip communication, namely between a chip 705, 805 and its associated
adjacent security layers 710, 810 in Figures 7 and 8, respectively. See Clark
col. 7, ll. 30–42; col. 8, ll. 4–18. Given this critical inter-chip
communication between the chip and security layers, to suggest that it would
have somehow been an obvious design choice to select intra-chip
connectivity instead of inter-chip connectivity in Clark’s system as the
Examiner proposes (Final Act. 9–10) is not only unsubstantiated on this
record, the Examiner’s proposal runs counter to the critical inter-chip
communication that is essential to realizing Clark’s functionality.
The Examiner’s construing the recited facilitating intra-chip
communication within the chip’s interior as ostensibly directed to the
connectors’ “intended use” (Ans. 6) is likewise untenable on this record. As
Appellant indicates, the recited intra-chip communication facilitation is not
mere intended use, but rather a functional characteristic of the recited
connectors that are situated between monolithically integrated layers of a
secure semiconductor chip. Reply Br. 6. And even if the recited intra-chip
communication facilitation could somehow be considered mere intended use
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as the Examiner proposes—which it is not—the Examiner has not shown
that Clark’s solder balls 322, 324 that the Examiner presumably maps to the
recited connectors (see Final Act. 9) are capable of performing the purported
intended use. See In re Schreiber, 128 F.3d 1473, 1477–78 (Fed. Cir. 1997);
see also MPEP § 2114(II). Accord Ans. 6 (noting that if a prior art structure
is capable of performing the intended use, it meets the claim). Not only are
solder balls 322, 324 located external to chip 305—a chip that lacks vias
unlike the embodiments of Clark’s Figures 7 and 8—it is unclear how these
external solder balls that are designed to facilitate communication with
security layers 310 and 312 external to the chip would also be capable of
facilitating intra-chip communication within the chip’s interior as claimed.
We reach the same conclusion regarding the embodiments of Clark’s
Figures 7 and 8. Although the chips in these embodiments have electrically
conductive vias 760 and 860, respectively, we fail to see—nor has the
Examiner shown—that the solder-ball “connectors” under the Examiner’s
mapping are capable of facilitating intra-chip communication within the
chip’s interior, particularly since the solder ball “connectors” are not within
the vias as recited in claim 1 or unexposed to the chip’s exterior as recited in
claim 11. Therefore, even if the recited intra-chip communication could
somehow be considered a mere intended use of the recited connectors—
which it is not—the Examiner has still not shown the relied-upon connectors
in Clark would be capable of performing this purported intended use.
Accordingly, we are persuaded that the Examiner erred in rejecting
(1) independent claim 1; (2) independent claim 11 that recites commensurate
limitations; and (3) dependent claims 5, 7, 15–17, 20–23, and 25 for similar
reasons.
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THE OTHER OBVIOUSNESS REJECTIONS
Because the Examiner has not shown that the additional cited prior art
cures the foregoing deficiencies regarding the rejection of the independent
claims, we will not sustain the obviousness rejections of dependent claims 4,
6, 8–10, 14, 18, 19, and 24 (Final Act. 15–19) for similar reasons.
CONCLUSION
In summary:
Claims
Rejected
35 U.S.C.
§
Reference(s)/
Basis
Affirmed Reversed
1, 5, 7,
11, 15–
17, 20–
23, 25
103 Fischer, Clark,
Norman
1, 5, 7,
11, 15–
17, 20–
23, 25
6 103 Fischer, Clark,
Norman,
Appenzeller
6
8 103 Fischer, Clark,
Norman,
Holtmanns
8
9, 18 103 Fischer, Clark,
Norman,
Yamada
9, 18
10, 19 103 Fischer, Clark,
Norman,
Edelstein
10, 19
24 103 Fischer, Clark,
Norman, Paul
24
Overall
Outcome
1, 4–11,
14–25
REVERSED