Cree, Inc.Download PDFPatent Trials and Appeals BoardMar 26, 202015344735 - (D) (P.T.A.B. Mar. 26, 2020) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/344,735 11/07/2016 Qingchun Zhang 1194-125C 7979 27820 7590 03/26/2020 WITHROW & TERRANOVA, P.L.L.C. 106 Pinedale Springs Way Cary, NC 27511 EXAMINER YECHURI, SITARAMARAO S ART UNIT PAPER NUMBER 2818 NOTIFICATION DATE DELIVERY MODE 03/26/2020 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): patents@wt-ip.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte QINGCHUN ZHANG and BRETT HULL Appeal 2019-003404 Application 15/344,735 Technology Center 2800 Before ROMULO H. DELMENDO, JAMES C. HOUSEL, and BRIAN D. RANGE, Administrative Patent Judges. HOUSEL, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1–9, 11–17, and 19–24. We have jurisdiction under 35 U.S.C. § 6(b). We REVERSE, but designate a NEW GROUND OF REJECTION pursuant to 37 C.F.R. § 41.50(b).2 1 We use the word Appellant to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as Cree, Inc. Appeal Brief (“Appeal Br.”) filed November 21, 2018. 2 Our Decision additionally refers to the Specification (“Spec.”) filed November 7, 2016, the Examiner’s Final Office Action (“Final Act.”) dated Appeal 2019-003404 Application 15/344,735 2 CLAIMED SUBJECT MATTER The invention is directed to transistor structures, such as metal oxide semiconductor field effect transistors (“MOSFETs”), having reduced electrical field at the gate oxide. Spec. ¶ 2. More particularly, Appellant discloses providing a doped region within the junction field effect (“JFET”) region of the transistor device, wherein the doping of the doped region is of the same type as the doping of the wells. Id. ¶ 5–7. According to Appellant, the doped region within the JFET reduces an electrical field at the gate oxide interface, resulting in improved device reliability and reduction of the possibility of hot carriers injecting into the gate oxide during long-term blocking operation, in which the drain is place under a high positive bias. Id. ¶ 4. Claim 1, reproduced below from the Claims Appendix to the Appeal Brief, is illustrative of the claimed subject matter. The limitation at issue is italicized. 1. A transistor device comprising a gate, a source, and a drain, wherein the gate is at least partially in contact with a gate oxide, where at least one doped region resides within a junction field effect (JFET) region defined between well regions of the transistor device and is completely below a top surface of the JFET region and completely within the JFET region and completely between the well regions in order to reduce an electrical field on the gate oxide such that the at least one doped region does not extend below the well regions. May 31, 2018, the Examiner’s Answer (“Ans.”) dated February 8, 2019, and the Reply Brief (“Reply Br.”) filed March 28, 2019. Appeal 2019-003404 Application 15/344,735 3 Independent claim 9 recites a semiconductor device similar to that of claim 1 and further including, in relevant part, first and second regions of a first conductivity type introduced at the JFET region, at least one of which is implanted to a depth that is between half the well depth and the well depth, and at least one of the first and second regions does not extend below the well regions. REFERENCES The Examiner relies upon the following prior art: Name Reference Date Kinzer et al. (“Kinzer”) US 5,844,259 Dec. 01, 1998 Tihanyi et al. (“Tihanyi”) US 6,184,555 B1 Feb. 06, 2001 Deboy et al. (“Deboy”) US 2001/0020732 A1 Sept. 13, 2001 Nakamura et al. (“Nakamura”) US 2003/0235942 A1 Dec. 25, 2003 Das et al. (“Das”) US 2008/0296771 A1 Dec. 04, 2008 REJECTIONS The Examiner maintains, and Appellant requests our review of, the following grounds of rejection: 1. Claims 1, 3, 8, and 22 under 35 U.S.C. § 102(b) as anticipated by Tihanyi; 2. Claims 2 and 6 under 35 U.S.C. § 103(a) as unpatentable over Tihanyi in view of Deboy; 3. Claims 4, 5, and 7 under 35 U.S.C. § 103(a) as unpatentable over Tihanyi in view of Nakamura; 4. Claims 9, 11, 12, 14–16, 23, and 24 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Tihanyi; 5. Claim 13 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Tihanyi, and further in view of Kinzer; Appeal 2019-003404 Application 15/344,735 4 6. Claims 17, 19, and 21 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Tihanyi, and further in view of Nakamura; and 7. Claim 20 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Tihanyi, and further in view of Deboy. OPINION Rejection 1: Anticipation by Tihanyi After review of the Examiner’s and Appellant’s opposing positions and the appeal record before us, we determine that Appellant’s arguments are sufficient to identify reversible error in the Examiner’s anticipation rejection. In re Jung, 637 F.3d 1356, 1365 (Fed. Cir. 2011). Accordingly, we reverse the stated anticipation rejection for substantially the reasons set forth in the Appeal and Reply Briefs. We offer the following for emphasis only. The Examiner rejects claims 1, 3, 8, and 22 under 35 U.S.C. § 102(b) as anticipated by Tihanyi. Specifically, the Examiner finds that Tihanyi teaches a transistor device as recited in claim 1, having at least one doped region 40, 41 within the JFET region defined between the well regions 5, as shown in Figure 1. Final Act. 2–3. The Examiner further finds that the at least one doped region 40, 41 is completely below a top surface of the JFET, completely within the JFET, and does not extend below the well regions. Id. at 3. The Examiner refers to a portion of Tihanyi, Figure 1 (reference numeral 5 added), reproduced below. Appeal 2019-003404 Application 15/344,735 5 Tihanyi, Fig. 1, Region C, depicting a transistor structure The Examiner finds that Tihanyi teaches intercell zones 13 correspond to the space between and not below well regions 5. Final Act. 4. The Examiner bases this finding on Tihanyi’s disclosures that Figure 1 shows depletion zones and complementary depletion zones “introduced in the intercell zones 13 within the inner zone 2”; that well regions 5 are spatially separated from one another by intercell zones 13; and that these depletion zones are randomly distributed in region C within the inner zone 2. Id. at 3– 4 (emphasis omitted). The Examiner finds that there is no doubt the region between well regions 5 is an integral part of intercell zones 13 and there are depletion zones in intercell zones 13 between well regions 5. Ans. 5. Although Tihanyi’s Figure 1 does not show any depletion zones that are not below well regions 5, the Examiner notes that this drawing is merely an illustration and is not intended to be limiting as to the position of the depletion zones because Tihanyi teaches that the distribution of depletion zones 40, 41 is random. Id. at 6. Therefore, the Examiner finds that random distribution of Appeal 2019-003404 Application 15/344,735 6 the depletion zones would include locations anywhere within the intercell zones including completely within the region between well regions 5. Id. Appellant disputes the Examiner’s finding that Tihanyi teaches that the depletion zones are randomly distributed such that at least one depletion zone is completely between, and does not extend below, well regions 5. Appeal Br. 8. Specifically, Appellant contends that the Examiner’s position that Tihanyi’s depletion zones are randomly distributed anywhere in the intercell zones demonstrates that Tihanyi does not disclose the claimed elements sufficient to anticipate claim 1. Id. at 9. Instead, Appellant urges that the Examiner’s finding is based on possibilities or, at best, probabilities that Tihanyi’s random distribution of depletion zones within region C of zone 2 would provide at least one depletion zone completely between, and not below, well regions 5. Id. at 10. A claim is anticipated only where “each and every limitation is found either expressly or inherently in a single prior art reference.” Celeritas Techs., Ltd. v. Rockwell Int’l Corp., 150 F.3d 1354, 1361 (Fed. Cir. 1998). “[A] prior art reference without express reference to a claim limitation may nonetheless anticipate by inherency.” In re Omeprazole Patent Litig., 483 F.3d 1364, 1373 (Fed. Cir. 2007). Past recognition of the inherent feature is not required. Schering Corp. v. Geneva Pharm., 339 F.3d 1373, 1378 (Fed. Cir. 2003); see also e.g., Gen. Elec. Co. v. Jewel Incandescent Lamp Co., 326 U.S. 242, 249 (1945) (“It is not invention to perceive that the product which others had discovered had qualities they failed to detect.”). In general, a limitation is inherent “if it is the ‘natural result flowing from’ the explicit disclosure of the prior art.” Schering Corp., 339 F.3d at 1379 (quoting Eli Lilly & Co. v. Barr Labs., Inc., 251 F.3d 955, 970 (Fed. Cir. 2001)). Appeal 2019-003404 Application 15/344,735 7 “Inherency . . . may not be established by probabilities or possibilities. The mere fact that a certain thing may result from a given set of circumstances is not sufficient.” MEHL/Biophile Int’l Corp. v. Milgraum, 192 F.3d 1362, 1365 (Fed. Cir. 1999) (quoting In re Oelrich, 666 F.2d 578, 581 (CCPA 1981)). There is no dispute that Tihanyi’s written description, including Figure 1, is silent with regard to the limitation that at least one doped region must be completely within the JFET region between, and not below, the well regions. The Examiner’s position relies on Tihanyi’s disclosure that the depletion zones are randomly distributed in region C, which includes the space between, and not below, well regions 5. However, as Appellant contends, this finding is based on the possibility or probability that a depletion zone may occur, randomly, in the space between, and not below, Tihanyi’s well regions 5. Random distribution only creates a possibility that a depletion zone is provided in this space, whereas anticipation requires that a depletion zone necessarily or inherently is provided. Therefore, a preponderance of the evidence does not support the Examiner’s finding that Tihanyi teaches the recited doped region within the space between, and not below, the well regions. Accordingly, we cannot sustain the Examiner’s anticipation rejection of claims 1, 3, 8, and 22 based on Tihanyi. Rejection 2: Obviousness over Tihanyi and Deboy The Examiner rejects claims 2 and 6 under 35 U.S.C. § 103(a) as unpatentable over Tihanyi in view of Deboy. We note that the Examiner does not rely on Deboy to remedy the deficiency in Tihanyi discussed above. Accordingly, we cannot sustain the Examiner’s obviousness rejection of claims 2 and 6. Appeal 2019-003404 Application 15/344,735 8 Rejection 3: Obviousness over Tihanyi and Nakamura The Examiner rejects claims 4, 5, and 7 under 35 U.S.C. § 103(a) as unpatentable over Tihanyi in view of Nakamura. We note that the Examiner does not rely on Nakamura to remedy the deficiency in Tihanyi discussed above. Accordingly, we cannot sustain the Examiner’s obviousness rejection of claims 4, 5, and 7 on the basis of the Examiner’s reasoning. Rejection 4: Obviousness over Das in view of Tihanyi After review of the Examiner’s and Appellant’s opposing positions and the appeal record before us, we determine that Appellant’s arguments are sufficient to identify reversible error in the Examiner’s obviousness rejection over Das and Tihanyi. Jung, 637 F.3d at 1365. Accordingly, we reverse the stated obviousness rejection for substantially the reasons set forth in the Appeal and Reply Briefs. We offer the following for emphasis only. The Examiner rejects claims 9, 11, 12, 14–16, 23, and 24 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Tihanyi. Specifically, the Examiner finds that Das teaches a semiconductor device substantially as recited in claim 9, except for first and second regions of a first conductivity type introduced at the JFET region to reduce an electrical field at the gate oxide. Final Act. 10. For this missing feature, the Examiner finds Tihanyi teaches a semiconductor device comprising at least one doped region with the JFET region. Id. at 11–12. The Examiner concludes that it would have been obvious to add depletion zones as taught in Tihanyi to Das’s device to control depletion and reduce the electrical field to improve device reliability and electrical behavior. Id. at 13. Appellant argues that Tihanyi fails to teach or suggest that at least one of the depletion zones does not extend below the well regions as required by Appeal 2019-003404 Application 15/344,735 9 claim 9. Appeal Br. 11–12. Appellant also contends that Das does not remedy this deficiency in Tihanyi. Id. at 12. For the reasons given above with regard to rejection 1, we agree. Although this rejection is one of obviousness, rather than anticipation, we note that the Examiner’s reliance on Tihanyi is still based on error in determining the inherency of a random distribution of depletion zones necessarily provides a depletion zone in the JFET that is not below the well regions. Accordingly, we cannot sustain this rejection. Rejections 5–7: Obviousness over Das in view of Tihanyi, and further in view of Kinzer, Nakamura, or Deboy The Examiner rejects claims 13, 17, and 19–21 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Tihanyi, and further in view of one of Kinzer, Nakamura, and Deboy. We note that the Examiner does not rely on any of Kinzer, Nakamura, and Deboy to remedy the deficiency in combination of Das and Tihanyi discussed above. Accordingly, we cannot sustain the Examiner’s obviousness rejections of claims 13, 17, and 19–21. We enter the following new grounds of rejection pursuant to 37 C.F.R. § 41.50(b). New Grounds of Rejection 1 Claims 1, 3–5, 7, 8, and 22 The Examiner finds that Nakamura teaches a transistor device comprising gate 12, source 14, drain 16, gate oxide 10, and at least one P- doped region 20 within JFET region 4. Final Act. 8 (referring to Figs. 1, 3). Nakamura’s gate 12 is in contact with gate oxide 10 and P-doped region 20 resides completely within JFET region 4 and between well regions 6, and is Appeal 2019-003404 Application 15/344,735 10 completely between, and not below, well regions 6. Id.; Figs. 1A–1B; Nakamura ¶¶ 44, 50, 55. Nakamura’s P-doped region 20 is substantially in the middle of the JFET region, and that a plurality of these regions may be provided between well regions 6. Id.; see also id. ¶ 11. Nakamura teaches that P-doped region 20 has the same function as the doped region of the invention, i.e., electric field relaxation or reduction. Nakamura ¶¶ 10–12. Moreover, Nakamura teaches that this electric field reduction depletes the JFET region which increases the breakdown voltage between the source and drain. Id. ¶ 50. We acknowledge that Nakamura’s P-doped region 20 has a top surface at the top surface of JFET region 4 and is thus not completely below the top surface of the JFET region as required by claim 1. However, Tihanyi teaches that depletion zones may be embedded in and below the top surface of JFET region. Tihanyi Fig. 1. Because Nakamura’s P-doped region 20 similarly functions to deplete the JFET region, it would have been obvious to embed Nakamura’s P-doped region 20 below the top surface of the JFET as taught in Tihanyi. A person of skill in the art would have had reason to make this modification because such a configuration was an acceptable alternative configuration known in the art. We, therefore, reject claims 1, 3, 8, and 22 under 35 U.S.C. § 103(a) as unpatentable over Nakamura in view of Tihanyi. Because we make additional findings regarding Nakamura and our reasoning differs from that of the Examiner, we designate this rejection to be a new ground. 37 C.F.R. § 41.50(b). In addition, as the Examiner finds (Final Act. 8), Nakamura teaches that P-doped region 20 may be connected to the source, as required by claim 4 to promote depletion of the JFET region. Nakamura ¶¶ 12, 61. Thus, we Appeal 2019-003404 Application 15/344,735 11 include claim 4 in the obviousness rejection over the combination of Nakamura and Tihanyi. As the Examiner also finds (Final Act. 8), Nakamura teaches that the junction depth of P-doped region 20 is 0.5 µm or less (Nakamura ¶ 55), which encompasses the range of 0.1–.3 µm recited in claim 5. “[A] prima facie case of obviousness typically exists when the ranges of a claimed composition overlap the ranges disclosed in the prior art.” E.I. DuPont de Nemours & Co. v. Synvina C.V., 904 F.3d 996, 1006 (Fed. Cir. 2018), quoting In re Peterson, 315 F.3d 1325, 1329 (Fed. Cir. 2003). Thus, we include claim 5 in the above new ground of rejection. As to claim 7, we note Nakamura fails to teach the relative dimensions of the regions of the semiconductor device, including the width of JFET region 4. As the Examiner finds (Final Act. 9), Nakamura teaches the relationship between dimensions, voltages, and concentrations of these regions and their effect on depletion and resistance. Nakamura ¶¶ 42–64. Nakamura also recognizes that narrowing the JFET region increases the JFET resistance and increases electrical connection loss. Id. ¶ 8. Therefore, it would have been within the ordinary skill in the art to have provided Nakamura’s JFET region with a width in the range recited in claim 7 absent unexpected results. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 421 (2007) (“A person of ordinary skill is also a person of ordinary creativity, not an automaton.”). Claims 2 and 6 As the Examiner further finds (Final Act. 6), Deboy teaches that MOSFETs incorporating p-conductive regions in an n-conductive semiconductor body results in an effective electrical surface field, which is Appeal 2019-003404 Application 15/344,735 12 particularly advantageous in a semiconductor body composed of silicon carbide, whose surface field in the area of thermal oxides needs to be reduced to allow maximum blocking capability. Deboy ¶ 8. It would have been obvious to have formed Nakamura’s MOSFET semiconductor body from silicon carbide because P-doped region 20 would provide the needed electrical surface field reduction at the gate oxide to allow maximum blocking capability as taught by Deboy. Thus, we reject claim 2 under 35 U.S.C. § 103(a) as unpatentable over Nakamura in view of Tihanyi, as applied against claim 1 in the above new ground of rejection, and further in view of Deboy. The Examiner also finds that Deboy teaches the width of p-conductive regions 8 may be approximately 1–3 µm. Final Act. 7; Deboy ¶ 20. Because Nakamura is silent regarding the width of P-doped region 20, the ordinary artisan would have looked to the art to establish this dimension, and would have been guided by Deboy’s teaching as to the width of p-conductive regions 8. We note that because Deboy’s lower endpoint of the width range and the upper endpoint of the width range of claim 6 are the same, i.e., approximately 1 µm, claim 6 is prima facie obvious absent evidence of unexpected results for the claimed range. Peterson, 315 F.3d at 1329. Thus, we include claim 6 in the above new ground of rejection. New Grounds of Rejection 2 Claims 9, 11, 12, 14–17, 19, 21, and 23 As discussed above, Nakamura teaches a transistor device comprising a P-doped region within a JFET region and completely between, and not below, the well regions. Nakamura Figs. 1A–1B; ¶¶ 44, 50, 55. Nakamura teaches that P-doped region 20 may be substantially in the middle of the Appeal 2019-003404 Application 15/344,735 13 JFET region, and that a plurality of these regions may be provided between well regions 6. Id.; see also id. ¶ 11. In addition, as the Examiner finds (Final Act. 8), Nakamura teaches that P-doped region 20 may be connected to the source, as required by claim 4 to promote depletion of the JFET region. Nakamura ¶¶ 12, 61. Nakamura teaches that P-doped region 20 has the same function as the doped region of the invention, i.e., electric field relaxation or reduction. Id. ¶¶ 10–12. Moreover, Nakamura teaches that this electric field reduction depletes the JFET region which increases the breakdown voltage between the source and drain. Id. ¶ 50. It would have been obvious to have provided Das’s semiconductor device with a plurality of P-doped regions within JFET region 734 in order to reduce the electric field at the gate oxide and deplete the JFET region to increase breakdown voltage as taught by Nakamura. With regard to the limitations of claims 11 and 12, as the Examiner finds (Final Act. 13–14), Das teaches that the semiconductor device may be a MOSFET or insulated gate bipolar transistor (“IGBT”). As the Examiner also finds (Final Act. 8), Nakamura teaches that the junction depth of P-doped region 20 is 0.5 µm or less (Nakamura ¶ 55), which encompasses the range of 0.1–.3 µm recited in claim 19. “A prima facie case of obviousness typically exists when the ranges of a claimed composition overlap the ranges disclosed in the prior art.” Peterson, 315 F.3d at 1329. As to claim 21, we note Nakamura fails to teach the relative dimensions of the regions of the semiconductor device, including the width of JFET region 4. As the Examiner finds (Final Act. 9), Nakamura teaches the relationship between dimensions, voltages, and concentrations of these Appeal 2019-003404 Application 15/344,735 14 regions and their effect on depletion and resistance. Nakamura ¶¶ 42–64. Nakamura also recognizes that narrowing the JFET region increases the JFET resistance and increases electrical connection loss. Id. ¶ 8. Therefore, it would have been within the ordinary skill in the art to have provided Nakamura’s JFET region with a width in the range recited in claim 21 absent unexpected results. KSR, 550 U.S. at 421. We, therefore, reject claims 9, 11, 12, 14–17, 19, 21, and 23 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Nakamura. Because we make additional findings regarding Nakamura and our reasoning differs from that of the Examiner, we designate this rejection to be a new ground. 37 C.F.R. § 41.50(b). Claims 13, 20, and 24 Claim 13 depends from claim 9, and further requires that the semiconductor device is a metal oxide semiconductor (“MOS”) controlled thyristor. Das teaches that the device may be a thyristor, but does not teach that the thyristor is MOS controlled. Das ¶ 34. As the Examiner finds (Final Act. 16), Kinzer teaches an MOS controlled thyristor having similar structure to Das. Kinzer 1:7–10. It would have been obvious to configure Das’s semiconductor thyristor device as an MOS thyristor that is controlled by an MOS gate with high reverse breakdown voltage and high forward current for ease of control and low forward drop. Id. at 1:15–25. Thus, we reject claim 13 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Nakamura, and further in view of Kinzer. Claim 20 depends from claim 9, and further requires, among other things, that the width of one of the first and second regions in the JFET region has a width of approximately 0.5–1.0 µm. As the Examiner finds Appeal 2019-003404 Application 15/344,735 15 (Final Act. 7), Deboy teaches the width of p-conductive regions 8 may be approximately 1–3 µm. Deboy ¶ 20. Because Nakamura is silent regarding the width of P-doped region 20, the ordinary artisan would have looked to the art to establish this dimension, and would have been guided by Deboy’s teaching as to the width of p-conductive regions 8. We note that because Deboy’s lower endpoint of the width range and the upper endpoint of the width range of claim 6 are the same, i.e., approximately 1 µm, claim 6 is prima facie obvious absent evidence of unexpected results for the claimed range. Peterson, 315 F.3d at 1329. Thus, we reject claim 20 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Nakamura, and further in view of Deboy. Claim 24 depends from claim 9, and further requires that at least one of the first and second regions is completely below a top surface of the JFET region. Nakamura’s P-doped region 20 has a top surface at the top surface of JFET region 4, and is thus not completely below the top surface of the JFET region. However, Tihanyi teaches that depletion zones may be embedded in and below the top surface of JFET region. Tihanyi Fig. 1. Because Nakamura’s P-doped region 20 similarly functions to deplete the JFET region, it would have been obvious to embed Nakamura’s P-doped region 20 below the top surface of the JFET as taught in Tihanyi. Thus, we reject claim 24 under 35 U.S.C. § 103(a) as unpatentable over Das in view of Nakamura, and further in view of Tihanyi. CONCLUSION Upon consideration of the record, and for the reasons given above and in the Appeal and Reply Briefs, each of the Examiner’s rejections of claims 1, 3, 8, and 22 under 35 U.S.C. § 102(b) as anticipated by Tihanyi, claims 2 Appeal 2019-003404 Application 15/344,735 16 and 4–7 under 35 U.S.C. § 103(a) as unpatentable over Tihanyi in view of Deboy or Nakamura, and claims 9, 11–17, 19–21, 23, and 24, is reversed. However, we institute new grounds of rejection under 35 U.S.C. §103(a) of claims 1, 3–5, 7, 8, and 22 as unpatentable over Nakamura in view of Tihanyi; claims 2 and 6 as unpatentable over Nakamura and Tihanyi, further in view of Deboy; claims 9, 11, 12, 14–17, 19, 21, and 23 as unpatentable over Das in view of Nakamura; and claims 13, 20, and 24 as unpatentable over Das and Nakamura, further in view of Kinzer, Deboy, or Tihanyi. DECISION SUMMARY In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed New Ground 1, 3, 8, 22 102(b) Tihanyi 1, 3, 8, 22 2, 6 103(a) Tihanyi, Deboy 2, 6 4, 5, 7 103(a) Tihanyi, Nakamura 4, 5, 7 9, 11, 12, 14–16, 23, 24 103(a) Das, Tihanyi 9, 11, 12, 14–16, 23, 24 13 103(a) Das, Tihanyi, Kinzer 13 17, 19, 21 103(a) Das, Tihanyi, Nakamura 17, 19, 21 20 103(a) Das, Tihanyi, Deboy 20 1, 3–5, 7, 8, 22 103(a) Nakamura, Tihanyi 1, 3–5, 7, 8, 22 2, 6 103(a) Nakamura, Tihanyi 2, 6 9, 11, 12, 14–17, 19, 21, 23 103(a) Das, Nakamura 9, 11, 12, 14–17, 19, 21, 23 Appeal 2019-003404 Application 15/344,735 17 13, 20, 24 103(a) Das, Nakamura, Kinzer, Deboy, Tihanyi 13, 20, 24 Overall Outcome 1–9, 11– 17, 19–24 1–9, 11– 17, 19–24 TIME PERIOD FOR RESPONSE This decision contains a new ground of rejection pursuant to 37 CFR § 41.50(b) (effective September 13, 2004, 69 Fed. Reg. 49960 (August 12, 2004), 1286 Off. Gaz. Pat. Office 21 (September 7, 2004)). 37 CFR § 41.50(b) provides “[a] new ground of rejection pursuant to this paragraph shall not be considered final for judicial review.” 37 CFR § 41.50(b) also provides that Appellant, WITHIN TWO MONTHS FROM THE DATE OF THE DECISION, must exercise one of the following two options with respect to the new ground of rejection to avoid termination of the appeal as to the rejected claims: (1) Reopen prosecution. Submit an appropriate amendment of the claims so rejected or new Evidence relating to the claims so rejected, or both, and have the matter reconsidered by the examiner, in which event the proceeding will be remanded to the examiner. . . . (2) Request rehearing. Request that the proceeding be reheard under § 41.52 by the Board upon the same Record. . . . Further guidance on responding to a new ground of rejection can be found in the Manual of Patent Examining Procedure § 1214.01. REVERSED 37 C.F.R. § 41.50(b) Copy with citationCopy as parenthetical citation