Cheng-Po Chen et al.Download PDFPatent Trials and Appeals BoardOct 24, 201913965437 - (D) (P.T.A.B. Oct. 24, 2019) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 13/965,437 08/13/2013 Cheng-Po Chen 246528-US-2 (GERD:1585) 8033 41838 7590 10/24/2019 GENERAL ELECTRIC COMPANY (Global Research) C/O FLETCHER YODER P. O. BOX 692289 HOUSTON, TX 77269-2289 EXAMINER STOWE, SCOTT C ART UNIT PAPER NUMBER 2829 NOTIFICATION DATE DELIVERY MODE 10/24/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): docket@fyiplaw.com rariden@fyiplaw.com robinson@fyiplaw.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte CHENG-PO CHEN, EMAD ANDARAWIS ANDARAWIS, VINAYAK TILAK, and ZACHARY MATTHEW STUM ____________ Appeal 2019-001145 Application 13/965,437 Technology Center 2800 ____________ Before MARK NAGUMO, MICHAEL P. COLAIANNI, and GEORGE C. BEST, Administrative Patent Judges. BEST, Administrative Patent Judge. DECISION ON APPEAL Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 1–5, 9–15, and 18–23 of Application 13/965,437. Final Act. (October 24, 2016). We have jurisdiction under 35 U.S.C. § 6. For the reasons set forth below, we affirm. 1 We use the word “Appellant” to refer to “Applicant” as defined in 37 C.F.R. § 1.42. Appellant identifies General Electric Co. as the real party in interest. Appeal Br. 3. Appeal 2019-001145 Application 13/965,437 2 BACKGROUND The ’437 Application describes methods and apparatus for making integrated circuits that facilitate electrical isolation of components on a semiconductor wafer. Spec. ¶ 3. The resulting integrated circuits are said to be especially useful in high temperature environments. Id. Independent claims 1 and 13 are representative of the ’437 Application’s claims and are reproduced below from the Claims Appendix of the Appeal Brief. 1. An integrated circuit, comprising: a substrate comprising a first semiconducting layer and a second semiconducting layer formed over a substantial portion of the first semiconducting layer to define the substrate, wherein the second semiconducting layer comprises an epitaxial layer; a first transistor embedded within the substrate and a corresponding first body terminal, wherein the first transistor is reverse biased at a first body voltage level; and a second transistor embedded within the substrate and a corresponding second body terminal electrically isolated respectively from the first transistor and the corresponding first body terminal via one or more deep trench isolation barriers, wherein the second transistor is reverse biased at a second body voltage level different from the first body voltage level, and further wherein the first transistor is electrically connected to the second transistor, such that the first and second transistors operate to interact with each other while the respective body voltage levels are different from each other and are changing independently of each other during operation of the integrated circuit, wherein the one or more deep trench isolation barriers extend completely through the second semiconducting Appeal 2019-001145 Application 13/965,437 3 layer and further a distance into the first semiconducting layer, further wherein each of the first transistor and the second transistor is isolated in a corresponding device island. Appeal Br. 18 (emphasis, some paragraphing, and indentation added). 13. An integrated circuit, comprising: a substrate comprising a first semiconducting layer and a second semiconducting layer formed over a substantial portion of the first semiconducting layer to define the substrate, wherein the second semiconducting layer comprises an epitaxial layer; a plurality of transistors embedded within the substrate; and a corresponding body terminal associated with each transistor, wherein one or more isolation barriers substantially eliminate electrical connectivity between the body terminals, and further wherein the body terminal of a first transistor of the plurality of transistors is biased to a first voltage level, the body terminal of a second transistor of the plurality of transistors is biased to a second voltage level different from the first voltage level, and the first transistor is electrically connected to the second transistor, such that the first and second transistors operate to interact with each other while their respective body voltage levels are different from each other and are changing independently of each other during operation of the integrated circuit, and while the substantial elimination of electrical connectivity between the body terminals is maintained during simultaneous operation of the first and second transistors and further wherein the one or more isolation barriers comprise one or more deep trench isolation barriers, and the one or more deep trench isolation barriers extend completely through the second semiconducting layer and further a distance into the first semiconducting layer, Appeal 2019-001145 Application 13/965,437 4 further wherein each of the first transistor and the second transistor is isolated in a corresponding device island. Id. at 19–20 (emphasis, some paragraphing, and indentation added). REJECTIONS On appeal, the Examiner maintains the following rejections: 1. Claims 1–5, 9–15, and 18–20 are rejected under 35 U.S.C. § 102(a)(1) as anticipated by Jimbo.2 Final Act. 3–9. 2. Claim 21 is rejected under 35 U.S.C. § 103 as unpatentable over Jimbo. Final Act. 9–10. 3. Claims 22 and 23 are rejected under 35 U.S.C. § 103 as unpatentable over the combination of Jimbo and Liu.3 Final Act. 10–11. DISCUSSION A. § 102(a)(1) Rejection as Anticipated by Jimbo. Appellant only presents substantive arguments for reversal of the rejection of independent claims 1 and 13. See Appeal Br. 8–16. Dependent claims 2–5, 9–12, 14, 15, and 18–20 are alleged to be patentable by virtue of their dependence from these claims. Id. at 15–16. We, therefore, choose independent claims 1 and 13 as representative of the group of claims subject to this ground of rejection. 37 C.F.R. § 41.37(c)(1)(iv). Each dependent claim will stand or fall with its parent independent claim. 2 US 6,642,583 B2, issued November 4, 2003. 3 US 2011/0260245 A1, published October 27, 2011. Appeal 2019-001145 Application 13/965,437 5 Appellant argues that the rejection of independent claims 1 and 13 should be reversed on the basis of a limitation that appears in both of these claims: “wherein each of the first transistor and the second transistor is isolated in a corresponding device island.” See Appeal Br. 8–15. In particular, Appellant argues that Jimbo does not describe this claim limitation. Id. In rejecting claims 1 and 13, the Examiner found that Jimbo’s Figure 6 discloses apparatus satisfying this limitation. Final Act. 3–4. For ease of reference, we reproduce Figure 6 below. Jimbo’s Figure 6 is a cross-sectional view of a high voltage driver integrated circuit. Jimbo 5:20–23. The Examiner found that Figure 6 depicts trench isolation barrier 51 as separating a first transistor (the N-MOS transistor from section 21) from a second transistor (the N-MOS transistor from section 22). Final Act. 3. According to the Examiner, the first and second transistors are isolated on corresponding device islands because “each of the first and second transistor Appeal 2019-001145 Application 13/965,437 6 is on an opposing side of the isolation trench [and] thus is disposed in a corresponding device island.” Id. at 4 (referring to Jimbo, Fig. 6). Appellant argues that Jimbo does not describe the claimed isolation of the first and second transistors in corresponding device islands. Appeal Br. 10–15 (citing Jimbo 9:31–47; Spec. ¶¶ 37, 38, 49, 56, 59, Fig. 2). Appellant concludes: Appellant respectfully submits that the trench structure of Jimbo is structurally completely different from the device islands of the current Application and they cannot be scientifically equated with each other. Further, [while the] regions are separated from each other by the isolation barriers, each of the first transistor and the second transistor is not isolated in a corresponding device island, as is claimed in previously presented versions of independent claims 1 and 13. Id. at 15. Appellant’s arguments are not persuasive. Appellant’s block quotation of six complete paragraphs of the ’437 Application’s Specification, with emphasis only, does not point out where the Examiner erred in finding that Jimbo’s isolation trench 51 electrically separates and, therefore, isolates the first and second transistors disclosed in Jimbo. Nor does Appellant explain how Jimbo’s trench structure is structurally different from the device islands described in the ’437 Application. At best, this is an invitation to review these sections virtually de novo. We decline this invitation as our primary function is review, not examination de novo. In sum, Appellant has not met its burden of showing the existence of reversible error. For the reasons set forth above, we affirm the rejection of independent claims 1 and 13. We, therefore, also affirm the rejection of dependent claims 2–5, 9–12, 14, 15, and 18–20. Appeal 2019-001145 Application 13/965,437 7 B. § 103 Rejection as Unpatentable over Jimbo. Appellant argues that the rejection of claim 21 as unpatentable over Jimbo should be reversed because “Jimbo does not teach or suggest the cited claim element of independent claims 1 and 13. Therefore independent claims 1 and 13 are patentable over Jimbo. For similar reasons dependent claim[] 21 . . . which depend from independent claim[] 1 . . . [is] patentable over Jimbo.” Appeal Br. 16. As discussed above, we have determined that the Examiner did not reversibly err in finding that Jimbo describes each element of independent claim 1. We, therefore, affirm the rejection of claim 21 as unpatentable over Jimbo. C. § 103 Rejection as Unpatentable over the Combination of Jimbo and Liu. Appellant argues that the rejection of claims 22 and 23 as unpatentable over the combination of Jimbo and Liu should be reversed because Jimbo does not teach or suggest the cited claim element of independent claims 1 and 13. Therefore independent claims 1 and 13 are patentable over Jimbo. For similar reasons dependent claims . . . 22 and 23 which depend from independent claims 1 or 13 are patentable over Jimbo. Further, the other secondary reference Liu was cited with respect to various aspects of [the pending] claims but also does not appear to address the deficiencies with respect to independent claims 1 and 13. Thus, Appellant also submits that Appeal 2019-001145 Application 13/965,437 8 claims . . . are not taught or suggested by the applied art and each of these claims is patentable. Appeal Br. 16. As discussed above, we have determined that the Examiner did not reversibly err in finding that Jimbo describes each element of the independent claims. We, therefore, affirm the rejection of claims 22 and 23 as unpatentable over the combination of Jimbo and Liu. CONCLUSION In summary: Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1–5, 9–15, 18–20 102(a)(1) Jimbo 1–5, 9–15, 18–20 21 103 Jimbo 21 22, 23 103 Jimbo, Liu 22, 23 Overall Outcome 1–5, 9–15, 18–23 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). AFFIRMED Copy with citationCopy as parenthetical citation