Bigtera Limited

Patent Trials and Appeals Board

Aug 12, 2021

2020003212 (P.T.A.B. Aug. 12, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/184,801 02/20/2014 Kuan-Kai Chiu 250229-1010 3971
109673 7590 08/12/2021
McClure, Qualey & Rodack, LLP
280 Interstate North Circle SE
Suite 550
Atlanta, GA 30339
EXAMINER
BIRKHIMER, CHRISTOPHER D
ART UNIT PAPER NUMBER
2136
NOTIFICATION DATE DELIVERY MODE
08/12/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
callie.reynolds@mqrlaw.com
dan.mcclure@mqrlaw.com
uspatents@mqrlaw.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
_______________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
_______________

Ex parte KUAN-KAI CHIU and TSUNG-LIN YU
_______________

Appeal 2020-003212
Application 14/184,801
Technology Center 2100
_______________

Before JEREMY J. CURCURI, NATHAN A. ENGELS, and
JAMES W. DEJMEK, Administrative Patent Judges.

DEJMEK, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from a Final Rejection of
claims 1, 5, 6, and 10. Appellant has canceled claims 2–4 and 7–9. See
Appeal Br. A-1–A-3. We have jurisdiction over the remaining pending
claims under 35 U.S.C. § 6(b).
We affirm in part.

1 Throughout this Decision, we use the word “Appellant” to refer to
“applicant” as defined in 37 C.F.R. § 1.42 (2019). Appellant identifies
BIGTERA LIMITED as the real party in interest. Appeal Br. 2.
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STATEMENT OF THE CASE
Introduction
Appellant’s disclosed and claimed invention generally relates to a
storage system and access control method that “can allocate[] I/O operation
for virtual machines averagely.” Spec. 1:9–10. In a disclosed embodiment,
a storage system may comprise a plurality of disk files, which correspond to
a plurality of virtual disks. Spec. 4:20–5:1, Fig. 1. In addition, the storage
system further comprises an I/O interface and processor unit. Spec. 4:17–
18, Fig. 1. According to the Specification, when a hypervisor makes an I/O
request to the storage system (e.g., to access a first disk file), the processor
unit of the storage system reads a first quality of service (“QoS”) data
recorded with the first disk file and determines a first delay period based on
the QoS data. Spec. 5:3–11. The I/O response from the storage subsystem
is not sent to the hypervisor until the first delay period has expired.
Spec. 5:11–13. According to the Specification, “the QoS of I/O operations
of the virtual disks can be controlled fairly by adjusting the QoS setting of
the disk files.” Spec. 10:17–18.
Claim 1 is exemplary of the subject matter on appeal and is
reproduced below with the disputed limitations emphasized in italics:
1. An access control method for use in a storage system, the
storage system connecting to at least one hypervisor server and
storing a plurality of disk files which correspond to a plurality of
virtual disks respectively, the disk files being stored as a file
system in a storage unit of the storage system, the access control
method comprising:
receiving, at the storage system, a first I/O request from
the at least one hypervisor, wherein the first I/O request is
configured to access a first disk file of the disk files;
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operating, by the storage system, a first I/O operation of a
first virtual disk of the virtual disks according to the first I/O
request;
reading, by the storage system, a quality of service (QoS)
data of the first disk file, wherein the QoS data comprises an
input output per second (IOPS) information and an I/O
bandwidth information, wherein the QoS data is recorded with
the first disk file or recorded with a dictionary of the first disk
file, and the first disk file or the dictionary of the disk file is
stored in the storage unit of the storage system;
determining, by the storage system, a first delay period
according to the IOPS information of the first disk file and the
I/O bandwidth information of the first disk file; and
suspending a subsequent I/O operation of the first disk file
for a time duration associated with the first delay period to
balance an I/O QoS of the first virtual disk by transmitting, by
the storage system, a first I/O response to the at least one
hypervisor only after expiration of the first delay period has
passed.

The Examiner’s Rejections
1. Claims 1, 5, 6, and 10 stand rejected under 35 U.S.C. § 112(a)
for failing to comply with the written description requirement. Final Act. 5–
6.
2. Claims 6 and 10 stand rejected under 35 U.S.C. § 112(b) as
being indefinite. Final Act. 7.
3. Claims 1, 5, 6, and 10 stand rejected under 35 U.S.C.
§ 102(a)(1) as being anticipated by Muppirala et al. (US 2011/0302287 A1;
Dec. 8, 2011) (“Muppirala”). Final Act. 7–20.

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ANALYSIS2
Rejections under 35 U.S.C. § 112
The Examiner finds a lack of written description support for
“transmitting . . . a first I/O response to the at least one hypervisor only after
expiration of the first delay period has passed,” as recited in independent
claim 1 and commensurately recited in independent claim 6. Final Act. 5–6.
In addition, the Examiner finds the terms “storage circuit” and “processor
circuit,” as recited in independent claim 6, lack written description support
and are indefinite. Final Act. 6–7.

a. “storage circuit” and “processor circuit”
We begin our analysis with a brief review of the prosecution history
related to these disputed claim terms. As an initial matter, we note that, as
originally drafted, the claims recited a “storage unit” and “processing unit.”
See, e.g., Spec. 13–14 (claim 6). In a Non-Final Office Action (“Non-Final
Act.”), mailed November 7, 2018, the Examiner determined the terms
“storage unit” and “processing unit” invoked the provisions of 35 U.S.C.
§ 112(f). Non-Final Act. 3–6. Further, the Examiner determined the
Specification did not set forth a corresponding structure for performing the
recited functions for the “storage unit” and processing unit,” respectively.
Non-Final Act. 6–9. As such, the Examiner rejected the claims reciting a
“storage unit” and “processing unit” under 35 U.S.C. § 112(b). Non-Final

2 Throughout this Decision, we have considered the Appeal Brief, filed
December 19, 2019 (“Appeal Br.”); the Reply Brief, filed March 26, 2020
(“Reply Br.”); the Examiner’s Answer, mailed February 6, 2020 (“Ans.”);
and the Final Office Action, mailed May 22, 2019 (“Final Act.”), from
which this Appeal is taken.
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Act. 6–9. In response, Appellant amended the claim language to recite a
“storage circuit” and “processing circuit,” asserting that the term “circuit”
provides sufficient structure and does not, therefore, trigger the provisions of
35 U.S.C. § 112(f). Amdt. 3–4, 6–7 (filed May 7, 2019).
In the Appeal Brief, Appellant reiterates that “it is well settled that the
term ‘circuit’ is structural.” Appeal Br. 9 (citing MPEP § 2181). Appellant
argues that it is of no moment that that the Specification does not mention
the term circuit because one of ordinary skill in the art would understand the
storage unit and processor unit to each comprise a circuit. Appeal Br. 7–8.
Moreover, Appellant argues that “[t]here is no meaningful/patentable
difference between labeling a block (in the specification) with ‘storage unit’
or ‘processing unit’ versus ‘storage circuit’ or ‘processing circuit.’” Appeal
Br. 9. As such, Appellant argues the terms are not indefinite under
35 U.S.C. § 112(b). Appeal Br. 9.
In Massachusetts Institute of Technology and Electronics for Imaging,
Inc. v. Abacus Software, 462 F.3d 1344, 1355–56 (Fed. Cir. 2006), our
reviewing court “concluded that the term ‘circuit,’ combined with a
description of the function of the circuit, connoted sufficient structure to one
of ordinary skill in the art to avoid [35 U.S.C. § 112(f)] treatment.” We do
not read Abacus to stand for the proposition that mere use of the term
“circuit” serves as a talisman against triggering the provisions of 35 U.S.C.
§ 112(f). If that were the case, a clever draftsperson could simply amend
claim language from a term that invokes 35 U.S.C. § 112(f) to recite a
“circuit” that performs the same function. Additionally, Abacus does not
stand for always finding sufficient structure for the recited circuit in the
recited function being performed. Such an interpretation would similarly
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eviscerate meaningful application of 35 U.S.C. § 112(f). Recognizing these
concerns, our reviewing court has explained that “not just any adjectival
qualification or functional language” coupled with a recited “circuit” will
provide the requisite structure to avoid triggering 35 U.S.C. § 112(f). Power
Integrations, Inc. v. Fairchild Semiconductor Int’l, Inc., 711 F.3d 1348,
1364–65 (Fed. Cir. 2013); see also Intelligent Automation Design, LLC v.
Zimmer Biomet CMF & Thoracic, LLC, 799 F. App’x 847, 850–51 (Fed.
Cir. 2020) (unpublished). Rather, “[t]he proper inquiry is whether the claim
limitation itself, when read in light of the specification, connotes to the
ordinarily skilled artisan sufficiently definite structure for performing the
identified functions.” Power Integrations, 711 F.3d at 1365 (citing Apex
Inc. v. Raritan Computer, Inc., 325 F.3d 1364, 1373 (Fed. Cir. 2003)). In
Williamson v. Citrix Online, LLC, 792 F.3d 1339, 1349 (Fed. Cir. 2015), our
reviewing court reiterated that “[t]he standard [(for whether the provisions of
35 U.S.C. § 112(f) apply)] is whether the words of the claim are understood
by persons of ordinary skill in the art to have a sufficiently definite meaning
as the name for structure.” That is, if the recited term would convey a
sufficiently definite structure to one of ordinary skill in the art, the
provisions of 35 U.S.C. § 112(f) will not be triggered.
We conclude that a “storage circuit, being configured to store a
plurality of disk files” conveys a sufficiently definite structure to one of
ordinary skill in the art. As such, 35 U.S.C. § 112(f) is not invoked.
Moreover, we do not find a “storage circuit” to be indefinite under 35 U.S.C.
§ 112(b). See Orthokinetics, Inc. v. Safety Travel Chairs, Inc., 806 F.2d
1565, 1576 (Fed. Cir. 1986) (explaining that the test for definiteness under
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35 U.S.C. § 112(b) is whether “those skilled in the art would understand
what is claimed when the claim is read in light of the specification”).
The “processing circuit” is recited as being electrically connected to
the storage circuit and the I/O interface and is configured “to operate a first
I/O operation[,] . . . to determine a first delay period[,] . . . and to suspend a
subsequent I/O operation.” See claim 6.
We agree with Appellant (see Appeal Br. 9) that in this case there is
no patentable distinction between reciting the term “processing unit” or
“processing circuit.” Both invoke the provisions of 35 U.S.C. § 112(f).
Although the ordinarily skilled artisan may understand that a
“processing circuit” (or even a “processing unit”) may be “some kind of
processor device,” as suggested by Appellant (see Appeal Br. 6), “a
[processor device] can serve as structure for a computer-implemented
function only where the claimed function is ‘coextensive’ with a [processor
device] itself.” EON Corp. IP Holdings LLC v. AT&T Mobility LLC, 785
F.3d 616, 622 (Fed. Cir. 2015) (citing In re Katz Interactive Call Processing
Patent Litig., 639 F.3d 1303, 1316 (Fed. Cir. 2011)). Examples of
coextensive functions include receiving data, storing data, and processing
data. EON, 785 F.3d at 622. “A microprocessor or general purpose
computer lends sufficient structure only to basic functions [(i.e., the
identified coextensive functions)] of a microprocessor. All other computer-
implemented functions require disclosure of an algorithm.” EON, 785 F.3d
at 623. A structure described in the Specification qualifies as a
corresponding structure “only if the specification or prosecution history
clearly links or associates that structure to the function recited in the claim.”
B. Braun Med., Inc. v. Abbott Labs., 124 F.3d 1419, 1424 (Fed. Cir. 1997).
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Mindful of the guidance set forth in EON, we find that Appellant has
not disclosed an algorithm to perform the recited function of determining a
first delay period. To the contrary, the Specification expressly states the
processing unit reads QoS data from a disk file and determines a first delay
period, but that determination of a first delay period is “not shown.” See
Spec. 6:13; see also Spec. 5:11. Accordingly, we conclude that a “processor
circuit” invokes 35 U.S.C. § 112(f) and is indefinite under 35 U.S.C.
§ 112(b) for lack of a corresponding structure described in the Specification.
In addition, we note that MPEP § 2163(II)(A)(3)(a) states that “when a claim
is rejected as indefinite under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112,
second paragraph, because there is no corresponding structure, materials, or
acts, or an inadequate disclosure of corresponding structure, materials, or
acts, for a means- (or step-) plus-function claim limitation, then the claim
must also be rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first
paragraph, for lack of an adequate written description.”
Appellant also argues the rejection under 35 U.S.C. § 112(a) should
be reversed because “the inquiry is what the specification teaches to one of
ordinary skill in the art.” Reply Br. 3. Applying this test, Appellant asserts
that a “storage circuit” and “processing circuit” are “within the teachings of
the specification.” Appeal Br. 7.
As an initial matter, contrary to Appellant’s assertion, the correct
standard for satisfying the written description requirement is that the
disclosure must reasonably convey to skilled artisans that Appellant
possessed the claimed invention as of the filing date. See Ariad Pharms.,
Inc. v. Eli Lilly & Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en banc).
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Specifically, the description must “clearly allow persons of ordinary skill in
the art to recognize that [the inventor] invented what is claimed” and
the test requires an objective inquiry into the four corners of the
specification from the perspective of a person of ordinary skill in
the art. Based on that inquiry, the specification must describe an
invention understandable to that skilled artisan and show that the
inventor actually invented the invention claimed.
Ariad Pharms., Inc., 598 F.3d at 1351 (internal quotations and citations
omitted). Moreover, “it is ‘not a question of whether one skilled in the art
might be able to construct the patentee’s device from the teachings of the
disclosure. . . . Rather, it is a question whether the application necessarily
discloses that particular device.’” Lockwood v. Am. Airlines, Inc., 107 F.3d
1565, 1572 (Fed. Cir. 1997) (quoting Jepson v. Coleman, 314 F.2d 533, 536
(CCPA 1963)) (emphasis added).
As discussed above, from the perspective of a person of ordinary skill
in the art, we find adequate support for the recited storage circuit. However,
absent an algorithm (or other suitable disclosure) for a processor circuit to
perform the function of determining a first delay period based on the
retrieved QoS data, we find the processor circuit fails to find the requisite
written disclosure support in the Specification.
For the reasons discussed supra, we sustain the Examiner’s rejection
of independent claim 6 under 35 U.S.C. § 112(b) for lack of a corresponding
structure for a processor circuit to determine a first delay period and
35 U.S.C. § 112(a) for lack of the requisite written description support for a
processor circuit to determine a first delay period. We also sustain the
Examiner’s rejection of claim 10, which depends therefrom, under 35 U.S.C.
§ 112(a), § 112(b).

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b. “transmitting . . . a first I/O response to the at least one hypervisor
only after expiration of the first delay period has passed”
Appellant argues the Specification provides the requisite written
description support for the claim limitation of “transmitting . . . a first I/O
response to the at least one hypervisor only after expiration of the first delay
period has passed.” Appeal Br. 4–5. In particular, Appellant directs our
attention to page 6, lines 13 through 15, which expressly states: “Then, the
I/O interface 231 of the storage system 23 then transmits a first I/O response
234 to the hypervisor 21 after the first delay period passes.” Appeal Br. 4.
We agree with Appellant that the Specification describes the temporal
aspect of not transmitting the I/O response until after the first delay period
has passed. Accordingly, we do not sustain the Examiner’s rejection under
35 U.S.C. § 112(a) on this basis.

Rejection under 35 U.S.C. § 102(a)(1)
Appellant disputes the Examiner’s finding that Muppirala discloses
suspending the transmission of an I/O response until after a determined first
delay period has expired. Appeal Br. 9–15; Reply Br. 4. More specifically,
Appellant argues Muppirala does not determine a delay period based on QoS
parameters and does not suspend an I/O operation for the duration of the
determined time period. Appeal Br. 9–15. Instead, Appellant asserts
Muppirala describes a QoS parameter may correspond to a workload
identification tag (“WIT”) and that the QoS parameter may be associated
with various characteristics, such as throughput, bandwidth, transit delay,
jitter, loss ratio, and error rate. Appeal Br. 13. Appellant further asserts the
Muppirala describes that the QoS parameters “are used for setting purposes
[(i.e., determining a data rate)] directly and independently but are not used
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for determining any delay period of suspending I/O operation.” Appeal
Br. 14.
In response, the Examiner finds Muppirala describes the use of QoS
delay parameters to issue requests. Ans. 7. Moreover, the Examiner
explains “[t]here is always some unit of time/delay it takes for a request to
be sent from a source location to a destination location[;]. . . . [t]here is a
delay period from the time the initial request is generated and a response to
the request is generated.” Ans. 7–8.
As an initial matter, to the extent the Examiner is equating the claimed
first delay period to be the propagation delay associated with receiving and
responding to a request, we find such an interpretation to be unreasonably
broad and inconsistent with the Specification.
Regarding the disclosure of Muppirala, Muppirala generally relates to
providing QoS control to myriad sections of a network environment. See
Muppirala, Abstr. More particularly, Muppirala describes “in a network
environment where multiple hosts have access to a common target device,
various factors, such as bandwidth and latency, are controlled to provide an
expected Quality of Service (QoS).” Muppirala ¶ 2. Muppirala describes it
is known to provide QoS control techniques at a single point of control of a
network environment. Muppirala ¶ 9. Muppirala proposes an approach
termed end-to-end QoS control that provides QoS control at a plurality of
sections within the network environment to address potential conflicts, or
sub-optimal performance, when two applications are trying to access a
common target device at the same time. See Muppirala ¶¶ 9–12.
In a disclosed embodiment, Muppirala describes using a workload
identification tag (“WIT”), associated with a workload or application
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command, for QoS control. Muppirala ¶ 13. The WIT is a global tag across
the network environment. Muppirala ¶ 46. A central QoS controller may
use information stored in the WIT for QoS control and to “schedule
processing times for various application commands.” Muppirala ¶¶ 61, 71,
Fig. 1.
Based on our review of Muppirala, we do not find Muppirala
discloses the scheduling of application commands further includes
determining a delay period associated with the QoS data and suspending an
I/O response until the determined time period has expired.
For the reasons discussed supra, we do not sustain the Examiner’s
rejection under 35 U.S.C. § 102(a)(1) of independent claim 1. For similar
reasons, we do not sustain the Examiner’s rejection under 35 U.S.C.
§ 102(a)(1) of independent claim 6, which recites similar limitations. In
addition, we do not sustain the Examiner’s rejection under 35 U.S.C.
§ 102(a)(1) of claims 5 and 10, which depend therefrom.

CONCLUSION
We sustain the Examiner’s decision rejecting claims 6 and 10 under
35 U.S.C. § 112(b) for lack of a corresponding structure (i.e., a processing
circuit configured to determine a first delay period) disclosed in the
Specification.
We sustain the Examiner’s decision rejecting claims 6 and 10 under
35 U.S.C. § 112(a) for lack of written description for a processing circuit
configured to determine a first delay period.
We do not sustain the Examiner’s decision rejecting claims 1, 5, 6,
and 10 under 35 U.S.C. § 112(a) for lack of written description related to
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suspending transmission of an I/O response until after a determined first
delay period has passed.
We do not sustain the Examiner’s decision rejecting claims 1, 5, 6,
and 10 under 35 U.S.C. § 102(a)(1).

DECISION SUMMARY
Claim(s)
Rejected
35 U.S.C. § Reference(s)/Basis Affirmed Reversed
6, 10 112(f) /
112(b)
Indefiniteness 6, 10
1, 5, 6, 10 112(a) Written Description 6, 10 1, 5
1, 5, 6, 10 102(a)(1) Muppirala 1, 5, 6, 10
Overall
Outcome
6, 10 1, 5

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See
37 C.F.R. § 41.50(f).

AFFIRMED IN PART