Ashot Melik-MartirosianDownload PDFPatent Trials and Appeals BoardSep 13, 201915207414 - (D) (P.T.A.B. Sep. 13, 2019) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/207,414 07/11/2016 Ashot MELIK-MARTIROSIAN 122203-5250 2596 128298 7590 09/13/2019 Morgan, Lewis & Bockius LLP (WD/HGST) 600 Anton Boulevard, Suite 1800 Costa Mesa, CA 92626 EXAMINER HUANG, MIN ART UNIT PAPER NUMBER 2827 NOTIFICATION DATE DELIVERY MODE 09/13/2019 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): OCIPDocketing@morganlewis.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE BEFORE THE PATENT TRIAL AND APPEAL BOARD Ex parte ASHOT MELIK-MARTIROSIAN Appeal 2018-007258 Application 15/207,414 Technology Center 2800 Before CATHERINE Q. TIMM, LINDA M. GAUDETTE, and MERRELL C. CASHION, JR., Administrative Patent Judges. TIMM, Administrative Patent Judge. DECISION ON APPEAL STATEMENT OF THE CASE Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s decision to reject claims 21, 22, 30–32, and 40 under 35 U.S.C. § 103(a) as obvious over Jeong2 in view of Yoo.3 The Examiner also rejects “[c]laim 23/24/25/28/29 or 33/34/35/38/39” and “[c]laim 26/27 or 36/37” on the ground of nonstatutory double patenting as being unpatentable over 1 We use the word “Appellant” to refer to “Applicant” as defined in 37 C.F.R. § 1.42(a). Appellant identifies the real party in interest as HGST Technologies Santa Ana, Inc. Appeal Br. 3. 2 Jeong et al., US 2010/0124122 A1, published May 20, 2010. 3 Yoo et al., US 2010/0265764 A1, published Oct. 21, 2010. Appeal 2018-007258 Application 15/207,414 2 claim 1 of US 8,737,141 B2. Final Act. 5 (emphasis omitted). Appellant does not address the nonstatutory double patenting rejection in the briefs. We have jurisdiction under 35 U.S.C. § 6(b). We AFFIRM-IN-PART. CLAIMED SUBJECT MATTER According to the Specification, the invention relates generally to memory devices and, in particular, to a system and process that extends the life span of a multi-level cell flash memory. Spec. ¶ 2. Claim 21, reproduced below, is illustrative of the claimed subject matter: 21. A method, comprising: performing a memory operation on a memory device based on one or more stored parameters, the memory operation comprising an application of a number of step pulses to one or more memory cells of the memory device; determining that an operation duration of the performed memory operation satisfies a predetermined threshold duration for the memory operation; and in response to the operation duration satisfying the predetermined threshold duration, adjusting at least one of the stored parameters for use in a subsequent performance of the memory operation. Appeal Br. 12 (claims appendix). Claim 31, the other independent claim, is directed to a system that includes a controller that is operable to carry out the method of claim 21. Appeal 2018-007258 Application 15/207,414 3 OPINION Obviousness In rejecting claims 21, 22, 30–32, and 40 as obvious over Jeong in view of Yoo, the Examiner concedes that Jeong uses the number of program/erase (P/E) cycles, and not an operation duration, as the threshold for adjusting stored parameters. Final Act. 2. The Examiner, however, finds that Yoo teaches that P/E cycles and operation time are interchangeable for determining memory device characteristics and concludes that it would have been obvious to the ordinary artisan to use operation time in the method of Jeong. Final Act. 3 (citing Yoo ¶ 39). We, however, agree with Appellant that the Examiner’s rejection is based on a faulty claim interpretation. Yoo does not teach “determining that an operation duration of the performed memory operation satisfies a predetermined threshold duration for the memory operation.” Claims 21 and 31 (emphasis added). Yoo teaches that “threshold voltages of memory cells may be shifted (e.g., decreased and/or increased) due to deterioration of an oxide layer caused by time elapse.” Yoo ¶ 39. In other words, as the memory device ages, the oxide layer deteriorates, which causes the threshold voltage of the memory cells to be shifted. In order to encompass the aging aspect taught by Yoo, the Examiner interprets “operation duration” as “time elapsed since the device started operation.” Ans. 3. Appellant counters that the phrase means “a duration of an operation, performed on a memory, that is measured by time.” Reply Br. 3. We agree with Appellant that the Examiner has interpreted the claim limitation “operation duration” in an unreasonably broad manner that Appeal 2018-007258 Application 15/207,414 4 divorces the language from the phrase “of the performed memory operation.” Reply Br. 3. To determine the correct interpretation, we first consider the language as it occurs in the claims. Claims 21 and 31 recite “an operation duration of the performed memory operation.” Claims 21 and 31 (emphasis added). Thus, it is the performed memory operation that has an operation duration. The phrase “the performed memory operation” takes its antecedent basis from the step of “performing a memory operation on a memory device based on one or more stored parameters.” The claims further limit the memory operation. The memory operation that is performed, according to the claims, comprises “an application of a number of step pulses to one or more memory cells of the memory device.” Claims 21 and 31. Next, we consider whatever enlightenment as to the meaning of “memory operation” and “operation duration” that may be afforded by the written description contained in the Specification. In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997) (“[A]s an initial matter, the PTO applies to the verbiage of the proposed claims the broadest reasonable meaning of the words in their ordinary usage as they would be understood by one of ordinary skill in the art, taking into account whatever enlightenment by way of definitions or otherwise that may be afforded by the written description contained in the applicant’s specification.”). As pointed out by the Examiner, the Specification does not define “duration.” Ans. 3. Nor does the Specification use the terminology “operation duration.” The Specification, however, discusses a memory operation and refers to programming and erase operations in the context of applying step pulses. The memory operation that uses a number of step Appeal 2018-007258 Application 15/207,414 5 pulses is an operation in which pulses are applied to program and erase the memory cells. Spec. ¶¶ 5–7; see also Spec. ¶ 35 (discussing programming memory cells “using an Incremental Step Pulse Program (ISSP)” and erasing memory cells “using a similar Incremental Step Pulse Erase (ISPE)”). Thus, the memory operations that have an operation duration are the programming and erasing operations. Hence, we agree with Appellant that “operation duration” refers to the duration of time of a memory operation. Reply Br. 4. The Specification discloses those duration operations as the time required to program the memory cells and the time required to erase the memory cells. Yoo’s disclosure of “deterioration of an oxide layer caused by time elapse” is not an “operation duration of the performed memory operation” as it is not a duration of a performed memory operation, i.e., it is not a duration of programming time or erase time. Appellant has identified an error in the Examiner’s claim interpretation that resulted in a reversible error in the Examiner’s finding that Yoo teaches the required “operation duration of the performed memory operation.” Thus, we do not sustain the Examiner’s obviousness rejection. Obviousness Double Patenting The Examiner also rejects “[c]laim 23/24/25/28/29 or 33/34/35/38/39” and “[c]laim 26/27 or 36/37” on the ground of nonstatutory double patenting as being unpatentable over claim 1 of US 8,737,141 B2. Final Act. 5 (emphasis omitted). Appellant does not address this rejection in the briefs. Thus, we summarily affirm the obviousness double patenting rejection. This being said, the use of slashes and “or” makes the listing of claims unclear. In patent prosecution practice, slashes between claim numbers have Appeal 2018-007258 Application 15/207,414 6 generally been used to show the dependency of claims. See MPEP § 608.01(n)(I)(F) (Table using slashes (e.g., 3/2/1) to identify a claim along with the claims from which it depends). The Examiner’s slashes do not conform to the dependency of the claims. Thus, it does not appear that the Examiner is using the slashes to show dependency. In general English usage, a slash may be used to show alternatives (e.g., “and/or”) and this may be the way the Examiner is using the slashes. Thus, we assume that the Examiner is rejecting claims 23–29 and 33–39. In any case, because Appellant does not argue against the rejection, we have no basis to reverse it as to any claim. DECISION Claims Rejected Basis Affirmed Reversed 21, 22, 30– 32, 40 § 103(a) 21, 22, 30– 32, 40 23–29, 33– 39 Nonstatutory double patenting 23–29, 33– 39 Overall Outcome 23–29, 33– 39 21, 22, 30– 32, 40 FINALITY AND RESPONSE No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R. § 1.136(a)(1)(iv). AFFIRMED-IN-PART Copy with citationCopy as parenthetical citation