ARM Limited

Patent Trials and Appeals Board

Dec 31, 2020

2019003926 (P.T.A.B. Dec. 31, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/855,687 09/16/2015 Alex James WAUGH JRL-550-1903 2989
73459 7590 12/31/2020
NIXON & VANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203
EXAMINER
BRAGDON, REGINALD GLENWOOD
ART UNIT PAPER NUMBER
2139
NOTIFICATION DATE DELIVERY MODE
12/31/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ALEX JAMES WAUGH

Appeal 2019-003926
Application 14/855,687
Technology Center 2100

Before CARL W. WHITEHEAD JR., DAVID M. KOHUT, and
IRVIN E. BRANCH, Administrative Patent Judges.

KOHUT, Administrative Patent Judge.

DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1–4, 6, 7, and 19–21.2 We have
jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM.

1 We use “Appellant” to reference the applicant as defined in
37 C.F.R. § 1.42. Appellant identifies the real party in interest as
“ARM Limited.” Appeal Br. 3.
2 The Examiner indicates that claims 5 and 8−18 are objected to as being
dependent upon a rejected base claim, but would be allowable if rewritten in
independent form including all of the limitations of the base claim and any
intervening claims. Final Act. 7.
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STATEMENT OF THE CASE
Appellant’s Invention
According to Appellant, the following example of the invention
“help[s] illustrate . . . the claimed technology.” Appeal Br. 7.
The first and second storage circuits correspond in the example
in Figure 2 to a level 1 cache and a level 2 cache. When a
cache eviction occurs, a cache line is moved from the level 1
cache to the level 2 cache. But if a power down is occurring, it
is unlikely that the data in the level 2 cache will be accessed for
a long period of time. So[,] rather than expend energy in
maintaining that data in the level 2 cache[ if] the power state
changes to power down, a signal is issued in order to cause that
data in the level 2 cache to not be retained by the level 2 cache.
Id. (addressing Spec. 10, l. 1–11, l. 5). Claim 1, reproduced below, recites
all subject matter argued on appeal. Id. at 9.
1. An apparatus comprising:
power state determination circuitry to determine a power state
of a processing circuit; and
control circuitry to issue a control signal relating to an item of
data stored in a first storage circuitry,
wherein when the power state of the processing circuit is a
predetermined state, the control circuitry issues a further control
signal to a second storage circuitry to indicate whether the item
of data is to be retained by the second storage circuitry.
Appeal Br., Claims Appendix.
Rejections
Claims 1–4, 20, and 21 stand rejected under 35 U.S.C. § 102(a)(1) as
being anticipated by Moshayedi (US 2010/0202239 A1; pub. Aug. 12, 2010)
Final Act. 3–4.
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Claim 19 stands rejected under 35 U.S.C. § 103 as being unpatentable
over Moshayedi and Haghighi (US 2016/0054933 A1; pub. Feb. 25, 2016).
Final Act. 5.
Claims 6 and 7 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Moshayedi and Vinod (US 2016/0283380 A1; pub. Sept.
29, 2016). Final Act. 5.
OPINION
Appellant addresses the rejected claims (1–4, 6, 7, and 19–21)
collectively. Appeal Br. 5–9. The only argued claim limitation is: “when
the power state of the processing circuit is a predetermined state, the control
circuitry issues a further control signal to a second storage circuitry to
indicate whether the item of data is to be retained by the second storage
circuitry” (independent claims 1 and 21). Id. at 9 (original emphasis). The
limitation is recited by all claims and is read on Moshayedi by all of the
Examiner’s rejections (Final Act. 3–6).
Before addressing the arguments, we note the Examiner reads claim 1
on Moshayedi’s system as follows. The claimed “power state
determination” reads on the system’s determination of whether the primary
power source is interrupted. Final Act. 3; see also Moshayedi ¶ 33. The
claimed “control signal relating to an item of data stored in a first storage
circuitry” reads on the system responding to a power interruption by
signaling the memory to copy data from the volatile memory 120 to the
non-volatile memory 130 (i.e., to backup data). Final Act. 3; see also
Moshayedi ¶¶ 34, 46, 49. The claimed “when the power state . . . is a
predetermined state” reads on the primary power source being uninterrupted.
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Final Act. 3–4; Ans. 4;3 see also Moshayedi ¶ 48. And, the claimed “further
control signal . . . to indicate whether the item of data is to be retained by the
second storage circuitry” reads on the system signaling the memory to erase
the non-volatile memory 130. Final Act. 3–4; Ans. 4–5; see also
Moshayedi ¶ 51.
We also note Moshayedi’s above operations would occur as part of
the system’s following sequence of operations: IDLE (normal operation);
BACKUP the volatile memory 120 in response to the power being
interrupted (NVDIMM_PG is low) and the data being designated for backup
(NVCACHE_ENABLE is high); POWER DOWN in response to completing
the backup; POWER UP in response to the power returning (NVDIMM_PG
is high); RESTORE the data to the volatile memory 120; and ERASE the
non-volatile memory 130 in response to completing the restore operation
(NVCACHE_ENABLE deasserts). See Moshayedi ¶¶ 35, 46–48, 50–51.
Appellant contends:
In contrast to what is required by claim 1, Moshayedi’s power
state []“when the primary power source becomes available”[
(claim 1)] has no effect on whether data is retained in
non-volatile (flash) memory because the data is not erased from
non-volatile (flash) memory until: (a) the device is in the restore
state; (b) the restore successfully completes; and
(c) NVCACHE_ENABLE transitions from high to low.

3 In this Decision, we cite to the Answer mailed March 13, 2019 and note
that a prior Answer was mailed February 25, 2019. Both Answers are
identical, except the later-filed Answer adds a sixth page to describe a
“[r]equirement to pay appeal forwarding fee.”
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Appeal Br. 8 (addressing Moshayedi ¶ 51); see also id. at 7 (“[D]ata is
always retained in the non-volatile (flash) memory 130 when the primary
power source becomes available[.]”). We are unpersuaded of error.
Appellant contends that the Moshayedi system’s erasure of data from
the non-volatile memory 130 cannot teach the argued claim limitation
because the system’s signal to erase occurs several operations after power
has returned to the system (i.e., after operations (a) to (c) of the above block
quote) and the claimed “issues a further control signal . . . to indicate
whether the item of data is to be retained by the second storage circuitry”
occurs “when the power state of the processing circuit is a predetermined
state.” Id. at 8 (block-quoted above). However, as the Examiner finds,
Moshayedi’s system achieves the argued claim limitation because the system
signals the non-volatile memory 130 to erase itself when power is
uninterrupted (while NVDIMM_PG is high). Final Act. 3–4; Ans. 4–5; see
also supra 3–4 (explanation of the Examiner’s findings). We conclude that
the claim limitation requires nothing more. Accord Spec. 3, ll. 10–13
(stating erasure should be conditioned on the power source’s state and thus
occur “when,” i.e., while, the power source is a predetermined state);
Merriam Webster Dictionary, https://www.merriam-webster.com/dictionary/
when (last visited December 29, 1970). Therefore, the disputed limitation
does not distinguish over Moshayedi’s system signaling the erasure several
operations after the power returns (while NVDIMM_PG is high and upon
NVCACHE_ENABLE deasserting to low).
Appellant also contends Moshayedi’s NVCACHE_ENABLE signal
does not teach the claimed “further control signal . . . to indicate whether the
item of data is to be retained by the second storage circuitry” because,
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according to Appellant, “[i]nstead . . . ‘NVCACHE_ENABLE transitions
from high to low’ (mapped to the further control signal) to erase data ‘if the
restore function is interrupted by loss of power.’” Reply Br. 4 (citing
Moshayedi ¶ 51). We are unpersuaded of error for each of two reasons.
First, Appellant is mischaracterizing the rejection. Contrary to the
argument, the rejection is not reading the claimed “further control signal” on
the Moshayedi’s NVCACHE_ENABLE signal. Final Act. 3–4; Ans. 4–5;
see also supra 3–4 (explanation of the Examiner’s findings). Rather, the
rejection is reading the claimed “further control signal” on Moshayedi’s
system signaling the non-volatile memory 130 to erase itself. Id.
Second, Appellant is mischaracterizing the disclosure of Moshayedi’s
cited paragraph 51. Contrary to the argument (Reply Br. 4), paragraph 51
does not present the quoted statements—“if the restore function is
interrupted by loss of power” and “NVCACHE_ENABLE transitions from
high to low”—as respectively ‘if’ and ‘then’ parts of an if/then operation.
Rather, paragraph 51 states “Module 100:,” then lists several operations after
the colon and separated by semi-colons, and thereby separates the quoted
statements into different operations of Moshayedi’s invention (i.e., of the
“dual in-line memory module (DIMM) 100”).
For the foregoing reasons, we sustain the rejections of claims 1–4, 6,
7, and 19–21 under § 103.
OVERALL CONCLUSION
We affirm the Examiner’s decision to reject claims 1–4, 6, 7, and 19–
21.
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DECISION SUMMARY
Claims
Rejected 35 U.S.C. Basis Affirmed Reversed
1–4, 20, 21 § 103 Moshayedi 1–4, 20, 21
19 § 103 Moshayedi, Haghighi 19
6, 7 § 103 Moshayedi, Vinod 6, 7
Overall
Outcome
1–4, 6, 7,
19–21

TIME PERIOD FOR RESPONSE
No time period for taking any subsequent action in connection with
this Appeal may be extended under 37 C.F.R. § 1.136(a). See
37 C.F.R. § 1.136(a)(1)(iv).

AFFIRMED