ARM Limited

Patent Trials and Appeals Board

Dec 2, 2020

2019005337 (P.T.A.B. Dec. 2, 2020)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/241,461 08/19/2016 Rowan Nigel NAYLOR P03837US.family 4785
134423 7590 12/02/2020
Leveque Intellectual Property Law, P.C.
241 E. 4th Street, #102
Frederick, MD 21701
EXAMINER
OBERLY, ERIC T
ART UNIT PAPER NUMBER
2184
NOTIFICATION DATE DELIVERY MODE
12/02/2020 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
eofficeaction@appcoll.com
info@levequeip.com
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PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ROWAN NIGEL NAYLOR,
PHANINDRA KUMAR MANNAVA, and
BRUCE JAMES MATHEWSON
____________
Appeal 2019-005337
Application 15/241,461
Technology Center 2100
____________

Before ELENI MANTIS MERCADER, NORMAN H. BEAMER, and
ADAM J. PYONIN, Administrative Patent Judges.

PYONIN, Administrative Patent Judge.

DECISION ON APPEAL
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s rejection. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in
37 C.F.R. § 1.42. Appellant identifies Arm Limited as the real party in
interest. Appeal Br. 3.
Appeal 2019-005337
Application 15/241,461

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STATEMENT OF THE CASE
Introduction
Appellant’s disclosure relates to an “interconnect circuit” that has a
first interface for coupling to a primary device and a second interface for
coupling to a secondary device, and is used to “reduce the latency associated
with the handling of transfers within the interconnect circuitry.” Abstract.
Claims 1, 19, and 22 are independent; claim 1 is reproduced below for
reference (with emphasis added):
1. Interconnect circuitry comprising:
a first interface to couple to a master device;
a second interface to couple to a slave device,
transactions being performed between the master device and the
slave device, where each transaction comprises one or more
transfers, each transfer comprising a request and a response;
a first connection path between the first interface and the
second interface comprising a first plurality of pipeline stages,
the first connection path forming a default path for propagation
of the requests and responses of the transfers;
a second connection path between the first interface and
the second interface comprising a second plurality of pipeline
stages, where the second plurality is less than the first plurality;
and
path selection circuitry to determine on a transfer-by-
transfer basis presence of a fast path condition, in the presence
of the fast path condition the path selection circuitry causing at
least one of the request and the response for a given transfer to
be propagated via the second connection path.

The Examiner’s Rejections
Claims 1–9, 15–20, and 22 stand rejected under 35 U.S.C. § 103 as
being unpatentable over Mathewson (US 2004/0267994 A1; Dec. 30, 2004)
and Epps (US 6,721,316 B1; Apr. 13, 2004). Final Act. 2.
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Application 15/241,461

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Claims 10, 11, and 21 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Mathewson, Epps, and Rowlands (US 2003/0217115 A1;
Nov. 20, 2003). Final Act. 8.
Claims 12–14 stand rejected under 35 U.S.C. § 103 as being
unpatentable over Mathewson, Epps, and Pellacuru (US 7,334,125 B1; Feb.
19, 2008). Final Act. 10.

ANALYSIS
Appellant argues that
the skilled person having knowledge of the disclosure of Mathewson
lacks knowledge of path selection circuitry that can determine the path
of a data packet on a transfer-by-transfer basis. To the contrary, a
skilled artisan would simply have knowledge of a system that
provides fast and slow pathways that are selected between based on a
global operating condition

Reply Br. 6. Appellant contends, whereas “[w]ith respect to Epps, there is
absolutely no teaching of path selection circuitry in a system having fast and
slow paths,” and “[i]nstead, Epps discloses a method of dropping data
packets when they are not deemed important.” Reply Br. 6, citing Epps
13:55–57, 19:16–21 (cited in Appeal Br. 15–16). Appellant argues that “the
Examiner improperly uses hindsight reconstruction to pick and choose the
‘on a transfer-by-transfer basis’ feature from Epps without considering the
teaching of Epps as a whole” (Reply Br. 7), and that
based on the Examiner’s interpretation of Epps, packets by default
follow the fast path (the second connection path), but are selectively
deferred/dropped (which the Examiner appears to equate to the first
connection path). This is the exact opposite of the claimed subject
matter, where the default approach is to use the first connection path,
but the path selection circuitry is used to determine the presence of a
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Application 15/241,461

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“fast path condition”, and in the presence of the fast path condition
causes the second connection path to be used instead of the first
connection path.

Reply Br. 8, emphasis in original.
We agree. The Examiner finds the following:
Mathewson is concerned with the characteristics of the data, [0045],
and the timing characteristics of the interconnect, [0055], in arranging
communication between the master and slave, but does not appear to
go as far as to make the determination “on a transfer-by-transfer
basis”. The secondary reference Epps demonstrates a technique
applicable to directing transfers through routing circuitry and applies a
determination “on a transfer-by-transfer basis”, which is such that
“Important” packets/transfers are not delayed by further processing,
the fast path of Epps is the path that does not subject the packets to
delay by further processing, such as the Random Early Detection
(RED) processing which can make a determine on whether the packet
could/should be drop[ped] or not.

Ans. 5, citing Epps 7:36, 33:25–30. The Examiner further finds that “[t]he
modification of Mathewson in view of . . . Epps is motivated by the benefit
of avoiding delay in the handling of certain transfers.” Ans. 5–6.
We agree that the Examiner has improperly used hindsight
construction to incorporate the teachings in Epps into Mathewson. Here,
Mathewson is concerned with the placement of a “register slice” in a circuit.
Mathewson ¶ 45; see also Mathewson ¶ 50, and Figs. 1A, 2, 3. Mathewson
further teaches the use such slices can use a “bypass mode . . . where the
selectable register slices 800 are selectively bypassed, once it is determined
that the operating conditions will allow the bypass mode to be used.”
Mathewson ¶ 92, (emphasis added). The Examiner’s cited portion of Epps
teaches that “‘[i]mportant packets can be [] labeled,” on a transfer-by-
transfer basis, to “ensur[e] that certain control messages (such as IPC
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packets) are delivered from one linecard to another linecard in the system.”
Epps 33:26–31.
We are persuaded the Examiner errs in combining Mathewson and
Epps. Mathewson teaches or suggests using system level information
(“operating characteristics”) rather than information of the slice itself in
determining a bypass mode. See, e.g., Mathewson ¶ 101 (“configuration can
be performed dynamically as operating conditions change. For example,
different predetermined setups can be defined for different clock speeds,
different supply voltages, etc.”). The Examiner does not sufficiently explain
why one of ordinary skill would modify Mathewson’s teachings based on
system operating conditions with Epps’s teachings based on individual
packets. Thus, we find the Examiner has erred in relying on the combination
of Mathewson and Epps. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398,
421 (2007) (“A factfinder should be aware, of course, of the distortion
caused by hindsight bias and must be cautious of arguments reliant upon ex
post reasoning.”).
Accordingly, we are constrained by the record to reverse the
Examiner’s obviousness rejection of independent claim 1, independent
claims 19 and 22 which recite similar limitations, as well as the rejections of
the claims dependent thereon.

Appeal 2019-005337
Application 15/241,461

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DECISION SUMMARY

REVERSED
Claims
Rejectede
jected
35 U.S.C.
§
Reference(s)/Basis

Affirmed Reversed
1–9, 15–
20, 22
103 Mathewson, Epps 1–9, 15–
20, 22
10, 11, 21 103 Mathewson, Epps,
Rowlands
10, 11, 21
12–14 103 Mathewson, Epps,
Pellacuru
12–14
Overall
Outcome
1–22