ARM LimitedDownload PDFPatent Trials and Appeals BoardAug 12, 20212020003170 (P.T.A.B. Aug. 12, 2021) Copy Citation UNITED STATES PATENT AND TRADEMARK OFFICE UNITED STATES DEPARTMENT OF COMMERCE United States Patent and Trademark Office Address: COMMISSIONER FOR PATENTS P.O. Box 1450 Alexandria, Virginia 22313-1450 www.uspto.gov APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO. 15/428,550 02/09/2017 Anitha KONA JRL-550-2080 1066 73459 7590 08/12/2021 NIXON & VANDERHYE, P.C. 901 NORTH GLEBE ROAD, 11TH FLOOR ARLINGTON, VA 22203 EXAMINER ROCHE, JOHN B ART UNIT PAPER NUMBER 2184 NOTIFICATION DATE DELIVERY MODE 08/12/2021 ELECTRONIC Please find below and/or attached an Office communication concerning this application or proceeding. The time period for reply, if any, is set in the attached communication. Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the following e-mail address(es): PTOMAIL@nixonvan.com pair_nixon@firsttofile.com PTOL-90A (Rev. 04/07) UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ Ex parte ANITHA KNOA, MICHAEL WAYNE GARNER, RANDALL L. JONES, TESSIL THOMAS, SEOW CHUAN LIM, KARTHICK SANTHANAM and LIANA CHRISTINE NICKLAUS _____________ Appeal 2020-003170 Application 15/428,550 Technology Center 2100 ____________ Before MAHSHID D. SAADAT, ST. JOHN COURTENAY III, and SCOTT E. BAIN, Administrative Patent Judges. COURTENAY, Administrative Patent Judge. DECISION ON APPEAL Appellant1 appeals under 35 U.S.C. § 134(a) from a final rejection of claims 1 and 3–14, which constitute all the claims pending in this application. Claim 2 is canceled. We have jurisdiction over the pending claims under 35 U.S.C. § 6(b). We affirm. 1 We use the word “Appellant” to refer to “applicant” as defined in 37 C.F.R. § 1.42(a). According to Appellant, the real party in interest in this appeal is ARM Limited, a corporation of the United Kingdom. See Appeal Br. 3. Appeal 2020-003170 Application 15/428,550 2 STATEMENT OF THE CASE 2 Introduction Embodiments of Appellant’s claimed subject matter relate generally to data processing. “In particular, the present disclosure has relevance to responding to unresponsive processing circuitry.” Spec. 1. Representative Claim 1 1. A data processing apparatus comprising: first processing circuitry; [a] interrupt generating circuitry configured to generate an outgoing interrupt and to transmit the outgoing interrupt outside said data processing apparatus, in response to said first processing circuitry becoming unresponsive; and [b] interrupt receiving circuitry configured to receive an incoming interrupt from outside said data processing apparatus, which indicates that second processing circuitry has become unresponsive, and in response to receiving said incoming interrupt, to cause said data processing apparatus to access data managed by said second processing circuitry, [c] wherein said data managed by said second processing circuitry comprises a state of said second processing circuitry. Appeal Br. 13. Claims App. (disputed claim limitations bracketed as “a”, “b”, and “c” as designated and argued by Appellant in the Briefs). 2 We herein refer to the Final Office Action, mailed March 20, 2019 (“Final Act.”); the Appeal Brief, filed October 18, 2019 (“Appeal Br.”); the Examiner’s Answer, mailed January 24, 2020; and the Reply Brief, filed March 23, 2020 (“Reply Br.”). Appeal 2020-003170 Application 15/428,550 3 Prior Art Evidence Relied Upon by the Examiner Name Reference Date Iizuka et al. (“Iizuka”) US 2004/0193763 A1 Sept. 30, 2004 Snead US 2010/0235558 A1 Sept. 16, 2010 Cannata et al. “Cannata”) US 2015/0370665 A1 Dec. 24, 2015 Table of Rejections Rejections Claims Rejected 35 U.S.C. § Reference(s)/Basis A 1, 3, 4, 6–14 103 Cannata, Snead B 5 103 Cannata, Snead, Iizuka ISSUES AND ANALYSIS We have considered all of Appellant’s arguments and any evidence presented. To the extent Appellant has not advanced separate, substantive arguments for particular claims, or other issues, such arguments are forfeited or waived.3 See, e.g., 37 C.F.R. § 41.37(c)(1)(iv). Throughout this opinion, 3 See In re Google Technology Holdings LLC, 980 F.3d 858, 862 (Fed. Cir. 2020) (some internal citation omitted): It is well established that “[w]aiver is different from forfeiture.” United States v. Olano, 507 U.S. 725, 733 (1993). “Whereas forfeiture is the failure to make the timely assertion of a right, Appeal 2020-003170 Application 15/428,550 4 we give the claim limitations the broadest reasonable interpretation (BRI) consistent with the Specification. See In re Morris, 127 F.3d 1048, 1054 (Fed. Cir. 1997). We highlight and address specific findings and arguments for emphasis in our analysis below. Rejection A under 35 U.S.C. § 103 of Representative Claim 1 Reference Teachings In the Appeal Brief, Appellant advances three principal arguments regarding limitations “a” “b” and “c” of claim 1: (a) “Cannata does not disclose transmitting an interrupt outside an apparatus as is required by ‘interrupt generating circuitry configured to generate an outgoing interrupt and to transmit the outgoing interrupt outside said data processing apparatus, in response to said first processing circuitry becoming unresponsive.’” Appeal Br. 7. (b) “[B]ecause Cannata lacks the claimed interrupt receiving circuitry, there is no interrupt receiving circuitry configured to receive an incoming interrupt from outside the data processing apparatus that indicates that the second processing circuitry has become unresponsive.” Appeal Br. 8. (c) Regarding limitation “c” (“wherein said data managed by said second processing circuitry comprises a state of said second processing circuitry”), “[t]here is no disclosure or suggestion that ‘what the second waiver is the ‘intentional relinquishment or abandonment of a known right.’” Id. (quoting Johnson v. Zerbst, 304 U.S. 458, 464 (1938)) (additional citations omitted). The two scenarios can have different consequences for challenges raised on appeal, id. at 733–34, and for that reason, it is worth attending to which label is the right one in a particular case. Appeal 2020-003170 Application 15/428,550 5 processing circuitry was accessing at the time of its failure’ is part of the failover table.” Appeal Br. 9. Regarding the secondary Snead reference, Appellant contends: There is no reasonable basis for a person of ordinary skill in the art (POSITA) to modify Cannata to include Snead's watchdog timers and common interrupt line 120. Cannata already describes a system where processors monitor other processors for failures that includes time-out mechanism being used by the monitoring processor to detect a failure in the monitored processor. See paragraph [0097]. A POSITA would have viewed adding watchdog timers to Cannata's processors as unnecessary. Appeal Br. 10. We consider the following issues seriatim, as raised by Appellant’s arguments in the Appeal Brief: Limitations “a” “b” and “c” of Claim 1 Issue 1: Under 35 U.S.C. § 103, did the Examiner err by finding that the combination of Cannata and Snead teaches or suggests the following disputed a, b, and c limitations of independent claim 1? [a] interrupt generating circuitry configured to generate an outgoing interrupt and to transmit the outgoing interrupt outside said data processing apparatus, in response to said first processing circuitry becoming unresponsive; and [b] interrupt receiving circuitry configured to receive an incoming interrupt from outside said data processing apparatus, which indicates that second processing circuitry has become unresponsive, and in response to receiving said incoming interrupt, to cause said data processing apparatus to access data managed by said second processing circuitry, Appeal 2020-003170 Application 15/428,550 6 [c] wherein said data managed by said second processing circuitry comprises a state of said second processing circuitry. Claim 1 (disputed claim limitations bracketed as “a”, “b”, and “c” as argued by Appellant in the Appeal Brief). Combinability of the References Issue 2: Under 35 U.S.C. § 103, did the Examiner err by improperly combining the Cannata and Snead references? The Examiner’s Response in the Answer The Examiner disagrees with Appellant, and further explains the basis for the rejection in the Answer, regarding claim 1 limitations “a” “b” and “c.” The Examiner’s Mapping 4 for Limitations “a” “b” and “c” of claim 1 In response to Appellant’s argument for limitation “a” of claim 1, the Examiner finds that Cannata teaches “a processor generating an interrupt in response to a failover” at paragraph 109, lines 12–16. Ans. 19. The Examiner also finds that Snead teaches “transmitting an outgoing interrupt outside a data processing apparatus” as depicted in Figure 1, and as described at paragraph 18, lines 1–5. Ans. 9 (emphasis added). The 4 See the mapping rule, under 37 C.F.R § 1.104(c)(2): “When a reference is complex or shows or describes inventions other than that claimed by the applicant, the particular part relied on must be designated as nearly as practicable. The pertinence of each reference, if not apparent, must be clearly explained and each rejected claim specified.” Appeal 2020-003170 Application 15/428,550 7 Examiner additionally finds Cannata “discloses the interrupt being generated on the PCIe bus, which would appear to at least fairly suggest that the interrupt is being transmitted outside of the processor.” Ans. 10 (emphasis added). In response to Appellant’s argument for limitation “b” of claim 1, the Examiner finds Snead “discloses interrupt receiving circuitry configured to receive the incoming interrupt from outside a data processing apparatus,” citing Snead’s Figure 1, and paragraph 18, lines 3 –7, in support. Ans. 10. The Examiner finds that the combined teachings and suggestions of Cannata and Snead render limitation “b” of claim 1 obvious. See Id. In response to Appellant’s argument for limitation “c” of claim 1, the Examiner finds Cannata, at paragraph 109, lines 17–19, “discloses SSDs [(Solid State Drives)] matching a failover table of the failed processor of Cannata.” Ans. 10. The Examiner finds that the reason the information of the second processing circuitry would be kept would be “in order to continue the operations that were being performed with minimal interruptions.” Ans. 11. The Examiner finds “the failover table would be indicative of the failed processor attempting to access/operate particular drives, which would be important to continue operations.” Id. Appeal 2020-003170 Application 15/428,550 8 Analysis Limitation “a” of Claim 1 [a] interrupt generating circuitry configured to generate an outgoing interrupt and to transmit the outgoing interrupt outside said data processing apparatus, in response to said first processing circuitry becoming unresponsive; Regarding disputed limitation “a” of claim 1, we note that Cannata describes at least one embodiment in which “processor 320 comprises an ARM microcontroller, [or] ARM microprocessor” (¶ 69, and “once a particular processor has been configured to manage a particular SSD drive, the processor might experience a failure or interruption in normal operation” (¶ 102), whereby “[r]esponsive to the failure of a processor, such as processor 631, another processor 732 can be configured to take over management of the SSD drives previously managed by the failed processor 631” (¶ 103). Cannata (¶ 104 ) further describes: “Each processor can include table 780 which indicates which SSDs are managed by that processor and which SSDs are managed by the processors which that processor monitors for failures.” “Once a processor has been determine to have failed, the monitoring processor, such as processor 732, can be configured to initiate a restart, reboot, or power cycle of the failed processor.” Cannata ¶ 107. “If the failed processor comes back online and functioning after the restart, reboot, or power cycle, then those SSD drives that were transitioned to the monitoring processor can be re-managed by the previously failed processor.” Id. Appeal 2020-003170 Application 15/428,550 9 Based upon our review of the record, we find Appellant is arguing the references separately by attacking Cannata in isolation.5 See Appeal Br. 6–7. The Examiner finds that Snead teaches or suggests interrupt generating and receiving circuitry: Snead ’558 teaches interrupt generating circuitry transmitting outgoing interrupts outside a data processing apparatus (watchdog timer of each processor asserts TIMEOUT signal along interrupt line 120 to other processors, see figure 1 and paragraph 18, lines 1-5), and [] interrupt receiving circuitry configured to receive the incoming interrupt from outside said data processing apparatus (each processor 102 has an INT input that receives interrupt signal from line 120, see figure 1 and paragraph 18, lines 3-7). Final Act. 3–4. (emphasis added). We note that Appellant does not address the Examiner’s specific findings regarding Snead (id.) in the Appeal Brief. Therefore, we find Appellant’s arguments in the Reply Brief regarding Snead are untimely under our procedural rule 37 C.F.R. § 41.41(b)(2).6 5 See In re Merck & Co., 800 F.2d 1091, 1097 (Fed. Cir. 1986) (One cannot show non obviousness by attacking references individually where the rejections are based on combinations of references.). 6 We emphasize that the Reply Brief is not an opportunity to make arguments that could have been made in the principal brief on appeal to rebut the Examiner’s rejections, but were not. See Ex parte Borden, 93 USPQ2d 1473, 1474 (BPAI 2010) (informative). Any argument raised in the reply brief which was not raised in the appeal brief, or is not responsive to an argument raised in the examiner’s answer, including any designated new ground of rejection, will not be considered by the Board for purposes of the present appeal, unless good cause is shown. 37 C.F.R. § 41.41(b)(2). Appeal 2020-003170 Application 15/428,550 10 Limitation “b” of Claim 1 [b] interrupt receiving circuitry configured to receive an incoming interrupt from outside said data processing apparatus, which indicates that second processing circuitry has become unresponsive, and in response to receiving said incoming interrupt, to cause said data processing apparatus to access data managed by said second processing circuitry, We reproduce Appellant’s argument for claim 1 limitation (b): “[B]ecause Cannata lacks the claimed interrupt receiving circuitry, there is no interrupt receiving circuitry configured to receive an incoming interrupt from outside the data processing apparatus that indicates that the second processing circuitry has become unresponsive.” Appeal Br. 8. Based upon our review of the record, we again find Appellant is arguing the references separately by attacking Cannata in isolation. See Appeal Br. 8. See Merck, 800 F.2d at 1097. The Examiner finds Snead teaches or suggests interrupt generating and receiving circuitry. See Final Act. 3–4. As noted above, the Examiner finds that Snead teaches “transmitting an outgoing interrupt outside a data processing apparatus” as depicted in Figure 1, and as described at paragraph 18, lines 1–5. Ans. 9 (emphasis added). The Examiner additionally finds Cannata “discloses the interrupt being generated on the PCIe bus, which would appear to at least fairly suggest that the interrupt is being transmitted outside of the processor.” Ans. 10 (emphasis added). Therefore, we find unavailing Appellant’s arguments regarding limitation “b” of claim 1. Appeal 2020-003170 Application 15/428,550 11 Limitation “c” of Claim 1 [c] wherein said data managed by said second processing circuitry comprises a state of said second processing circuitry. We reproduce Appellant’s argument for limitation “c” of claim 1: “[t]here is no disclosure or suggestion that ‘what the second processing circuitry was accessing at the time of its failure’ is part of the failover table.” Appeal Br. 9. However, we note the Examiner’s finding that Cannata, at paragraph 109, lines 17–19, “discloses SSDs matching a failover table of the failed processor of Cannata.” Ans. 10. The Examiner specifically found “the failover table would be indicative of the failed processor attempting to access/operate particular drives, which would be important to continue operations.” Id. The Examiner’s findings are supported by a preponderance of the evidence. See Cannata at paragraph 109, which expressly discloses a failover table and a failover interrupt (emphasis added): There is a table included in each processor that tells it which SSD it owns normally and which it supports when there is a failover situation. In the event of a failover an interrupt is generated on the PCIe bus as it switches over. A discovery process of drive(s) assigned to the failed processor is initiated. This is followed by the processor populating discovered SSD(s) that match the failover table into its active table. Appeal 2020-003170 Application 15/428,550 12 See also, e.g., Cannata ¶ 103: “Responsive to the failure of a processor, such as processor 631, another processor 632 can be configured to take over management of the SSD drives previously managed by the failed processor 631.” As noted above, Cannata (¶ 104) describes: “Each processor can include table 780 which indicates which SSDs are managed by that processor and which SSDs are managed by the processors which that processor monitors for failures.” “Once a processor has been determine to have failed, the monitoring processor, such as processor 732, can be configured to initiate a restart, reboot, or power cycle of the failed processor.” Cannata ¶ 107. “If the failed processor comes back online and functioning after the restart, reboot, or power cycle, then those SSD drives that were transitioned to the monitoring processor can be re-managed by the previously failed processor.” Id. Regarding each of limitations “a” “b” and “c” of claim 1, we emphasize that “the question under 35 USC 103 is not merely what the references expressly teach but what they would have suggested to one of ordinary skill in the art at the time the invention was made.” Merck & Co. v. Biocraft Labs., Inc., 874 F.2d 804, 807 (Fed. Cir. 1989) (quoting In re Lamberti, 545 F.2d 747, 750 (CCPA 1976)) (emphasis added). See also MPEP § 2123. Appeal 2020-003170 Application 15/428,550 13 Combinability of the References We also disagree with Appellant’s contention that There is no reasonable basis for a person of ordinary skill in the art (POSITA) to modify Cannata to include Snead's watchdog timers and common interrupt line 120. Cannata already describes a system where processors monitor other processors for failures that includes time-out mechanism being used by the monitoring processor to detect a failure in the monitored processor. See paragraph [0097]. A POSITA would have viewed adding watchdog timers to Cannata's processors as unnecessary. Appeal Br. 10. The Examiner found Snead is analogous to Cannata because “they are both drawn to the same inventive field of inter-processor communication.” Final Act. 4. The Examiner further explains the motivation for an artisan to have modified Cannata with the teachings of Snead: Prior to the effective filing date of the invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Cannata'665 and Snead'558 before them, to modify the processing system of Cannata'665 to include the interrupt- related circuitry of Snead'558 by incorporating a watchdog timer for each processor, whereby an asserted signal from each timer is collected and sent to each processor in the system. The motivation for doing so would have been to bring about higher redundancy and reliability in networked, cloud, and enterprise environments (paragraph 4, lines 4-8). Therefore, it would have been obvious to combine Cannata'665 and Snead'558 to bring about the invention as claimed. Final Act. 4. Appeal 2020-003170 Application 15/428,550 14 We note that Cannata lacks specific details regarding the particular circuitry that implements the failover interrupts, except that we know “[i]n the event of a failover, an interrupt is generated on the PCIe bus as it switches over.” Cannata ¶ 109. The Examiner’s looks to Snead for a teaching of particular interrupt generation circuitry (e.g., watchdog timers 1161-N, and particular interrupt receiving circuitry, i.e., the “INT” interrupt receiving pin and associated internal circuitry of processors 1021-N, as depicted in Figure 1. As noted by Appellant, Cannata’s processors already monitor other processors for failures that include a “time-out mechanism being used by the monitoring processor to detect a failure in the monitored processor. See paragraph [0097].” Appeal Br. 10. But it is our view that Cannata describes a processor-intensive way of performing such monitoring, i.e., by sending periodic messages in which the monitoring processor must wait for a response, such as by polling a register or a network communication port: Processor 632 can monitor another processor, such as processor 631, using different methods. In a first example, processor 632 sends periodic messages to processor 631 and awaits response messages from processor 631. If the response messages fail to come within a predetermined amount of time, then processor 632 can determine that processor 631 has failed. The periodic messages can include probe packets sent through a network stack or stacks between processors, such as over a network interface that processor 631 and 632 can communicate. In another example, a set of registers or bits are maintained for processor 631 in processor 632 that are set or reset by processor 631. If a register or bit associated with processor 631 has not been properly set or reset within a predetermined amount of time, then processor 632 can determine that processor 631 has failed Appeal 2020-003170 Application 15/428,550 15 Cannata ¶ 97. (emphasis added). In contrast, we find Snead’s use of external watchdog timers to do the monitoring and to generate the “TIMEOUT” interrupt (as depicted in Snead’s Figure 1) would reduce the processing overhead for the processors described in Cannata, consistent with the Examiner’s finding of motivation: “The motivation for doing so would have been to bring about higher redundancy and reliability in networked, cloud, and enterprise environments (paragraph 4, lines 4-8).” Final Act. 4 (citing Cannata ¶ 4, ll. 4–8). Therefore, we find the Examiner provides sufficient “articulated reasoning with some rational underpinning to support the legal conclusion of obviousness.” In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006). See Final Act. 4. Moreover, in KSR, the Court held that “[t]he combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results.” KSR Int’l Co. v. Teleflex, Inc., 550 U.S. 398, 416 (2007). When a work is available in one field of endeavor, design incentives and other market forces can prompt variations of it, either in the same field or a different one. If a person of ordinary skill can implement a predictable variation, § 103 likely bars its patentability. For the same reason, if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill . . . . [A] court must ask whether the improvement is more than the predictable use of prior art elements according to their established functions. Id. at 417. Appeal 2020-003170 Application 15/428,550 16 Moreover, “it is not necessary that the inventions of the references be physically combinable to render obvious the invention under review.” In re Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983). The relevant inquiry is whether the claimed subject matter would have been obvious to those of ordinary skill in the art in light of the combined teachings of those references. See In re Keller, 642 F.2d 413, 425 (CCPA 1981). “Combining the teachings of references does not involve an ability to combine their specific structures.” In re Nievelt, 482 F.2d 965, 968 (CCPA 1973). This legal guidance is applicable here. Accordingly, we agree with and adopt the Examiner’s underlying factual findings and ultimate legal conclusion of obviousness regarding Rejection A of representative claim 1 over the collective teachings and suggestions of Cannata and Snead.7 For at least the aforementioned reasons, we sustain the Examiner’s Rejection A of representative independent claim 1. Grouped claims 3, 4, and 6–14, not separately argued, fall with claim 1 under Rejection A. See 37 C.F.R. § 41.37(c)(1)(iv). 7 See Icon Health and Fitness, Inc. v. Strava, Inc., 849 F.3d 1034, 1042 (Fed. Cir. 2017) (“As an initial matter, the PTAB was authorized to incorporate the Examiner’s findings.”); see also In re Brana, 51 F.3d 1560, 1564 n.13 (Fed. Cir. 1995) (upholding the PTAB’s findings, although it “did not expressly make any independent factual determinations or legal conclusions,” because it had expressly adopted the examiner’s findings). Appeal 2020-003170 Application 15/428,550 17 Rejection B of Dependent Claim 5 In view of the lack of any substantive, separate arguments for patentability directed to obviousness Rejection B of remaining dependent claim 5, we sustain the Examiner’s rejection of this claim, which falls with respective associated independent claim 1. Arguments not timely made are forfeited. See 37 C.F.R. § 41.37(c)(1)(iv). CONCLUSION The Examiner did not err in rejecting claims 1 and 3–14 as obvious under 35 U.S.C. § 103 over the cited combinations of references. FINALITY AND RESPONSE Claims Rejected 35 U.S.C. § Reference(s)/Basis Affirmed Reversed 1, 3, 4, 6–14 103 Cannata, Snead 1, 3, 4, 6–14 5 103 Cannata, Snead, Iizuka 5 Overall Outcome 1, 3–14 No time period for taking any subsequent action in connection with this appeal may be extended under 37 C.F.R. § 1.136(a)(1)(iv). See 37 C.F.R. § 41.50(f) AFFIRMED Copy with citationCopy as parenthetical citation