ARM LIMITED

Patent Trials and Appeals Board

Dec 23, 2021

2020006056 (P.T.A.B. Dec. 23, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/944,340 11/18/2015 Andrew David TUNE JRL-550-1933 5129
73459 7590 12/23/2021
NIXON & VANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203
EXAMINER
HUSON, ZACHARY K
ART UNIT PAPER NUMBER
2181
NOTIFICATION DATE DELIVERY MODE
12/23/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte ANDREW DAVID TUNE and
SEAN JAMES SALISBURY
Appeal 2020-006056
Application 14/944,340
Technology Center 2100

Before DAVID J. CUTITTA II, MICHAEL J. ENGLE, and
PHILLIP A. BENNETT, Administrative Patent Judges.

CUTITTA, Administrative Patent Judge.

DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1, 3, and 5–15.2 We have jurisdiction
under 35 U.S.C. § 6(b).
We REVERSE.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42(a).
Appellant identifies ARM Limited as the real party in interest. Appeal Br. 1.
2 Claim 2 is cancelled. Appeal Br. 15, 16.
Appeal 2020-006056
Application 14/944,340

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CLAIMED SUBJECT MATTER
Summary
The subject matter of Appellant’s application relates to “interconnect
circuitry having a buffer.” Spec. 1:5. The interconnect transfers requests
between source ports and destination ports and employs “a technique that
enables head-of-line blocking to be alleviated whilst reducing the possibility
of a subset of source devices filling the buffer and thereby causing head-of-
line blocking to occur on other source devices.” Spec. 2:4–7.
Illustrative Claim
Claim 1, reproduced below with certain dispositive limitation(s) at
issue italicized, illustrates the claimed subject matter:
1. An interconnect to transfer requests between ports,
the ports comprising a plurality of source ports and a plurality
of destination ports, the interconnect comprising:
storage circuitry to store said requests;
input circuitry to receive said requests from said plurality
of source ports, to select at least one selected source port from
an allowed set of said plurality of source ports, and to transfer a
presented request from said at least one selected source port to
said storage circuitry;
output circuitry to cause a request in said storage
circuitry to be output at one of said plurality of destination
ports;
counter circuitry to maintain counter values for a
plurality of tracked ports from amongst said ports, each counter
value indicating the number of requests in said storage circuitry
associated with a corresponding tracked port that are waiting to
be output by said output circuitry; and
filter circuitry to determine whether or not a given source
port is in said allowed set in dependence on said counter
circuitry, wherein:
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Application 14/944,340

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said plurality of tracked ports comprise said plurality of
source ports, and
said counter value corresponds to the number of requests
stored in the storage circuitry that have been sent by that source
port that have not yet been output by said output circuitry.
Appeal Br. 15 (Claims App.).
REFERENCES
The Examiner relies on the following prior art references:3
Name Reference Date
Herbst US 7,065,050 B1 June 20, 2006
Jones US 7,068,672 B1 June 27, 2006
Walsh US 7,209,440 B1 Apr. 24, 2007
Kinter US 2013/0031314 A1 Jan. 31, 2013
Kitahara US 2014/0173163 A1 June 19, 2014
REJECTIONS
The Examiner rejects the claims as shown below:
Claim(s) Rejected 35 U.S.C. § References Final Act.
1, 3, 5, 6, 9, 11, 13–15 103 Kitahara, Herbst 7
7, 8 103 Kitahara, Herbst, Kinter 28
10 103 Kitahara, Herbst, Walsh 31
12 103 Kitahara, Herbst, Jones 32
OPINION
We review the appealed rejections for error based upon the issues
identified by Appellant and in light of Appellant’s arguments and evidence.
Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010) (precedential).

3 All citations to the references use the first-named inventor or author only.
Appeal 2020-006056
Application 14/944,340

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The Examiner determines that claim 1 is unpatentable over the
combined teachings of Kitahara and Herbst. Final Act. 7–11. Of particular
relevance, the Examiner relies on Herbst’s Pipelined Memory Management
Unit’s (“PMMU”) implementation of “temporal and spatially based flow
control within SOC [(Switch-On-Chip)] 10” to teach or suggest “filter
circuitry to determine whether or not a given source port is in said allowed
set in dependence on said counter circuitry,” as recited in claim 1. Final
Act. 11 (citing Herbst 59:21–23, 59:39–50 and Fig. 1, element 38). The
Examiner determines that motivation existed to apply the teachings of
Herbst to Kitahara “to prevent port congestion.” Final Act. 11 (citing Herbst
8:39).
Appellant argues Herbst fails to teach determining that a source port
is not in said allowed set, as claimed, because the text cited by the Examiner
from “Herbst refers to the situation in which an egress port becomes
congested.” Appeal Br. 10. According to Appellant, the Examiner “omits the
word ‘egress’ from the FOA’s summary of Herbst’s cited teachings,” despite
that Herbst actually “teaches switching off flow to an egress port that
becomes congested.” Appeal Br. 10–11 (citing Herbst 59:21–23, 59:39–50).
We are persuaded by Appellant’s argument that the portions of Herbst
cited by the Examiner relate to flow control by switching off “egress/output
ports” and therefore “Herbst does not teach switching off data flow from a
selected source port” because “Herbst’s teachings are limited to egress
ports.” Reply Br. 4–5 (emphasis added).

Appeal 2020-006056
Application 14/944,340

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Herbst’s Figure 1, reproduced below with annotations added,
illustrates SOC 10, including PMMU 70, “functionally connected to external
devices 11, external memory 12, fast ethernet ports 13, and gigabit ethernet
ports 15.” Herbst 4:57–60.

Figure 1 of Herbst depicts flow control of fast ethernet ports 13 and
gigabit ethernet ports 15. Herbst explains that “fast ethernet ports 13 will be
considered low speed ethernet ports, since they are capable of operating at
speeds ranging from 10 Mbps to 100 Mbps, while the gigabit ethernet ports
15, which are high speed ethernet ports, are capable of operating at 1000
Mbps.” Herbst 4:61–66. With respect to flow control by PMMU 70, Herbst
states:
[I]f a particular egress port is receiving an excessive number of
cells for transmission, then PMMU 70 is configured to
implement a combination of temporal and spatial flow control
methods to remedy the overcrowding at that particular egress
port. This overcrowding situation generally occurs when a
Gigabit port is acting as an ingress for packets destined for egress
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Application 14/944,340

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on a normal Ethernet port, as the Gigabit port can fill an egress
queue at a rate 10 to 100 times faster than normal Ethernet ports
can clear and transmit packets from the queue.
Herbst 59:23–32.
Herbst further discusses remedying the overcrowding by “switch[ing]
off data flow to a port that has or is becoming congested.” Id. at 59:41–42.
Herbst describes the congested port as a particular egress port, e.g., ethernet
port 13, explaining that the “overcrowding situation generally occurs when a
Gigabit port is acting as an ingress for packets destined for egress on a
normal Ethernet port.” Id. at 59:27–30. In contrast, Appellant’s “claim 1
refers to a source port being in the allowed set” and further “indicates that
the allowed source port relates to transmission, not receiving, i.e., ‘to
transfer a presented request from said at least one selected source port to said
storage circuitry.’” Reply Br. 4.
Accordingly, we agree with Appellant that the Examiner fails to teach
or suggest “filter circuity to determine whether or not a given source port is
in said allowed set,” in the context of claim 1. Nor does the Examiner show
that Kitahara compensates for the noted deficiencies of Herbst. Therefore,
Appellant persuades us of error in the Examiner’s obviousness rejection of
independent claim 1. Because we agree with at least one of the dispositive
arguments advanced by Appellant, we need not reach the merits of
Appellant’s other arguments seeking to distinguish claim 1.
CONCLUSION
We reverse the Examiner’s rejection of claim 1 and of claims 3, 5, 6,
9, 11, and 13–15, which either depend from claim 1 or otherwise recite
similar claim language.
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Application 14/944,340

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With respect to the remaining rejections of dependent claims 7, 8, 10,
and 12, the Examiner does not rely on Kinter, Walsh, or Jones to cure the
deficiency of the obviousness rejection explained above. Final Act. 28–32.
We, therefore, reverse the rejections of these claims for the reasons set forth
in relation to independent claim 1.
DECISION SUMMARY
In summary:

REVERSED
Claim(s)
Rejected
35
U.S.C. §
Reference(s)/
Basis
Affirm
ed Reversed
1, 3, 5, 6, 9,
11, 13–15
103 Kitahara, Herbst 1, 3, 5, 6, 9,
11, 13–15
7, 8 103 Kitahara, Herbst,
Kinter
7, 8
10 103 Kitahara, Herbst,
Walsh
10
12 103 Kitahara, Herbst,
Jones
12
Overall
Outcome
1, 3, 5–15