ARM Limited

Patent Trials and Appeals Board

Dec 21, 2021

2020006068 (P.T.A.B. Dec. 21, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/501,278 02/02/2017 Ali Ghassan SAIDI JRL-550-2074 1089
73459 7590 12/21/2021
NIXON & VANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203
EXAMINER
KHAN, MASUD K
ART UNIT PAPER NUMBER
2132
NOTIFICATION DATE DELIVERY MODE
12/21/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte ALI GHASSAN SAIDI and RICHARD ROY GRISENTHWAITE
___________

Appeal 2020-006068
Application 15/501,278
Technology Center 2100
____________

Before JAMES B. ARPIN, HUNG H. BUI, and CHRISTA P. ZADO,
Administrative Patent Judges.

ARPIN, Administrative Patent Judge.

DECISION ON APPEAL
Appellant1 appeals under 35 U.S.C. § 134(a) from the Examiner’s
decision rejecting claims 1, 2, and 6–24, all of the pending claims. Final
Act. 2.2 Claims 3–5 are cancelled. We have jurisdiction under 35 U.S.C.
§ 6(b).
We affirm.

1 “Appellant” refers to “applicant” as defined in 37 C.F.R. § 1.42 (2012).
Appellant identifies the real party-in-interest as ARM Limited. Appeal Br. 3
2 In this Decision, we refer to Appellant’s Appeal Brief (“Appeal Br.,” filed
April 17, 2020) and Reply Brief (“Reply Br.,” filed August 24, 2020); the
Final Office Action (“Final Act.,” mailed November 13, 2019) and the
Examiner’s Answer (“Ans.,” mailed June 25, 2020); and the Specification
(“Spec.,” filed February 2, 2017). Rather than repeat the Examiner’s
findings and Appellant’s contentions in their entirety, we refer to these
documents.
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STATEMENT OF THE CASE
The claimed apparatus and methods relate “to a data processing
apparatus having a write-back cache.” Spec., 1:3–5.
As noted above, claims 1, 2, and 6–24 are pending. Claims 1, 23, and
24 are independent. Appeal Br. 18–19 (claim 1), 23–25 (claims 23 and 24)
(Claims App.). Claims 2 and 6–22 depend directly or indirectly from
claim 1. Id. at 19–23.
Claim 1, reproduced below with disputed limitations emphasized, is
representative.
1. Apparatus for processing data comprising:
a processor core capable of performing data processing
operations in response to a sequence of instructions, wherein the
data processing operations comprise read operations which
retrieve data items from a memory and write operations which
write data items to the memory, wherein the memory is a non-
volatile memory;
a write-back cache capable of storing local copies of the
data items retrieved from the memory and written to the memory
by the processor core when executing the sequence of
instructions; and
a storage unit capable of storing indications of the write
operations initiated by the processor core, and
the processor core is capable of responding to an end
instruction in the sequence of instructions by:
causing the local copies of data items which are the subject
of the write operations by the processor core and for which an
indication is stored in the storage unit to be cleaned from the
write-back cache to the memory; and
clearing the indications of the write operations stored in
the storage unit,
wherein the processor core is further capable of causing
the indications of the write operations initiated by the processor
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core to be stored in the storage unit after a begin instruction in
the sequence of instructions,
wherein the processor core is capable of only performing
a write operation to a predetermined portion of the memory when
a pending write instruction specifying the predetermined portion
of the memory is preceded by the begin instruction and followed
by the end instruction, and
wherein the processor core is capable of preventing a
write operation to the predetermined portion of the memory from
being performed when a pending write instruction specifying the
predetermined portion of the memory is not preceded by the
begin instruction and followed by the end instruction.
Appeal Br. 18–19 (emphases added). Each of independent claims 23 and 24
recites limitations corresponding to the disputed limitations of claim 1. Id.
at 23–25.
REFERENCES AND REJECTIONS
The Examiner relies upon the following references:
Name3 Reference Published Filed
Rajwar US 2003/079094 A1 Apr. 24, 2003 Oct. 19, 2001
Akkary US 2007/0156994 A1 July 5, 2007 Dec. 30, 2005
Eilert US 2012/0198205 A1 Aug. 2, 2012 Jan. 27, 2011
Moraru US 2013/0091331 A1 Apr. 11, 2013 Oct. 11, 2011
Talagala US 2013/0227201 A1 Aug. 29, 2013 Mar. 15, 2013
Cain US 2014/0019689 A1 Jan. 16, 2014 July 10, 2012
Boehm US 2017/0192886 A1 July 6, 2017 Jan. 10, 20174

3 All reference citations are to the first named inventor only.
4 Although the present application claims the benefit of United Kingdom
Patent Application No. 1413772.3, filed August 4, 2014, Boehm claims the
benefit of International Patent Application No. PCT/US2014/049313, filed
July 31, 2014.
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The Examiner rejects:
a. claims 1, 11–13, 15–19, 23, and 24 under 35 U.S.C. § 103 as
obvious over the combined teachings of Moraru and Eilert (Final
Act. 6–29);
b. claim 2 under 35 U.S.C. § 103 as obvious over the combined
teachings of Moraru, Eilert, and Talagala (id. at 29);
c. claims 6–8 under 35 U.S.C. § 103 as obvious over the combined
teachings of Moraru, Eilert, and Rajwar (id. at 30–33);
d. claims 9 and 10 under 35 U.S.C. § 103 as obvious over the
combined teachings of Moraru, Eilert, and Cain (id. at 33–35);
e. claims 14, 20, and 22 under 35 U.S.C. § 103 as obvious over the
combined teachings of Moraru, Eilert, and Akkary (id. at 35–38);
and
f. claim 21 under 35 U.S.C. § 103 as obvious over the combined
teachings of Moraru, Eilert, Akkary, and Boehm (id. at 38–39).
We review the appealed rejections for error based upon the issues
identified by Appellant, and in light of the contentions and evidence
produced thereon. Ex parte Frye, 94 USPQ2d 1072, 1075 (BPAI 2010)
(precedential). The Examiner and Appellant focus their findings and
contentions, respectively, on claim 1; so we do as well. See Appeal Br. 9,
15, 16; Ans. 3–8. Arguments not made are forfeited.5 Unless otherwise

5 See In re Google Tech. Holdings LLC, 980 F.3d 858, 863 (Fed. Cir. 2020)
(“Because Google failed to present these claim construction arguments to
the Board, Google forfeited both arguments.”); 37 C.F.R. § 41.37(c)(1)(iv)
(2013) (“Except as provided for in §§ 41.41, 41.47 and 41.52, any arguments
or authorities not included in the appeal brief will be refused consideration
by the Board for purposes of the present appeal.”).
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indicated, we adopt the Examiner’s findings in the Final Office Action and
the Answer as our own and add any additional findings of fact for emphasis.
We address the rejections below.
ANALYSIS
Obviousness over Moraru and Eilert
As noted above, the Examiner rejects claim 1 as obvious over the
combined teachings of Moraru and Eilert. Final Act. 6–12, 39–40. The
Examiner finds Moraru teaches or suggests the majority of the limitations of
claim 1. Final Act. 6–10 (citing Moraru ¶¶ 17, 26–28, 36, 42, 53, 62–64,
Figs. 1, 2, 4, 29, 46, 81). Nevertheless, the Examiner finds:
Moraru does not explicitly teach wherein the processor
core is capable of only performing a write operation to a
predetermined portion of the memory when a pending write
instruction specifying the predetermined portion of the memory
is preceded by the begin instruction and followed by the end
instruction, and
wherein the processor core is capable of preventing a write
operation to the predetermined portion of the memory from being
performed when a pending write instruction specifying the
predetermined portion of the memory is not preceded by the
begin instruction and followed by the end instruction.
Id. at 11.
The Examiner finds, however, Eilert teaches or suggests these missing
limitations. Final Act. 11–12, 39–40 (citing Eilert ¶¶ 12, 14). In particular,
Eilert discloses:
In an embodiment, techniques and/or architecture to
perform one or more transactions may provide a benefit of
reducing software complexity and/or memory overhead of an
operating system, for example, by remapping physical memory
during a process of performing the transactions. Such
transactions may comprise a set of instructions or operators to
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be performed in atomic fashion as a single operation. Here, a
transaction performed in an “atomic fashion” refers to a
transaction that is not to be partially completed, but is either fully
carried out or the transaction fails leaving the prior state intact.
For example, a transaction may comprise a plurality of
instructions or operators to write particular information to a
memory. Such a transaction may comprise a begin-event and an
end-event, which is called a “commit”. As just mentioned, such
a transaction may not be partially completed but may either be
performed completely and successfully or fail. In other words,
either all or none of the instructions or operators of a transaction
may be successfully executed.
Eilert ¶ 12 (emphases added); see id. ¶ 14 (“Such software and/or hardware
may also be used to execute atomic transactions, as explained in detail
below.”). Thus, the Examiner finds Eilert teaches or suggests that
transactions may include a begin-event, a set of instructions, and an end-
event. The Examiner further finds Eilert teaches or suggests that hardware
and/or software may perform such transactions in an atomic fashion, that is,
either completely or not at all. Final Act. 11–12. Moreover, the Examiner
finds a person of ordinary skill in the relevant art would have had reason to
combine the teachings of Moraru and Eilert “to perform one or more
transactions[, which] may provide a benefit of reducing software complexity
and/or memory overhead of an operating system, for example, by remapping
physical memory during a process of performing the transactions” and,
thereby, to achieve the apparatus of claim 1. Id. at 12.
Appellant contends the Examiner errs in rejecting claim 1 for three
reasons. See Appeal Br. 9–17. As discussed below, we are not persuaded
the Examiner errs.
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1. Missing Final “Wherein” Clause
First, Appellant contends Eilert fails to teach or suggest the final
“wherein” clause, as recited in claim 1. Appeal Br. 9–15; see Reply Br. 2–5.
In particular, Appellant contends the Examiner “concludes that ‘[a] memory
write operation by an executing instruction obviously occurs in a designated
memory address specified by the write instruction.’ But the reference to ‘an
executing instruction’ wrongly suggests ‘instruction execution’ by a
processor core.” Appeal Br. 9 (quoting Final Act. 12). More specifically,
Appellant contends:
In claim 1, a certain part of memory (“the predetermined
portion of the memory”) is afforded special protection such that
it cannot be written to (by the action of “a pending write
instruction”) unless the pending write instruction is preceded by
a begin instruction and followed by an end instruction in the
“sequence of instructions” executed by the processor core.6
Reply Br. 2–3 (italics added).
Claim 1 recites that “a processor core [is] capable of performing data
processing operations in response to a sequence of instructions.” Appeal

6 Although claim 1 recites, “a write-back cache capable of storing local
copies of the data items retrieved from the memory and written to the
memory by the processor core when executing the sequence of instructions”
(Appeal Br. 18 (emphasis added)), claim 24 recites “means for storing local
copies of the data items retrieved from the memory and written to the
memory when executing the sequence of instructions, wherein the means for
storing has a write-back configuration with respect to the memory” (id. at 24
(emphasis added). See also id. at 24 (limitation of claim 24 corresponding to
that of claim 23). The Examiner interprets claim 24 to recite that the write-
back memory structure, e.g., L1 cache, performs this function. Final Act. 3;
see, e.g., Spec., 2:17–19 (“storing local copies in a write-back cache of the
data items retrieved from the memory and written to the memory when
executing the sequence of instructions”). Appellant does not challenge this
interpretation. See supra note 5.
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Br. 18 (emphases added). Claim 1 further recites, “the processor core is
capable of responding to an end instruction in the sequence of instructions
by [performing certain actions].” Id. (emphasis added); see Spec. 2:5–10,
4:19–29. Thus, although claim 1 recites that the processor core is capable of
performing operations “in response to a sequence of instructions,” the claim
only specifies such a response capability with respect to “an end
instruction.” Cf., e.g., Spec., 6:6–15.
Claim 1 recites two particular actions, which the processor core is
capable of taking in “responding to an end instruction in the sequence of
instructions,” namely, “causing the local copies of data items . . . to be
cleaned from the write-back cache to the memory” and “clearing the
indications of the write operations stored in the storage unit.” Appeal Br. 18
(Claims App.); see, e.g., Spec., 12:31–13:1 (“an explicit command is
received by the L1 cache [of CPU 12] to ‘clean’ this data item”). Claim 1,
however, does not recite that the core processor receives any of “the
sequence of instructions,” as opposed, for example, to the core processor
accessing, generating, or merely reacting to all or any of “the sequence of
instructions.” Nor does Appellant identify where the Specification discloses
that the processor core receives “the sequence of instructions.” Thus, we
understand the processor core’s “response to a sequence of instructions,”
and, in particular, the processor core “responding to an end instruction,” to
encompass an action in reaction to the occurrence of such an instruction or
instructions.
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Eilert’s Figure 2, which depicts a state diagram of transactions,
according to an embodiment of the disclosed transactional memory, is
reproduced below.

Figure 2 depicts a series of commands for transactions 0–2 sent from
system 200 to memory subsystem 210. Eilert ¶ 23; see Ans. 3. Each
transaction is bracketed by begin and end instructions. See Eilert ¶ 22,
Fig. 1 (depicting “Begin” instruction 110 and “End” instruction 130). In
Figure 2, “Begin Transaction 0” command is sent from system 200 to
memory subsystem 210, followed by “Transaction 0, Operation A,”
“Transaction 0, Operation B,” and “End Transaction 0” commands. Id. ¶ 23.
Eilert discloses, “[u]pon receiving an end portion of a transaction command
for transaction 0 from system 200, memory subsystem 210 may determine
whether transaction 0 successfully completed or failed. In either case,
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memory subsystem 210 may inform system 200 of such outcome.” Id.
Specifically, Figure 2 depicts memory subsystem 210 sends “Transaction 0
status” message to system 200. Id., Fig. 2. In response (or reaction) to the
“Transaction 0 status” message, which is triggered by “End Transaction 0”
command, system 200 may send “Begin Transaction” commands for
transactions 1 and/or 2. See id. ¶ 24, Fig. 2.
The Examiner finds Eilert’s “transactions are atomic operation[s]. If a
group of instruction[s] is not preceded by ‘begin’ event and followed by
‘end’ event, it is not a complete transaction. Therefore, it is obvious, the
system will prevent execution of a partial transaction, i.e., an incomplete
transaction will not be committed.” Final Act. 40. Further, the Examiner
finds:
From ¶0023 of Eilert specification: “Such transactions, as
mentioned above, may be initiated by a host or system 200 and
performed by a memory subsystem 210. For example, such a
host or system 200 may comprise a computing platform
executing an application and memory subsystem 210 may
comprise one or more memory devices.” From this recitation,
it is clear the system comprising a computing platform is
executing an application with the transactional instructions. It
is implied that a computing platform would have processor to
execute instructions. A transaction comprises a set of operations
encapsulated by begin and end instruction, Ref. Fig. 1 of Eilert.
Therefore, performing a transaction is equated with executing
the set of operations of that transaction.
Ans. 3–4 (italics added); see also Eilert ¶ 29 (“It is recognized that all or part
of the various devices shown in system 500, and the processes and methods
as further described herein, may be implemented using or otherwise
including hardware, firmware, software, or any combination thereof.”).
Thus, the Examiner finds Eilert teaches or suggests a processor core
executes such a sequence or instructions. See KSR Int’l Co. v. Teleflex Inc.,
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550 U.S. 398, 418 (2007) (“As our precedents make clear, however, the
analysis need not seek out precise teachings directed to the specific subject
matter of the challenged claim, for a court can take account of the inferences
and creative steps that a person of ordinary skill in the art would employ.”).
The Examiner’s findings are persuasive.
Appellant further contends neither Moraru nor Eilert teaches or
suggests a “hardware level protection mechanism,” such as the recited
processor core, that “prevent[s] a write operation to the predetermined
portion of the memory from being performed when a pending write
instruction specifying the predetermined portion of the memory is not
preceded by the begin instruction and followed by the end instruction.”
Appeal Br. 11 (quoting claim 1). Specifically, Appellant contends, “both
Eilert and Moraru [] focus on ensuring that certain groups of memory
actions are carried out atomically, meaning that either all memory actions in
a group take effect or none take effect.” Id. Thus, Appellant contends both
Moraru and Eilert teach or suggest actions taken by the memory, not by the
processor core.
The Examiner finds claim 1 is not limited to hardware level protection
mechanisms. Ans. 4. In particular, claim 1 recites “a processor core
capable of performing data processing operations in response to a sequence
of instructions, wherein the data processing operations comprise read
operations which retrieve data items from a memory and write operations
which write data items to the memory.” Appeal Br. 18 (Claims App.)
(emphases added). Thus, we agree with the Examiner that the recited
limitation of claim 1 encompasses software applications executing on a
processor core. Ans. 4; see Spec., 5:29–6:2 (describing instructions
provided by a “programmer”). Moreover, as discussed above, Eilert
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discloses that its memory transactions are performed by hardware and/or
software. Eilert ¶¶ 23, 29, Fig. 2.
Further, Eilert discloses its memory transactions
may comprise a set of instructions or operators to be performed
in atomic fashion as a single operation. Here, a transaction
performed in an “atomic fashion” refers to a transaction that is
not to be partially completed, but is either fully carried out or the
transaction fails leaving the prior state intact.
Eilert ¶ 12 (emphasis added); see also Moraru ¶ 14 (“data writes to memory
of an atomic transaction are either all applied to persistent data or none
are”). Eilert also discloses that the transaction requires a begin-event and an
end-event in order to be completed. Eilert ¶¶ 12, 15, 22, 23, Figs. 1, 2.
Thus, the Examiner finds Eilert teaches or suggests, “preventing a write
operation to the predetermined portion of the memory from being performed
when a pending write instruction specifying the predetermined portion of the
memory is not preceded by the begin instruction and followed by the end
instruction.” Final Act. 40.
Appellant contends, however, that the methods of claim 1 and the
combined teachings of Moraru and Eilert take different approaches to the
begin and end instructions. Appeal Br. 13. Appellant’s tables, identifying
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the allegedly different approaches taken by Moraru and Eilert as compared
to the approach taken by Appellant’s application, are reproduced below.

Appeal Br. 13.
Referring to these tables, Appellant acknowledges that under each
approach, if the begin instruction precedes the write instruction, but an end
instruction does not follow the write instruction, the write operation to the
predetermined portion of the memory is prevented. Appeal Br. 13–15.
Appellant also acknowledges that under each approach, if the begin
instruction precedes the write instruction and an end instruction follows the
write instruction, the write operation to the predetermined portion of the
memory is not prevented. Id.
Appellant contends, however, that
Moraru and Eilert do not teach that an “isolated” write
instruction, in which a begin instruction does not precede the
write instruction and in which an end instruction does not follow
the write instruction, is prevented [see *NO* in the table] from
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causing a write operation to the predetermined portion of
memory.
Appeal Br. 13–14.
The Examiner finds, however, that neither Moraru nor Eilert teaches
or suggests that “isolated” memory operations are allowed. Ans. 7 (citing
Moraru, Fig. 4, and Eilert, Fig. 2). In particular, the Examiner finds Eilert
discloses that portions of a transaction are treated as incomplete operations
until they are committed, and a committed transaction requires a begin-event
and an end-event. Id. (citing Eilert ¶¶ 12, 15); see Moraru, Fig. 4 (depicting
a “heap_begin” instruction and a “heap_close” instruction bracketing an
instruction to write to a mapped memory area). Thus, we are persuaded that,
like Appellant’s approach, Moraru and Eilert together teach or suggest that if
both begin and end instructions are missing, or if only the begin instruction
is missing, the write operation to the predetermined portion of the memory is
prevented, and Appellant’s table depicting the approach of Moraru and Eilert
is incorrect. See Ans. 8.
Appellant still further contends:
Given that the technology recited in claim 1 recites a very
different mechanism from the memory ordering and heap
grouping of Moraru and the transactional memory grouping of
memory operations in Eilert, the claimed technology cannot be
viewed as obvious based on the teachings in Moraru and Eilert.
Together, Moraru and Eilert teach that certain groups of memory
operations can be ensured to be performed atomically. But these
atomic memory operations do not teach a processor core
protecting the claimed “predetermined [portion] of memory.”
Appeal Br. 12; see id. at 10–12 (discussing protecting “a predetermined
portion of memory”).
The Examiner disagrees and finds, with respect to Figure 2,
reproduced above, Eilert discloses:
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For an example of a single transaction, transaction 0 may begin
by system 200 providing a begin portion of transaction command
for transaction 0. In response, memory subsystem 210 may
prepare to receive and execute subsequent transaction
operators, such as operator A and operator B. . . . Upon receiving
an end portion of a transaction command for transaction 0 from
system 200, memory subsystem 210 may determine whether
transaction 0 successfully completed or failed.
Eilert ¶ 23 (emphasis added); see id. ¶ 14 (“For example, relatively large
memory subsystems may include software and/or hardware by which pages
or sectors of the memory subsystem may be remapped to isolate defective
portions of memory and/or to ensure comparable levels of wear across
relatively large portions of memory space.”). Further, the Examiner finds,
with respect to Figure 4, discussed above, Moraru discloses, “[t]he
application initiates a data transaction at line 406 using the heap, and writes
to the mapped area in line(s) 408.” Ans. 5 (quoting Moraru ¶ 62). The
Examiner finds, “[a] mapped area is a predetermined area of the memory
before execution of the instruction. The write operations are performed in
that mapped [i.e., predetermined] portion of the memory.” Id. For the
above reasons, we agree with the Examiner that Eilert, alone or in view of
Moraru, teaches or suggests protecting, e.g., preventing, writing data to a
predetermined portion of the memory, “when a pending write instruction
specifying the predetermined portion of the memory is not preceded by the
begin instruction and followed by the end instruction.” See Appeal Br. 19
(Claims App.).
Consequently, Appellant does not persuade us the Examiner errs in
finding Eilert, alone or in view of Moraru, teaches or suggest the final
“wherein” clause of claim 1.
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2. Eilert’s “Instructions” Are Not Instructions For the Processor Core
Second, Appellant contends, “claim 1 is clear that the ‘pending write
instruction,’ the ‘begin instruction,’ and the ‘end instruction’ are part of the
‘sequence of instructions’ that the processor core receives and responds to.”
Appeal Br. 15 (emphasis added). As discussed above, however, claim 1
does not recite and Appellant does not show where the Specification
discloses that the processor core receives the “sequence of instructions.” See
supra Section 1. As we explained above, we understand the processor
core’s “response to a sequence of instructions,” and, in particular, the
processor core “responding to an end instruction,” to encompass an action in
reaction to the occurrence of such an instruction or instructions.
Consequently, Appellant does not persuade us the Examiner errs in
finding Eilert, alone or in view of Moraru, teaches or suggest the “sequence
of instructions” of claim 1. Ans. 7–8 (citing Eilert ¶¶ 12, 15, Fig. 2, as well
as Moraru ¶ 14, Fig. 4).
3. The Examiner Misinterprets Eilert’s “Complete” Transaction
Third, Appellant contends,
Eilert may “complete,” and thereafter, receive the “end portion
of a transaction command” from the system 200 by memory
subsystem 210. As a result, it is not correct to assert that the
absence of an “end” in Eilert necessary means “an incomplete
transaction.” [Eilert’s] Paragraphs [0023-24] make clear that a
“transaction” can “complete” before an “end portion” is
received. That means that transaction completion in Eilert is not
contingent on reception of an end portion by the memory
subsystem 210.
Appeal Br. 16–17. For the following reasons, we disagree with Appellant.
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As noted above, Eilert discloses:
Such transactions may comprise a set of instructions or operators
to be performed in atomic fashion as a single operation. Here, a
transaction performed in an “atomic fashion” refers to a
transaction that is not to be partially completed, but is either fully
carried out or the transaction fails leaving the prior state intact.
Eilert ¶ 12 (emphasis added). Further, Eilert discloses:
Such a transaction may comprise a begin-event and an end-
event, which is called a “commit”. As just mentioned, such a
transaction may not be partially completed but may either be
performed completely and successfully or fail. In other words,
either all or none of the instructions or operators of a transaction
may be successfully executed.
Id. (emphases added). Thus, the Examiner finds Eilert teaches or suggests
that a transaction, including a set of instructions, must include a begin-event
and an end-event in order to be performed completely. Final Act. 40;
Ans. 8. For the above reasons, we agree with the Examiner.
Consequently, Appellant does not persuade us the Examiner errs in
interpreting Eilert’s teachings regarding a “complete” transaction.
In view of the foregoing analysis, we are not persuaded the Examiner
errs in rejecting independent claim 1 as obvious over the combined teachings
of Moraru and Eilert, and we sustain the Examiner’s rejection of that claim.
We also are not persuaded the Examiner errs in rejecting independent
claims 23 and 24, which are not challenged separately, as obvious over the
combined teachings of Moraru and Eilert. See Final Act. 16–29. Appellant
does not challenge the rejection of any of claims 11–13 or 15–19 separately
from the challenge to claim 1. Appeal Br. 9; see Ans. 3–8. Consequently,
we also sustain the rejection of those claims.
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Remaining Rejections
As noted above, the Examiner rejects claims 2, 6–10, 14, and 20–22
as obvious over the combined teachings of Moraru, Eilert, and one or more
of Talagala, Rajwar, Cain, Akkary, and Boehm. Appellant does not
challenge the rejection of any of those claims separately from the challenge
to independent claim 1. Consequently, we also sustain the rejections of
those claims. See supra note 5.
DECISION
1. The Examiner does not err in rejecting
a. claims 1, 11–13, 15–19, 23, and 24 as obvious over the
combined teachings of Moraru and Eilert;
b. claim 2 as obvious over the combined teachings of Moraru,
Eilert, and Talagala;
c. claims 6–8 as obvious over the combined teachings of Moraru,
Eilert, and Rajwar;
d. claims 9 and 10 as obvious over the combined teachings of
Moraru, Eilert, and Cain;
e. claims 14, 20, and 22 as obvious over the combined teachings
of Moraru, Eilert, and Akkary; and
f. claim 21 under 35 U.S.C. § 103 as obvious over the combined
teachings of Moraru, Eilert, Akkary, and Boehm.
2. Thus, on this record, claims 1, 2, and 6–24 are not patentable.
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CONCLUSION
We affirm the Examiner’s rejections of claims 1, 2, and 6–24.
In summary:
Claim(s)
Rejected
35 U.S.C.
§
Reference(s)/
Basis
Affirmed Reversed
1, 11–13,
15–19, 23,
24
103 Moraru, Eilert 1, 11–13,
15–19, 23,
24

2 103 Moraru, Eilert,
Talagala
2
6–8 103 Moraru, Eilert,
Rajwar
6–8
9, 10 103 Moraru, Eilert,
Cain
9, 10
14, 20, 22 103 Moraru, Eilert,
Akkary
14, 20, 22
21 103 Moraru, Eilert,
Akkary, Boehm
21
Overall
Outcome
1, 2, 6–24
No time period for taking any subsequent action in connection with
this appeal may be extended under 37 C.F.R. § 1.136(a). See 37 C.F.R.
§ 1.136(a)(1)(iv) (2013).
AFFIRMED