ARM LIMITED

Patent Trials and Appeals Board

Apr 29, 2021

2020000974 (P.T.A.B. Apr. 29, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
15/019,069 02/09/2016 Matthew Lucien EVANS JRL-550-1952 9964
73459 7590 04/29/2021
NIXON & VANDERHYE, P.C.
901 NORTH GLEBE ROAD, 11TH FLOOR
ARLINGTON, VA 22203
EXAMINER
YOON, ALEXANDER J
ART UNIT PAPER NUMBER
2135
NOTIFICATION DATE DELIVERY MODE
04/29/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
PTOMAIL@nixonvan.com
pair_nixon@firsttofile.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

Ex parte MATTHEW LUCIEN EVANS
____________

Appeal 2020-000974
Application 15/019,069
Technology Center 2100
____________

Before JOHN A. JEFFERY, KRISTEN L. DROESCH, and JOHN A.
EVANS, Administrative Patent Judges.

JEFFERY, Administrative Patent Judge.

DECISION ON APPEAL
Under 35 U.S.C. § 134(a), Appellant1 appeals from the Examiner’s
decision to reject claims 1–16. We have jurisdiction under 35 U.S.C. § 6(b).
We REVERSE.

1 We use the word “Appellant” to refer to “applicant” as defined in 37
C.F.R. § 1.42. Appellant identifies the real party in interest as ARM
Limited. Appeal Br. 3.
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STATEMENT OF THE CASE
Appellant’s invention is a memory management unit (MMU) for
receiving and responding to (1) an address translation request; and (2) a
translated access request, from a requesting device. See Spec. 5. The
address translation request is not a request for memory access, but rather
specifies a virtual address for translation. Id. The MMU translates the
virtual address to an intermediate address and provides the intermediate
address to the requesting device. Id. Claim 1 is illustrative:
1. A memory management unit comprising:
an interface configured to receive an advance address
translation request from a device, the advance address
translation request specifying a virtual address to be
translated, the virtual address corresponding to a memory
location to be accessed at a later time in response to a
subsequent translated access request received from the device,
where said memory location corresponding to the virtual
address is not accessed in response to the advance address
translation request; and
translation circuitry configured to translate the virtual
address specified by the advance address translation request
into an intermediate address different from a physical address
directly specifying said memory location;
wherein the interface is configured to provide an address
translation response comprising the intermediate address to the
device in response to the advance address translation request.

THE REJECTIONS
The Examiner rejected claims 1–11 and 13–16 under 35 U.S.C. § 103
as unpatentable over Devaraj (US 2013/0013889 A1; published Jan. 10,
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2013), Case (US 7,278,008 B1; issued Oct. 2, 2007), and Isloorkar (US
2014/0156930 A1; published June 5, 2014). Non-Final Act. 3–10.2
The Examiner rejected claim 12 under 35 U.S.C. § 103 as
unpatentable over Devaraj, Case, Isloorkar, and Symes (US 2004/0105298
A1; published June 3, 2004). Non-Final Act. 10–11.

THE OBVIOUSNESS REJECTION OVER DEVARAJ, CASE, AND
ISLOORKAR
Regarding independent claim 1, the Examiner finds that Devaraj
discloses a memory management unit configured to (1) receive an address
translation request including a virtual address from a device, and (2)
translate the virtual address into an intermediate address. Non-Final Act. 3.
Although the Examiner acknowledges that Devaraj’s virtual address does
not correspond to a memory location that is not accessed responsive to the
address translation request, the Examiner cites Case as teaching this feature.
Non-Final Act. 3–4. The Examiner also acknowledges that Devaraj lacks,
but Case and Isloorkar collectively teach, providing a response to the
address translation request, comprising the intermediate address to the
device in concluding that the claim would have been obvious. Id.
Appellant argues the Examiner’s combination is improper not only
because Devaraj, Case, and Isloorkar collectively fail to disclose returning
an intermediate physical address back to the requesting device, but also
because the proposed combination would lead an ordinarily skilled artisan

2 Throughout this opinion, we refer to (1) the Non-Final Rejection mailed
December 13, 2018 (“Non-Final Act.”); (2) the Appeal Brief filed May 13,
2019 (“Appeal Br.”); (3) the Examiner’s Answer mailed September 17, 2019
(“Ans.”); and (4) the Reply Brief filed November 18, 2019 (“Reply Br.”).
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away from the claimed invention (Appeal Br. 7–9; Reply Br. 4–5), and is
based on improper hindsight reconstruction (Reply Br. 2–3).

ISSUES
I. Under § 103, has the Examiner erred in rejecting claim 1 by finding
that Devaraj, Case, and Isloorkar collectively would have taught or
suggested providing an address translation response comprising an
intermediate address to a device in response to an advance address
translation request sent from that device?
II. Is the Examiner’s proposed combination of the cited references
supported by articulated reasoning with some rational underpinning to
justify the Examiner’s obviousness conclusion? This issue turns on whether
the Examiner’s proposed combination (1) teaches away from the claimed
invention; and (2) is based on impermissible hindsight reconstruction.

ANALYSIS
We begin by noting that the Examiner’s reliance on Devaraj to teach
the claimed memory management unit (1) receiving an address translation
request specifying a virtual address for translation from a device, and (2)
translating the virtual address into an intermediate address different from a
physical address is undisputed. See Non-Final Act. 3 (citing Devaraj ¶ 60).
Also, the Examiner’s reliance on Case to teach the virtual address
corresponding to a memory location to be (1) accessed at a later time; and
(2) not accessed responsive to the advance address translation request is also
undisputed. See Non-Final Act. 4 (citing Case col. 24, ll. 4–9).
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As noted above, this dispute turns principally on the Examiner’s
reliance on Case and Isloorkar for teaching providing an address translation
response comprising the intermediate address to the device responsive to the
advance address translation request sent from that device. Therefore, we
confine our discussion to Case and Isloorkar in resolving this particular
issue.
As noted above, the rejection relies upon Case and Isloorkar for
collectively teaching providing a response to the address translation request,
comprising the intermediate address, to the device as claimed. See Non-
Final Act. 4. Specifically, Case is relied upon for teaching providing a
response to the address translation request, comprising the address, to the
device, and Isloorkar is relied upon for teaching an intermediate physical
address being returned. See Non-Final Act. 4 (citing Case col. 24, ll. 4–9
and Isloorkar ¶ 84).
On this record, we agree with Appellant that the Examiner’s rejection
of claim 1 relying on the Case and Isloorkar collectively to provide an
address translation response comprising the intermediate address to the
device requesting that translation is problematic. See Appeal Br. 7–8.
Although the Examiner finds (see Non-Final Act. 4), and Appellant
apparently admits (see Appeal Br. 7), that Case returns an address to the
device that requested an advance address translation, Case does not return an
intermediate physical address. Further, while the Examiner finds (see Non-
Final Act. 4), and Appellant does not dispute, that Isloorkar’s address
translation stages include translation from a virtual address to an
intermediate physical address (IPA), Isloorkar’s IPA is used within a stage
of translating the IPA to a physical address, and is not returned to a
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requesting device. See Isloorkar ¶¶ 82–84. Therefore, we fail to see—nor
has the Examiner shown—that Isloorkar’s intermediate physical address is
returned to the requesting device as claimed.
Nor is this deficiency cured by the Examiner’s proposed modification
which, on this record, is based on impermissible hindsight reconstruction of
the invention. See In re Fritch, 972 F.2d 1260, 1266 (Fed. Cir. 1992) (“It is
impermissible to use the claimed invention as an instruction manual or
‘template’ to piece together the teachings of the prior art so that the claimed
invention is rendered obvious . . . .”).
To be sure, any judgment on obviousness is in a sense necessarily a
reconstruction based on hindsight reasoning, so long as it takes into account
only knowledge which was within the level of ordinary skill in the art at the
time the claimed invention was made and does not include knowledge
gleaned only from Appellant’s disclosure, such a reconstruction is proper.
In re McLaughlin, 443 F.2d 1392, 1395 (CCPA 1971). But here, the
Examiner concludes that it would have been obvious for an ordinarily skilled
artisan to perform translations ahead of a subsequent data access, as
identified by the Applicant, to improve performance by reducing memory
management contention. Non-Final Act. 4. Our emphasis underscores the
sole justification for the Examiner’s proposed enhancement is Appellant’s
own disclosure which, as noted above, is impermissible hindsight
reconstruction. See id.; see also Fritch, 972 F.2d at 1266.
We reach this conclusion despite the fact that the cited references do
not teach away from the claimed invention contrary to Appellant’s
contentions (see Appeal Br. 9–11; Reply Br. 4–5), for nothing on this record
indicates that the cited references criticize, discredit, or otherwise discourage
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investigation into the invention claimed as required for teaching away. See
Norgren Inc. v. Int’l Trade Comm’n, 699 F.3d 1317, 1326 (Fed. Cir. 2012);
see also In re Kahn, 441 F.3d 977, 990 (Fed. Cir. 2006).
Although Appellant asserts that the Examiner’s proposed
combination requires more address translation in advance, and thus degrades
system performance (see Appeal Br. 10–11), the Examiner nonetheless finds
that advance address translation provides efficiency advantages by reducing
steps required for later translations. Ans. 4. Nevertheless, despite
Appellant’s arguments to the contrary (Appeal Br. 9–11), we do not find that
the cited references criticize, discredit, or discourage returning an
intermediate address instead of a physical address, even assuming, without
deciding, that this proposed alternative was somehow inferior.
Furthermore, Appellant’s contentions that there is ostensibly no
reasonable basis to modify Case because such a modification would include
Isloorkar’s cache and Case’s returning of a physical address, and an
intermediate address would not be returned to the device (see Appeal Br. 8–
9), are inconsistent with the Examiner’s proposed combination. It is well
settled that the test for obviousness is not whether the features of one
reference may be bodily incorporated into another cited reference as
Appellant apparently suggests. See In re Keller, 642 F.2d 413, 425 (CCPA
1981). Nor does an obviousness determination based on teachings from
multiple references require an actual, physical substitution of elements. In
re Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012) (citing In re Etter, 756
F.2d 852, 859 (Fed. Cir. 1985)). Rather, the test for obviousness is what the
combined teachings of the references would have suggested to a person of
ordinary skill in the art. Mouttet, 686 F.3d at 1333; see also Manual of
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Patent Examining Procedure (MPEP) § 2145(IV) (9th ed. rev. 10.2019 June
2020). Therefore, although the Examiner’s rejection is erroneous,
Appellant’s arguments that are apparently premised on the Examiner’s
rejection bodily incorporating features from one reference into another are
nonetheless unavailing.
We reach our conclusion despite an apparent engineering tradeoff
implicated by the Examiner’s proposed combination, namely possible
efficiency improvements that may result from storing partial translations in
advance in light of Islookar’s paragraph 30 that is relied upon for the first
time in the Examiner’s Answer. See Ans. 4. Islookar’s paragraph 30
explains that it may be advantageous to store partial translations because
retrieving translations from memory is a lengthy process requiring several
steps or walks. Storing partial translations, however, reduces the steps
required for later translations. Islookar ¶ 30.
According to the Examiner, ordinarily skilled artisans would
recognize from this passage that providing partial translations has efficiency
advantages. Ans. 4. Although this passage’s applicability to the proposed
combination is not entirely clear on this record, presumably if a partial (i.e.,
intermediate) physical address were sent to the requestor instead of a
complete physical address under the Examiner’s proposed combination in
light of Islookar’s paragraph 30, future translation efficiency would
apparently be improved because, among other things, the same data could
perhaps be reused for other, future translations. See id.
But because Case’s system exposes a physical address—an exposure
that must be avoided for security reasons as Appellant indicates (Appeal Br.
10–11)—security is a critical factor that the Examiner’s proposed efficiency
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improvements in light of Islookar’s paragraph 30 do not consider. That is,
even assuming, without deciding, that the proposed combination would be
more efficient by providing partial translations to the requesting device in
the form of intermediate addresses as the Examiner seems to suggest (see
Ans. 4), we cannot say—nor has the Examiner shown—that the resulting
compromises in security would amount to an engineering tradeoff to
ordinarily skilled artisans to yield an obvious modification. See Mouttet,
686 F.3d at 1330. Rather, despite its apparent efficiency advantages, the
Examiner’s proposed combination could still have significant security
vulnerabilities that could adversely affect the system’s integrity. The
Examiner’s proposed combination is, therefore, problematic for that
additional reason.
Therefore, we are persuaded that the Examiner erred in rejecting (1)
independent claim 1; (2) independent claims 14–16 that recite commensurate
limitations; and (3) dependent claims 2–11 and 13 for similar reasons.
Because this issue is dispositive regarding our reversing the Examiner’s
rejection of these claims, we need not address Appellant’s other associated
arguments.

THE OTHER OBVIOUSNESS REJECTION
We also do not sustain the Examiner’s obviousness rejection of
claim 12. See Non-Final Act. 10–11. Because the Examiner has not shown
that Symes cures the foregoing deficiencies regarding the rejection of
independent claim 1, we will not sustain the obviousness rejection of
dependent claim 12 for similar reasons.

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CONCLUSION
In summary:
Claims
Rejected
35 U.S.C. § Reference(s)/
Basis
Affirmed Reversed
1–11, 13–
16
103 Devaraj, Case,
Isloorkar
1–11, 13–16
12 103 Devaraj, Case,
Isloorkar,
Symes
12
Overall
Outcome
1–16

REVERSED