ARBOR GLOBAL STRATEGIES LLC,

Patent Trials and Appeals Board

Mar 2, 2022

IPR2020-01570 (P.T.A.B. Mar. 2, 2022)

Trials@uspto.gov Paper 40 571-272-7822 Entered: March 2, 2022 UNITED STATES PATENT AND TRADEMARK OFFICE ____________ BEFORE THE PATENT TRIAL AND APPEAL BOARD ____________ XILINX, INC., Petitioner, v. ARBOR GLOBAL STRATEGIES, LLC, Patent Owner. ____________ IPR2020-015701 Patent RE42,035 E ____________ Before KARL D. EASTHOM, BARBARA A. BENOIT, and SHARON FENICK, Administrative Patent Judges. EASTHOM, Administrative Patent Judge. JUDGMENT Final Written Decision Determining All Challenged Claims Unpatentable 35 U.S.C. § 318(a) 1 Taiwan Semiconductor Manufacturing Co. Ltd. (“TSMC”) filed a petition in IPR2021-00737, and the Board joined it as a party to this proceeding. See also Paper 39 (order dismissing-in-part TSMC as a party with respect to claims 1, 3, 5-9, 11, 13-17, 19-22, 25, 26, 28, and 29). IPR2020-01570 Patent RE42,035 E 2 Xilinx, Inc. (“Petitioner”) filed a Petition (Paper 2, “Pet.”) requesting an inter partes review of claims 1-38 (the “challenged claims”) of U.S. Patent No. RE42,035 B2 (Ex. 1001, the “’035 patent”). Pet. 1. Petitioner filed a Declaration of Dr. Paul Franzon (Ex. 1002) with its Petition. Arbor Global Strategies LLC (“Patent Owner”) filed a Preliminary Response (Paper 8, “Prelim. Resp.”). After the Institution Decision (Paper 13, “Inst. Dec.”), Patent Owner filed a Patent Owner Response (Paper 19, “PO Resp.”) and a Declaration of Dr. Shukri J. Souri (Ex. 2011); Petitioner filed a Reply (Paper 23) and a Reply Declaration of Dr. Paul Franzon (Ex. 1070); and Patent Owner filed a Sur-reply (Paper 27). Thereafter, the parties presented oral arguments via a video hearing (Dec. 3, 2021), and the Board entered a transcript into the record. Paper 33 (“Tr.”). For the reasons set forth in this Final Written Decision pursuant to 35 U.S.C. § 318(a), we determine that Petitioner demonstrates by a preponderance of evidence that the challenged claims are unpatentable. I. BACKGROUND A. Real Parties-in-Interest Petitioner identifies Xilinx, Inc. as the real party-in-interest. Pet. 72. Patent Owner identifies Arbor Global Strategies LLC. Paper 5, 1. Joined party Taiwan Semiconductor Manufacturing Co. Ltd. is also a real party-in- interest. See supra note 1. B. Related Proceedings The parties identify Arbor Global Strategies LLC, v. Xilinx, Inc., No. 19-CV-1986-MN (D. Del.) (filed Oct. 18, 2019) as a related infringement action involving the ’035 patent and three related patents, IPR2020-01570 Patent RE42,035 E 3 U.S. Patent No. 7,282,951 B2 (the “’951 patent”), U.S. Patent No. 6,781,226 B2 (the “’226 patent”) and U.S. Patent No. 7,126,214 B2 (the “’214 patent”). See Pet. 72-73; Paper 5. Petitioner “contemporaneously fil[ed] inter partes review (IPR)] petitions challenging claims in each of these patents,” namely IPR2020-01567 (challenging the ’214 patent), IPR2020-01568 (challenging the ’951 patent), and IPR2020-01571 (challenging the ’226 patent). See Pet. 72. Final written decisions for these three cases issue concurrently with the instant Final Written Decision. The parties also identify Arbor Global Strategies LLC v. Samsung Electronics Co., Ltd., 2:19-cv-00333-JRG-RSP (E.D. Tex.) (filed October 11, 2019) as a related infringement action involving the ’035, ’951, and ’226 patents. Subsequent to the complaint in this district court case, Samsung Electronics Co., Ltd. (“Samsung”) filed petitions challenging the three patents, and the Board instituted on all challenged claims, in IPR2020- 01020, IPR2020-01021, and IPR2020-01022. See IPR2020-01020, Paper 11 (decision instituting on claims 1, 3, 5-9, 11, 13-17, 19-22, 25, 26, 28, and 29 of the ’035 patent); IPR2020-01021, Paper 11 (decision instituting on claims 1, 4, 5, 8, 10, and 13-15 the ’951 patent); IPR2020-01022, Paper 12 (decision instituting on claims 13, 14, 16-23, and 25-30 of the ’226 patent). The Board recently issued final written decisions in the three Samsung cases, determining all challenged claims unpatentable. See IPR2020-01020, Paper 30 (holding unpatentable claims 1, 3, 5-9, 11, 13-17, 19-22, 25, 26, 28, 29 of the ’035 patent); IPR2020-01021, Paper 30 (holding unpatentable claims 1, 4, 5, 8, 10, and 13-15 of the ’951 patent); IPR2020-01022, Paper 34 (holding unpatentable claims 13, 14, 16-23, and 25-30 of the ’226 IPR2020-01570 Patent RE42,035 E 4 patent). The Board joined Taiwan Semiconductor Manufacturing Co. Ltd. as a party in each of the prior proceedings as it did here. C. The ’035 patent The ’035 patent describes a stack of integrated circuit (“IC”) die elements including a field programmable gate array (“FPGA”) on a die, a memory on a die, and a microprocessor on a die. Ex. 1001, code (57), Fig. 4. Multiple contacts traverse the thickness of the die elements of the stack to connect the gate array, memory, and microprocessor. Id. According to the ’035 patent, this arrangement “allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element while advantageously increasing final assembly yield and concomitantly reducing final assembly cost.” Id. Figure 4 follows: IPR2020-01570 Patent RE42,035 E 5 Figure 4 above depicts a stack of dies including FPGA die 66, memory die 66, and microprocessor die 64, interconnected using contact holes 70. Ex. 1001, 4:6-20. The ’035 patent explains that an FPGA provides known advantages as part of a “reconfigurable processor.” See Ex. 1001, 1:17-32. Reconfiguring the FPGA gates alters the “hardware” of the combined “reconfigurable processor” (e.g., the processor and FPGA) making the processor faster than one that simply accesses memory (i.e., “the conventional ‘load/store’ paradigm”) to run applications. See id. Such a “reconfigurable processor” also provides a known benefit of flexibly providing different types of different logical units required by an application after manufacture or initial use. See id. D. Illustrative Claims 1 and 23 Independent claims 1 and 23 illustrate the challenged claims at issue: 1. A processor module comprising: [1.1] at least a first integrated circuit die element including a programmable array; [1.2] at least a second integrated circuit die element stacked with and electrically coupled to said programmable array of said first integrated circuit die element; and [1.3] wherein said first and second integrated circuit die elements are electrically coupled by a number of contact points distributed throughout the surfaces of said die elements, and [1.4] wherein said contact points traverse said die elements through a thickness thereof. Ex. 1001, 6:11-22. 23. A programmable array module comprising: [23.1] at least a first integrated circuit die element including a field programmable gate array; IPR2020-01570 Patent RE42,035 E 6 [23.2] at least a second integrated circuit die element including a memory array stacked with and electrically coupled to said field programmable gate array of said first integrated circuit die element; and [23.3] wherein said field programmable gate array is programmable as a processing element, and [23.4] wherein said memory array is functional to accelerate external memory references to said processing element. Ex. 1001, 7:38. E. The Asserted Grounds Petitioner challenges claims 1-38 of the ’035 patent as follows (Pet. 1): Claims Challenged 35 U.S.C. § References 1-30, 33, 36, 38 1032 Zavracky, 3 Chiricescu,4 Akasaka5 31, 32, 34 103 Zavracky, Chiricescu, Akasaka, 2 The Leahy-Smith America Invents Act (“AIA”), Pub. L. No. 112-29, 125 Stat. 284, 287-88 (2011), amended 35 U.S.C. § 103. For purposes of trial, the ’035 patent contains a claim with an effective filing date before March 16, 2013 (the effective date of the relevant amendment), so the pre-AIA version of § 103 applies. 3 Zavracky et al., US 5,656,548, issued Aug. 12, 1997. Ex. 1003. 4 Silviu M. S. A. Chiricescu and M. Michael Vai, A Three-Dimensional FPGA with an Integrated Memory for In-Application Reconfiguration Data, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, May 1998, ISBN 0-7803-4455-3/98. Ex. 1004. 5 Yoichi Akasaka, Three-Dimensional IC Trends, Proceedings of the IEEE, Vol. 74, Iss. 12, pp. 1703-1714, Dec. 1986, ISSN 0018-9219. Ex. 1005. IPR2020-01570 Patent RE42,035 E 7 Claims Challenged 35 U.S.C. § References Trimberger6 35 103 Zavracky, Chiricescu, Akasaka, Satoh7 37 103 Zavracky, Chiricescu, Akasaka, Alexander8 II. ANALYSIS A. Legal Standards 35 U.S.C. § 103(a) renders a claim unpatentable if the differences between the claimed subject matter and the prior art are such that the subject matter, as a whole, would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 406 (2007). Tribunals resolve obviousness on the basis of underlying factual determinations, including (1) the scope and content of the prior art; (2) any differences between the claimed subject matter and the prior art; (3) the level of skill in the art; and (4) where in evidence, so-called secondary 6 Steve Trimberger et al., A Time-Multiplexed FPGA, Proceedings of the 1997 IEEE International Symposium on Field-Programmable Custom Computing Machines, April 1997, ISBN 0-8186-8159-4. 7 Satoh, PCT App. Pub. No. WO00/62339, published Oct. 19, 2000. Ex. 1008 (English translation). 8 Michael J. Alexander, James P. Cohoon, Jared L. Colflesh, John Karro, and Gabriel Robins, Three-Dimensional Field-Programmable Gate Arrays, Proceedings of Eighth International Application Specific Integrated Circuits Conference, Sept. 1995. Ex. 1009. IPR2020-01570 Patent RE42,035 E 8 considerations. See Graham v. John Deere Co., 383 U.S. 1, 17-18 (1966). Prior art references must be “considered together with the knowledge of one of ordinary skill in the pertinent art.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994) (citing In re Samour, 571 F.2d 559, 562 (CCPA 1978)). B. Level of Ordinary Skill in the Art Relying on the testimony of Dr. Franzon, Petitioner contends that [t]he person of ordinary skill in the art (“POSITA”) at the time of the alleged invention of the ’035 patent would have been a person with a Bachelor’s Degree in Electrical Engineering or Computer Engineering, with at least two years of industry experience in integrated circuit design, packaging, or fabrication. Pet. 7 (citing Ex. 1002 ¶¶ 58-60). Relying on the testimony of Dr. Souri, Patent Owner contends that [a] person of ordinary skill in the art (“POSITA”) around December 5, 2001 (the earliest effective filing date of the ’035 Patent) would have had a Bachelor’s degree in Electrical Engineering or a related field, and either (1) two or more years of industry experience; and/or (2) an advanced degree in Electrical Engineering or related field. PO Resp. 8-9 (citing Ex. 2011 ¶ 25). We adopt Petitioner’s proposed level of ordinary skill in the art as we did in the Institution Decision, because it comports with the teachings of the ’035 patent and the asserted prior art. See Inst. Dec. 20-21. Patent Owner’s proposed level largely overlaps with Petitioner’s proposed level. Even if we adopted Patent Owner’s proposed level, the outcome would not change. C. Claim Construction In an inter partes review, the Board construes each claim “in accordance with the ordinary and customary meaning of such claim as understood by one of ordinary skill in the art and the prosecution history pertaining to the patent.” 37 C.F.R. § 42.100(b) (2020). Under this IPR2020-01570 Patent RE42,035 E 9 standard, which is the same standard applied by district courts, claim terms take their plain and ordinary meaning as would have been understood by a person of ordinary skill in the art at the time of the invention and in the context of the entire patent disclosure. Phillips v. AWH Corp., 415 F.3d 1303, 1313 (Fed. Cir. 2005) (en banc). “There are only two exceptions to this general rule: 1) when a patentee sets out a definition and acts as his own lexicographer, or 2) when the patentee disavows the full scope of a claim term either in the specification or during prosecution.” Thorner v. Sony Comput. Entm’t Am. LLC, 669 F.3d 1362, 1365 (Fed. Cir. 2012). In the Institution Decision, we determined that [t]he parties’ arguments raise a claim construction issue regarding “wherein said memory array is functional to accelerate external memory references to said processing element” (claims 23 and 33) and “said memory array is functional to accelerate external memory references to the processing element,” and “wherein said memory array is functional to accelerate reconfiguration of said field programmable gate array as a processing element” (claims 24, 30, and 32). Neither party provides an explicit construction. Inst. Dec. 21-22. Tracking the institution decision in related IPR2020- 01021 (challenging related U.S. Patent No. 7,282,951 B2), in the Institution Decision here, we preliminarily construed the “‘functional to accelerate’ limitations [as] requir[ing] a number of contacts extending throughout the thickness of the wafers in a vertical direction (vias) within the periphery of the die to allow multiple short paths for data transfer between the memory IPR2020-01570 Patent RE42,035 E 10 and processor.” Inst. Dec. 25.9 Likewise, in the final written decision in IPR2020-01021 and in co-pending IPR2020-01568, the Board construed these “functional to accelerate” limitations in materially the same manner. IPR2020-01021, Paper 30, 26, Paper 33 (Errata); IPR2020- 01568, Paper 39 (final written decision) § II.C. In particular, the “functional to accelerate” clauses require “a number of contacts extending throughout the thickness of the wafers in a vertical direction (vias) within the periphery of the die to allow multiple short paths for data transfer between the memory array/memory and processing element/programmable array.” See IPR2020-01021, Paper 30, 26, Paper 33 (Errata). We herein adopt and incorporate the construction and the rationale supporting it from the final written decision of IPR2020-01021. Petitioner states that “[e]ven beyond the Board’s construction, the Petition shows that the Zavracky-Chiricescu-Akasaka Combination provides the ‘memory array . . . accelerate’ limitations under any reasonable construction,” “even under [Patent Owner’s] flawed construction.” Reply 8- 9. Patent Owner states that it “construes all terms in ‘accordance with the ordinary and customary meaning of such claim as understood by on of 9 The two relevant patent specifications (i.e., for U.S. Patent No. 7,282,951 B2 and the ’035 patent) include the same material disclosure for claim construction purposes. The application leading to U.S. Patent No. 7,282,951 B2 is a continuation of an application leading to US. Pat. No. 7,126,214 B2, which is a continuation-in-part an application leading to U.S. Pat. No. 6,781,226 B1, which is a continuation-in-part of the application leading to U.S. Patent No. 6,627,985 B2, from which the ’035 patent reissued. See Ex. 1001, codes (21), (64); IPR20-01021, Ex. 1001, codes (21), (63). IPR2020-01570 Patent RE42,035 E 11 ordinary skill in the art and the prosecution history pertaining to the patent.’” PO Resp. 9 (quoting 37 C.F.R. § 42.100(b)). Patent Owner argues that “the claims require . . . structure provided within the memory array (i.e. the wide configuration data port disclosed in the ’035 Patent) that is responsible for accelerating the programmable array’s accelerated external memory references.” PO Resp. 20 (citing Ex. 2011 ¶ 55). Contrary to this argument, Patent Owner fails to describe what particular structure of a wide configuration data port (WCDP) within a memory array the challenged claims require under “the ordinary and customary meaning” or otherwise. See id. at 9. The ’035 patent does not describe a WCDP “within the memory array.” Figure 5, for example, depicts “VERY WIDE CONFIGURATION DATA PORT” 82, but Figure 5’s WCDP is a separate black box from any structure involving memory or a memory array. Compare Ex. 1001, Fig. 4 (memory die 66 and vias 70), with id. at Fig. 5 (WCDP 82). IPR2020-01570 Patent RE42,035 E 12 Figure 5 follows: Figure 5 above illustrates a “VERY” WCDP 82 on the left connected to buffer cells 88, and configuration memory cells 88 and logic cells 84, toward the middle and right of the WCDP. See Ex. 1001, Fig. 5; 4:50-56. Buffer cells 88 (“preferably on a portion of the memory die 66” (see Fig. 4)), “can be loaded while the FPGA 68 comprising the logic cells 84 are [sic] in operation.” Id. at 4:51-53 (emphasis added). 10 10 Although the ’035 patent states that “[t]he buffer cells 88 are preferably on a portion of the memory die 66 (FIG. 4)” in reference to Figure 5, the buffer cells 88 in Figure 5 appear to be near or connected to FPGA logic cells 84 and configuration memory cells 86--perhaps depicting something other than the preferred embodiment describing buffer cells on the memory die. For example, Dr. Chakrabarty (Patent Owner’s expert in related IPR1020- IPR2020-01570 Patent RE42,035 E 13 Therefore, the central purpose of the buffer cells is “they can be loaded while the FPGA 68 comprising the logic cells are in operation,” which “then enables the FPGA 68 to be totally reconfigured in one clock cycle with all of it[s] configuration cells 84 updated in parallel.” Id. at 4:53- 53 (emphasis added). But none of the challenged claims require loading the FPGA while it is in operation. Also, configuration cells and the FPGA can be updated in parallel (e.g., in one clock cycle) without the buffer cells. See id.; see also infra note 11 (cache memory provides reconfiguration). Therefore, the claims do not require buffer cells even by implication. Regardless of the location of the disclosed but unclaimed buffer cells, Figures 4 and 5 and the disclosure indicate that the numerous connections between memory die 66 (with or without buffer cells 88 thereon) and FPGA die 68 (with our without configuration memory cells 86 thereon) facilitate the claimed “functional to accelerate” limitations, in line with our claim 01021) testified that FPGA die 68 is to the right of Figure 5’s WCDP 82, while memory die 66 (see Fig. 4), although undepicted in Figure 5, is to the left of Figure 5’s WCDP 82. Ex. 1075, 157:5-158:7; see also Reply 9 (quoting 1075, 157:23-158:3). In any event, Figure 5 depicts WCDP 82 as a separate circuit or structure (in black box form) from buffer cells 88 and any memory die or array, and it is not clear how Figure 5’s WCDP relates structurally to a memory die or memory array. See id. at Fig. 5. During the Oral Hearing, Patent Owner’s arguments further blurred what Figure 5 illustrates. That is, Patent Owner argued that “when the buffer cells are on the FPGA, it then raises the question, okay, well, what’s on the memory array, right. And my answer would be probably more buffer cells.” Tr. 54:21-24 (emphasis added). But there is no disclosure for buffer cells in or on both a memory array and an FPGA die. See id. at 55:3-6 (Patent Owner arguing that “I don’t think there’s anything that prevents” buffer cells from being on both dies (emphasis added)). IPR2020-01570 Patent RE42,035 E 14 construction.11 In other words, to the extent the claims implicate a WCDP, it is the numerous via connections associated with that port connected to a memory or memory array that support the “functional to accelerate” limitations as discussed further below. Patent Owner correctly notes that “the ’035 Patent discloses that loading configuration data through a typical, relatively narrow [i.e., ‘8 bit’ or single ‘byte’] configuration data port [with respect to prior art Figure 3] led to unacceptably long reconfiguration times.” See PO Resp. 20 (citing Ex. 1001, 3:66-4:5); Ex. 1001, 3:66-4:5 (“Configuration data is loaded through a configuration data port in a byte serial fashion and must configure the cells sequentially progressing through the entire array of logic cells 54 and associated configuration memory. It is the loading of this data through a relatively narrow, for example, 8 bit port that results in the long reconfiguration times.” (emphasis added)).12 Patent Owner contends that 11 The ’035 patent implies that configuration memory cells 66 are on FPGA die 68 in one embodiment, but a cache memory provides reconfiguration without them in other embodiments. See Ex. 1001, 4:56-61 (stating that “[o]ther methods for taking advantage of the significantly increased number of connections to the cache memory die 66 (FIG. 4) may include its use to totally replace the configuration bit storage on the FPGA die 68 as well as to provide larger block random access memory (‘RAM’) than can be offered within the FPGA die itself”). 12 This description indicates that 8 bits of the single byte load in parallel to the first 8 bit locations of configuration memory 56, and then in succession (serial) to the other configuration memory cells. In other words, the quoted description about “byte serial” loading and Figure 3 together show that each byte (i.e., 8 bits) loads over a parallel bus into successive 8 bit blocks (i.e., a byte) of configuration memory cells in succession (i.e., series). See Ex. 1001, Fig. 3 (showing 8 bit configuration data port 52 connected by a bus to IPR2020-01570 Patent RE42,035 E 15 “[t]he inventors solved this problem not only by stacking a memory die with a programmable array die, but also by interconnecting those two elements with a ‘wide configuration data port’ that employs through-silicon contacts, with the potential for even further acceleration where the memory die is ‘tri- ported.’” Id. (citing Ex. 1001, 4:31-38) (emphasis added). This argument itself (which mimics the testimony of Dr. Souri (Ex. 2011 ¶ 56)) shows that any structure of a WCDP implicated here simply “interconnect[s] those two [die] elements”-- i.e., implicating the numerous vias/contacts 70 as depicted in Figure 4 that connect die elements 64, 66, and 68 together. Therefore, Patent Owner’s argument and Dr. Souri’s testimony support our analysis and claim construction. In another argument addressing Petitioner’s allegation of obviousness, Patent Owner argues that Petitioner “does not account for all aspects of the claimed invention,” and states “[f]or example, . . . the ’035 patent . . . discloses utilizing a portion of the memory array as a wide configuration data port including buffer cells.” PO Resp. 22 (citing Ex. 1001, 4:47-52). Note that this argument for “buffer cells” differs from Patent Owner’s argument on page 20 of its Response, which does not mention “buffer cells” and only mentions a “wide configuration data port” as “responsible for accelerating the programmable array’s accelerated external memory references.” Again, the argument does not explain how the ’951 patent shows “utilizing a portion of the memory array as a wide configuration data port.” a block of configuration memory cells 56M0 and then in serial to successive blocks of configuration memory cells 56M1-5600). IPR2020-01570 Patent RE42,035 E 16 Based on the specification and claim language as discussed above and further below, apart from numerous vias 70 as depicted in Figure 4, none of the “functional to accelerate” clauses at issue here require any other structure associated with a WCDP. In support of our claim construction, Figure 4 of the ’035 patent, depicted next, illustrates vias 70 throughout each die, 64, 66, and 68: As depicted above, Figure 4 shows a number of vias 70 throughout the periphery of each die (i.e., microprocessor die 64, memory die 66, and FPGA 68 die). According to the abstract as quoted above, these “contacts [i.e., vias] . . . traverse the thickness of the die. The processor module disclosed allows for a significant acceleration in the sharing of data between the microprocessor and the FPGA element . . . .” Ex. 1001, code (57) (emphasis added). This description of “significant acceleration” does not mention a WCDP or buffer cells. IPR2020-01570 Patent RE42,035 E 17 Moreover, the ’035 patent specification consistently ties data acceleration to stacking techniques that include vias throughout the stacked dies without requiring other structure. In addition to the abstract, the ’035 patent describes “taking advantage of the significantly increased number of connections to the cache memory die.” Ex. 1001, 4:56-58. It describes “an FPGA module that uses stacking techniques to combine it with a memory die for the purpose of accelerating FPGA reconfiguration.” Id. at 2:55-57 (emphasis added). Similarly, it states that “the FPGA module may employ stacking techniques to combine it with a memory die for the purpose of accelerating external memory references.” Id. at 2:59-60 (emphasis added). The stacking techniques include and refer to the short multiple through-via interconnections 70 distributed throughout the dies as depicted in Figure 4. Id. at 2:31-35 (“[S]ince these differing die do not require wire bonding to interconnect, it is now also possible to place interconnect pads throughout the total area of the various die rather than just around their periphery. This allows for many more connections between the die than could be achieved with any other known technique.”). The ’035 patent also explains that “[b]ecause the various die 64, 66 and 68 (FIG. 4) have very short electrical paths between them, the signal levels can be reduced while at the same time the interconnect clock speeds can be increased.” Ex. 1001, 4:64-66 (emphasis added). Similarly, “there is an added benefit of . . . increased operational bandwidth.” Id. at 4:62-63 (emphasis added). As summarized here, these descriptions of shorter electrical paths, increased speed and bandwidth (leading to data acceleration), and acceleration in general, all because of the disclosed stacking techniques (which include multiple short through-vias), apply IPR2020-01570 Patent RE42,035 E 18 generally to such speed increases (i.e., acceleration) in the context of Figure 4 without mention of Figure 5’s WCDP and buffer cell embodiment, or any tri-port structure. As noted above, even reconfiguration may occur without the specific black box WCDP embodiment of Figure 5, for example, “[o]ther methods for taking advantage of the significantly increased number of connections to the cache memory die 66 (FIG. 4) may include its use to totally replace the configuration bit storage on the FPGA die 68.” Id. at 4:56-61 (emphasis added); see supra note 11. Based on the arguments and evidence of record, no reason exists to depart from the claim construction set forth in the final written decision IPR2020-01021. As Petitioner also argues, Patent Owner did not assert a clear requirement for a WCDP and/or buffer cells for the “functional to accelerate” in related district court litigation. See Reply 2-3 (arguing that Patent Owner does not justify incorporating limitations from the specification and “has taken five inconsistent positions on the ‘accelerate’ terms across co-pending IPRs and litigations”) (citing Ex. 1071 (district court claim chart)); Ex. 1071 (listing various claim construction statements by Patent Owner); Ex. 1072, 27). For example, in the district court litigation, Patent Owner argued as follows: The specification teaches in several sections that the short interconnects to the memory die allows for accelerated external memory references, providing additional context for a POSITA to interpret the claims. Darveaux Decl., ¶ 35. For example, the ‘951 Patent states that in reference to Figures 4 and 5 that acceleration to external memory is performed because “the FPGA module may employ stacking techniques to combine it with a memory die for accelerating external memory references IPR2020-01570 Patent RE42,035 E 19 as well as to expand its on chip block memory.” Ex. 2, ‘951 Patent at Figs. 4 and 5, 2:56-3:2 (emphasis added). Ex. 1072, 29 (emphasis added). In other words, this passage shows that Patent Owner argued in the district court that “short interconnects” of the disclosed “stacking techniques” improve the speed relative to the prior art--without relying specifically on a WCDP, buffer cells, or parallel processing. See id. Therefore, contrary to arguments in the Sur-reply, even though Patent Owner advanced other arguments during the district court litigation, none are clear enough to overcome Patent Owner’s broad statements in the district court litigation as quoted above, and Patent Owner has not “taken consistent positions across all IPRs and litigations.” See Sur-reply 2. As the Board also preliminarily determined in the Institution Decision, prosecution history of the related ’951 patent application also plays an important role in understanding the claims and supports the preliminary claim construction. See Inst. Dec. 24; accord Ex. 2009 (institution decision in IPR2020-1021), 24-25. The prosecution history of the ’951 patent application further supports our construction of the materially similar accelerate clauses involved in the ’951 patent claims and the ’035 patent claims. Specifically, the Examiner indicated allowance of dependent claim 35 of the ’951 patent (if written in independent form) over Lin (U.S. Patent No. 6,451,626 B1 (Ex. 1054; Ex. 1107, 67)), finding Lin does not teach or suggest “wherein said memory array is functional to accelerate external memory references to said processing element.” Ex. 1107, 72- 73; Inst. Dec. 24-25. IPR2020-01570 Patent RE42,035 E 20 Noting this in our Institution Decision, we pointed to petitioner Samsung’s annotation in the IPR1020-01021 proceeding of the following figures from Lin to illustrate the issue: Ex. 2009, 25; Inst. Dec. 25. Lin’s annotated Figures 1D and 2D above show that Lin discloses contacts (red) on the sides of dies, instead of a number contact vias extending throughout the area of each die within the periphery thererof, in line with the Examiner’s reasons for allowance. See id.; Ex. 1054 (Lin), Figs. 1D, 2D; Ex. 1107, 72-73. Accordingly, as we noted in the Institution Decision, in light of Lin’s teachings and absent explicit explanation during prosecution by the Examiner, the rejection and reasons for allowance provide further support the understanding that the “functional to accelerate” limitations require a number of contacts extending throughout the thickness of the wafers in a vertical direction (vias) within the periphery of the die to allow multiple short paths for data transfer between the memory and process[ing element]. Inst. Dec. 25-26; compare, Ex. 1001, Fig. 4 (showing numerous contact points), with Ex. 1054, Figs. 1D, 2D (showing peripheral contact points). IPR2020-01570 Patent RE42,035 E 21 During the Oral Hearing, Patent Owner argued that with respect to a WCDP that “[t]he spec is very clear that what we’re talking about is it has enough connections to allow the parallel updating of data.” Tr. 48:20-22 (emphasis added). When asked to compare the ’035 patent’s Figure 3 (which depicts a prior art eight bit configuration data port) and Figure 5 (which depicts a WCDP), Patent Owner stated that the WCDP “could be as small as 32 bits . . . if you have a small FPGA, right? If you want to update something in parallel, you could update 32-bit with 32 bits?” Tr. 49:1-9 (answering “yes, . . . if you have a very, . . . small FPGA, the number of bits can be . . . relatively smaller, but what’s critical is not the number of bits and . . . . [i]t’s not necessarily the number of bits that’s in the configuration data port, but how they’re arranged”). Patent Owner continued by answering that “parallel connections between cells on the die. . . . get to the heart of what the wide configuration data port is, how it works, and how the interconnections between the die work even absent . . . the data being used to configure the FPGA.” Id. at 49:13-16. Then, Patent Owner argued that “we all agree that the wide configuration data port . . . at least includes these interconnections between the die. So, what we’re talking about is moving data from one die to another. That’s the use of the wide configuration data port.” Id. at 49:22-50:4 (emphasis added). These arguments support our construction because our construction “at least includes these interconnections between the die” and allows data movement between dies. In addition, contrary to Patent Owner’s arguments in the Sur-reply, our construction implicitly distinguishes over the small number of connections in the narrow configuration data port of the ’035 patent’s prior art Figure 3. See Sur-reply 8 (arguing that IPR2020-01570 Patent RE42,035 E 22 “Petitioner’s . . . interpretation of the wide configuration data port as simply meaning ‘a data port used for configuration . . . . [with] a lot of connections though these TSVs’ [through silicon vias] . . . . directly contradict[s] the specification [and] . . . also encompasses the conventional ‘data port,’ which the ’035 Patent distinguishes the wide configuration data port from” (quoting Reply 8). In other words, the “functional to accelerate” clauses require “a number of contacts extending throughout the thickness of the wafers in a vertical direction (vias) within the periphery of the die to allow multiple short paths for data transfer between the memory array and processing element.” See IPR2020-01021, Paper 30, 26, Paper 33 (Errata). This implicitly represents more vias than prior art Figure 3 of the ’035 patent describes (i.e., eight), as supported in view of specification and the prosecution history of the related ’951 patent. See Ex. 1001, Fig. 3 (“8 BIT CONFIGURATION DATA PORT 52”). In addition, as discussed further below and as Petitioner shows, to the extent any of the “functional to accelerate” claims implicate parallel data transfer, our claim construction allows for such parallel data transfers--in line with Patent Owner’s arguments. See Tr. 49:13-16 (Patent Owner arguing that “parallel connections between cells on the die. . . . get to the heart of what the wide configuration data port is, how it works, and how the interconnections between the die work”); Sur-reply 2 (arguing that “the novel die-area interconnection arrangement with buffer cells (i.e., wide configuration data port) allows the parallel loading of data from the memory die to the programmable array that is responsible for the claimed acceleration” (emphasis added)). IPR2020-01570 Patent RE42,035 E 23 Moreover, Patent Owner concedes that “[t]he ’035 Patent makes clear that stacking die and short interconnections are simply ‘added benefits’ that allow for increased operational bandwidth and speed.” Sur-reply 6 (citing Ex. 1001, 4:62-67) (emphasis added). But increased speed is acceleration--not merely “an added benefit.” So is increased bandwidth in context to the ’035 patent, because both benefits of increase in speed and bandwidth fall within the “functional to accelerate” limitations at issue here for the reasons discussed above. See Ex. 1001, 4:42-66; Tr. 56:11-14 (Patent Owner arguing that “[i]f you have a data port that connects in parallel the cells in the memory array with the FPGA cells, that does massively increase bandwidth. . . . but just increasing bandwidth doesn’t get you parallel connections”). As noted, our claim construction allows for parallel data transfers (i.e., “a number of vertical contacts distributed throughout . . . to allow multiple short paths for data transfer”) so that an increase in bandwidth due to such multiple data paths (vias and connections) both satisfies and supports the “functional to accelerate” clauses. Therefore, as indicated above, we construe the “functional to accelerate” limitations as “a number of vertical contacts distributed throughout the surface of and traversing the memory die in a vertical direction (vias) to allow multiple short paths for data transfer between the “memory array/memory and processing element/programmable array.” Based on the current record, no other terms require explicit construction. See, e.g., Nidec Motor Corp. v. Zhongshan Broad Ocean Motor Co., 868 F.3d 1013, 1017 (Fed. Cir. 2017) (“[W]e need only construe terms ‘that are in controversy, and only to the extent necessary to resolve the IPR2020-01570 Patent RE42,035 E 24 controversy’. . . .” (quoting Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999))). D. Obviousness, Claims 1-30, 33, 36, and 38 Petitioner contends the subject matter of claims 1-30, 33, 36, and 38 would have been obvious over the combination of Zavracky, Chiricescu, and Akasaka. Pet. 13-55. As discussed below, Patent Owner disputes Petitioner’s contentions. See generally PO Resp.; Sur-reply. 1. Zavracky Zavracky, titled “Method for Forming Three Dimensional processor Using Transferred Thin Film Circuits,” describes “[a] multi-layered structure” including a “microprocessor . . . configured in different layers and interconnected vertically through insulating layers which separate each circuit layer of the structure.” Ex. 1003, code (57). Zavracky’s “invention relates to the structure and fabrication of very large scale integrated circuits, and in particular, to vertically stacked and interconnected circuit elements for data processing, control systems, and programmable computing.” Id. at 2:5-10. Zavracky includes numerous types of stacked elements, including “programmable logic device[s]” stacked with “memory” and “microprocessor[s].” See id. at 5:19-23. IPR2020-01570 Patent RE42,035 E 25 Zavracky’s Figure 12 follows: Figure 12 above illustrates a stack of functional circuit elements, including microprocessor and RAM (random access memory) elements wherein “buses run vertically through the stack by the use of inter-layer connectors.” Ex. 1003, 12:24-26. 2. Chiricescu Chiricescu, titled “A Three-Dimensional FPGA with an Integrated Memory for In-Application Reconfiguration Data,” describes a three- dimensional chip, comprising an FPGA, memory, and routing layers. Ex. 1004, II-232. Chiricescu’s FPGA includes a “layer of on-chip random access memory . . . to store configuration information.” Id. at II-232 § 1. IPR2020-01570 Patent RE42,035 E 26 Chiricescu describes and cites the published patent application that corresponds to Zavracky (Ex. 1003) as follows: At Northeastern University, the 3-D Microelectronics group has developed a unique technology which allows us to design individual CMOS circuits and stack them to build 3-D layered FPGAs which can have vertical metal interconnections (i.e., interlayer vias) placed anywhere on the chip. See id. at II-232; see also id. at II-235 (citing “P. Zavracky, M. Zavracky, D- P Vu and B. Dingle, ‘Three Dimensional Processor using Transferred Thin Film Circuits,’ US Patent Application # 08-531-177, allowed January 8, 1997”) (emphasis added).13 Chiricescu describes “[a]nother feature of architecture [as] a layer of on-chip random access memory . . . to store configuration information.” Ex. 1004, II-232 § 1. Chiricescu also describes using memory on-chip to “significantly improve[] the reconfiguration time,” explaining as follows: The elimination of loading configuration data on an as needed basis from memory off-chip significantly improves the reconfiguration time for an on-going application. Furthermore, a management scheme similar to one used to manage cache memory can be used to administer the configuration data. Id. at II-234. 13 Zavracky lists the same four inventors and “Appl. No. 531,177,” which corresponds to the application number cited by Chiricescu. Ex. 1003, codes (75), (21). IPR2020-01570 Patent RE42,035 E 27 Figure 2 of Chiricescu follows: Chiricescu’s Figure 2 above illustrates three layers in the 3-D-FPGA architecture, with a “routing and logic blocks” (RLB) layer arranged in a “sea-of-gates FPGA structure,” a routing layer, and the aforementioned memory layer (to program/reconfigure the FPGA). See Ex. 1004, II-232- 233. “[E]ach RLB is connected with the switch-boxes . . . in the routing layer (RL) by means of inter-layer vias. Each RLB can be configured to implement a D-type register and an arbitrary logic function of up to three variables.” Id. at II-232. Figure 2 also depicts an external “ROUTING_BUS” to access the 3-D structure with external circuitry to provide configuration data. Id. at II-232 (“A routing bus provides the configuration information of the routing layer . . . .”). 3. Akasaka Akasaka, titled “Three-Dimensional IC Trends” (1986), generally describes trends (several years before the 2001 effective filing date of the invention) in three-dimensional integrated stacked active layers. Ex. 1005, 1703. Akasaka states that “tens of thousands of via holes” allow for parallel processing in stacked 3-D chips, and the “via holes in 3-D ICs” decrease the interconnection length between IC die elements so that “the signal processing speed of the system will be greatly improved.” Id. at 1705. IPR2020-01570 Patent RE42,035 E 28 Akasaka further explains that “[h]igh-speed performance is associated with shorter interconnection delay time and parallel processing” so that “twice the operating speed is possible in the best case of 3-D ICs.” Id. Also, “input and output circuits . . . consume high electrical power.” Ex. 1005, 1705. However, “a 10-layer 3-D IC needs only one set of I/O circuits,” so “power dissipation per circuit function is extremely small in 3-D ICs compared to 2-D ICs.” Id. Figure 4 of Akasaka follows: Figure 4 compares short via-hole connections in 3-D stacked chips with longer connections in 2-D side-by-side chips. According to Akasaka, “[p]arallel processing is expected to be realized more easily in 3-D structures. Several thousands or several tens of thousands of via holes are present in these devices, and many information signals can be transferred from higher to lower layers (or vice versa) through them.” Ex. 1005, 1705. As one example, Akasaka describes one 3-D chip as including “a video sensor on the top layer, then an A/D converter, ALU [(arithmetic logic unit)], memory, and CPU in the lower layers to realize and intelligent image processor in a multilayered 3-D structure.” Id. IPR2020-01570 Patent RE42,035 E 29 4. Petitioner’s Showing, Claims 1-22, 36, and 38 Claim 1’s preamble recites “[a] processor module comprising.” Petitioner relies on the combined teachings of Zavracky, Chiricescu, and Akasaka as discussed below, and provides evidence that Zavracky discloses a processor module, including a programmable array, memory (RAM), and microprocessor as part of a layered 3-D stacked die structure. See Pet. 21 (citing Ex. 1003, 5:19-23, 12:12-38, Figs. 12-13; citing Ex. 1002 ¶¶ 282- 288). Claim 1 recites limitation [1.1], “at least a first integrated circuit die element including a programmable array.” See Pet. 22. Petitioner contends that the combined teachings of Zavracky and Chiricescu render the limitation obvious. Id. at 22-24. Petitioner relies on Zavracky’s “programmable logic array 802” and notes that Zavracky states “[t]he array can be formed in any of the layers of a multilayer structure.” Id. (quoting Ex. 1003, 12:28-38; 1002 ¶¶ 290-299).14 Petitioner also quotes Zavracky as stating “[t]he present invention relates to the structure and fabrication of very large scale integrated circuits, and in particular, . . . vertically stacked and interconnected circuit elements for . . . programmable computing.” Id. at 24-25 (quoting Ex. 1003, 2:2-6). Zavracky states that “[e]ach circuit layer can be fabricated in a separate wafer . . . and then transferred onto the layered structure and interconnected.” Ex. 1003, code (57). 14 Referring to its analysis of claim 2, Petitioner contends that “the POSITA would have understood Zavracky to be describing a programmable array called a field programmable gate array (FPGA), which provides the programmable array element.” See Pet. 23 & n.3 (citing Ex. 1002 ¶¶ 290- 99). IPR2020-01570 Patent RE42,035 E 30 Even if Zavracky does not disclose “a programmable array . . . programmable as a processing element,” Petitioner contends that “Chiricescu explicitly cites and characterizes Zavracky as teaching a way that ‘allows us to design individual CMOS circuits and stack them to build 3-D layered FPGAs.’” Pet. 23-24 (emphasis omitted) (citing Ex. 1004, II- 232). According to Petitioner, “Chiricescu then describes a 3-D chip comprising FPGA, memory, and routing layers. A FPGA, or field programmable gate array, provides “a programmable array.” Id. at 24. Noting that Zavracky’s teaches that the array (FPGA) can be in any layer (see Pet. 23 (citing Ex. 1003, 12:28-38)), Petitioner also quotes Zavracky as teaching that “[i]nter-layer connections . . . can be placed anywhere on the die and therefore are not limited to placement on the outer periphery . . . . Inter-layer connection is achieved with a minimal loss of die space.” Id. at 22 (quoting Ex. 1003, 6:43-65). Petitioner contends that “Chiricescu’s teachings, suggestions, and motivations of reconfiguring a FPGA with a stacked memory to accelerate processing and reconfiguration of the FPGA would have prompted a POSITA to pursue a combination with Zavracky.” Id. at 17 (citing Ex. 1002 ¶¶ 212-232). Petitioner explains that “[i]ntegrating the FPGA structure and reconfiguration scheme from Chiricescu would have produced the result forecast by Zavracky, wherein the programmable logic device “can be programmed to provide for userdefined communication protocol[s].” Id. at 20 (citing Ex. 1003, 12:29- 39; Ex. 1002 ¶ 231). Petitioner also contends that “Chiricescu . . . explicitly references and uses the interconnections of Zavracky.” Id. (citing Pet. § VII.A.2); see supra § II.D.2 (noting that Chiricescu cites and discuses Zavracky). Petitioner also IPR2020-01570 Patent RE42,035 E 31 contends that “[a] POSITA’s background knowledge in 2001 included knowing to stack various types of die elements together to form 3-D stacked ICs using vertical interconnects,” and would have known that stacking chips with such interconnects would “minimize latency between the device and chips and . . . maximize bandwidth.” Id. at 7-8 (citing Ex. 1025, 7:18-25, Fig. 22; Ex. 1002 ¶¶ 41-43). Claim 1 recites elements [1.2] “at least a second integrated circuit functional die element with and electrically coupled to said programmable array of said first integrated circuit die element” and [1.3]: “wherein said first and second integrated circuit functional elements are electrically coupled by a number of contact points distributed throughout the surfaces of said die elements.” Petitioner’s annotated version of Zavracky’s Figure 13 depicts stacked functional elements and the coupled contact points relied upon by Petitioner (see Pet. 22): IPR2020-01570 Patent RE42,035 E 32 Zavracky’s Figures 12 and 13 above as annotated by Petitioner portray (highlighted) inter-layer via connections and one or more second integrated circuit (IC) functional elements, respectively microprocessors 704, 706 and memory 702, and memory 808 (RAM) die, and microprocessor dies 804 and 806, stacked above programmable logic array 802 (FPGA). See Pet. 22-25. As noted above, Petitioner provides evidence that “Zavracky teaches that ‘openings or via holes’ inter-layer connections ‘can be placed anywhere on the die and therefore are not limited to placement on the outer periphery.’” See Pet. 26-27 (citing Ex. 1003, 6:43-47, 13:43-46, 14:56- 63). For example, Petitioner quotes Zavracky as teaching “integrated circuits, and in particular, to vertically stacked and interconnected circuit elements,” “a multitude of individual dies”; and “connections placed anywhere on the die.” See id. at 24 (citing Ex. 1003, 2:2-6, 4:63-67, 6:46- 47). Petitioner also relies on and quotes similar teachings in Akasaka: Akasaka, in terms similar to the ’035 patent, describes electrical coupling by contact points distributed throughout the surfaces of die elements: “It is possible to exchange signals between upper and lower active circuit layers through via holes in 3-D ICs.” Ex. 1005, 1705. “Each active layer is connected electrically through via holes.” Id., 1707. Pet. 26. Petitioner quotes Akasaka further: “Several thousands or several tens of thousands of via holes are present in these devices, and many information signals can be transferred from higher to lower layers (or vice versa) through them.” Pet. 26 (quoting Ex. 1005, 1705) (emphasis by Petitioner). Petitioner further contends that in Akasaka, “[t]he contact points IPR2020-01570 Patent RE42,035 E 33 on the surface of the die are created by ‘etching [the] via holes.’” Id. (citing Ex. 1005, 1707; citing Ex. 1002 ¶¶ 327-332). Petitioner provides several reasons to combine the reference teachings to suggest providing numerous via holes between stacked dies or chips according to Zavracky, Chiricescu, and Akasaka. See Pet. 16-20. For example, Petitioner describes Akasaka’s vertical via connections as resulting in “greatly improved” “processing speed” due “parallel processing” and “shorter interconnection delay time”: Akasaka teaches that these “tens of thousands of via holes” permit parallel processing by utilizing the many interconnections. [Ex. 1005, 1705.] As a result of this parallel processing, “the signal processing speed of the system will be greatly improved.” [Id.] Due to “shorter interconnection delay time” arising from stacking and “parallel processing” made possible from the area-wide interconnects, Akasaka states that “twice the operating speed is possible in the best case of 3D ICs” as compared to conventional designs. Id. Id. at 16. Petitioner also points out that Akasaka teaches that “tens of thousands of via holes’ permit parallel processing, and that use of the ‘via holes in 3-D ICs’ shortens the interconnection length between IC die elements so that ‘the signal processing speed of the system will be greatly improved.’” Pet. 16 (quoting Ex. 1004, 1705). In addition, Petitioner argues that “the POSITA knew of the need for replicated ‘common data memory’ in stacked designs, including as taught in Akasaka, to enable, e.g., multi-processor cache coherence.” Id. at 19-20 (citing Ex. 1002 ¶ 236; Ex. 1034, 466-469; Ex. 1005, 1713, Fig. 25). Petitioner generally relies on the “Zavracky-Chiricescu-Akasaka Combination” as “provid[ing] . . . the first and second IC die elements.” IPR2020-01570 Patent RE42,035 E 34 Pet. 25. As noted above, Petitioner points out that “Chiricescu explicitly references and builds on Zavracky.” Id. at 18 (citing Pet. § VII.A.2.); see supra § II.D.2 (noting the explicit citation to and description of Zavracky in Chiricescu)). Petitioner also contends “that applying Akasaka’s distributed contact points, e.g., in the 3D stacks of Zavracky or Chiricescu, would increase bandwidth and processing speed through better parallelism and increased connectivity.” Id. at 19 (citing Ex. 1002 ¶ 233; Ex. 1005, 1705). Petitioner also contends that “[t]he POSITA would have sought out Akasaka’s connectivity to improve Zavracky’s stacks in applications requiring parallel processing. Such applications included image processing algorithms run simultaneously over an entire image in memory.” Id. (citing Ex. 1002 ¶ 235; Ex. 1048; Ex. 1005; Ex. 1021). Claim 1 also recites limitation [1.4]: “wherein said contact points traverse said die elements through a thickness thereof.” Petitioner refers to its showing with respect to limitation [1.3]. Pet. 28. Petitioner similarly relies on Zavracky’s stacked chips interconnected by vias as portrayed in Figures 12 and 13, and further relies on Zavracky’s etching teachings for forming via holes: Zavracky describes connections made by “[v]ia holes [that] are formed through the upper contact areas to gain access to the lower contact areas. [E]tching [is used] to form the via holes[.]”[] Ex. 1003, 14:58-62. The POSITA would have understood this “etching” created a hole through the thickness of the die to permit busses that “run vertically through the stack”; that is, permit thru-silicon electrical contact. Ex. 1002 ¶¶333-34 (citing Ex. 1003, 12:26; Ex. 1020 (“vertical interconnections are formed using vias etched through the entire wafer”). Zavracky further teaches a continuous connection traversing through the dies, as shown in Figures 12, 13 and other figures . . . . These teachings by Zavracky would have been understood by a IPR2020-01570 Patent RE42,035 E 35 POSITA as providing for holes-which the ’035 patent describes as “contact points”-that “traverse said die elements through a thickness thereof.” Id. Pet. 28. Petitioner also relies on the combined teachings of Zavracky, Chiricescu, and Akasaka, based on its reasons to combine as summarized above. See Pet. 28-29 (citing Ex. 1005, 1704-07; Ex. 1004, II-232, Fig. 1; Ex. 1002 ¶ 334). Claim 2 depends from claim 1 and recites “wherein said programmable array of said first integrated circuit die element comprises an FPGA.” Petitioner generally refers to the “[t]he Zavracky-Chiricescu- Akasaka Combination” as it does for claim 1. See Pet. 30. Citing the testimony of Dr. Franzon and other evidence, Petitioner relies on Zavracky’s PLD (programmable logic device) 802 at the bottom of the stack in Figure 13 as an FPGA. Id. at 29-31 (citing Ex. 1002 ¶¶ 292-297; Ex. 1035, 1:29- 30; Ex. 1036, 4:1-9; Ex. 1037, 1:13-22; Ex. 1038, code (57) (describing “transistors of a programmable logic device (PLD), such as a field programmable gate array (FPGA)”). Petitioner relies on other teachings, including Chiricescu’s teachings, including its “sea-of-gates” FPGA layer, and the knowledge of an artisan of ordinary skill, to show that Zavracky’s PLD is or at least suggests an FPGA based on Chiricescu’s FGPA teachings. See Pet. 30 (citing 1002 ¶¶ 294- 297; Ex. 1004, II-232; Ex. 1040; Ex. 1051). Petitioner also generally relies on reasons for combining the references as outlined above with respect to claim 1 to suggest modifying Zavracky’s 3-D stack (memory, processor, FPGA) based on Chiricescu’s layer/stack teachings (FPGA, memory). See id. at 30-31 (citing Pet. §§ VII.A.2, VII.A.4). Petitioner also notes that Chiricescu specifically describes Zavracky’s teachings (see supra § II.D.2) IPR2020-01570 Patent RE42,035 E 36 as useful for providing 3-D FPGA stacks. See id. at 30 (“Chiricescu literally describes Zavracky as teaching technology ‘to build 3-D layered FPGAs which can have vertical metal interconnections (i.e., interlayer vias) placed anywhere on the chip’” (quoting Ex. 1004, II-232)). Claim 3 depends from claim 1 and recites “[t]he processor module of claim 1 wherein said second integrated circuit die element comprises a microprocessor.” Petitioner relies on its showing with respect to claim 1, which relies on Zavracky’s examples of microprocessors with “each microprocessor on its own die element (Figure 12) or using a multi-layer microprocessor (Figure 13).” Pet. 31. Claim 4 depends from claim 1 and recites “[t]he processor module of claim 1 wherein said second integrated circuit die element comprises a memory.” Petitioner refers to its showing for claim 1 and contends that “Zavracky’s Figure[] 12 and Figure 13 describe[] layers (comprising integrated circuit die elements per analysis in [1.1]) that comprise a memory, including by describing: ‘random access memory on the fourth layer 808’ also referred to as a ‘memory array.’” Pet. 32 (citing Ex. 1003, Fig. 10, 11:63-65 (“memory may be stacked on top of the multi-layer microprocessor.”), Fig. 12, 12:15-28 (“random access memory array”), Fig. 13, 12:33-35). Claim 5 depends from claim 1 and recites “[t]he processor module of claim 1 further comprising: at least a third integrated circuit die element stacked with and electrically coupled to at least one of said first or second integrated circuit die elements.” Petitioner refers to its showing for claims 1, 3, and 4, and explains that “the Zavracky-Chiricescu-Akasaka Combination provides that the microprocessor, memory, and programmable array die IPR2020-01570 Patent RE42,035 E 37 elements, are ‘stacked with and electrically coupled to’ each other, providing the additional limitation[s].” In particular, Zavracky describes stacks with at least three layers wherein the die elements are stacked and electrically coupled.” Pet. 33 (citing Ex. 1002 ¶¶ 313-326; Ex. 1003, Fig. 13). In other words, Petitioner’s showing for claim 5 summarizes the added limitations recited in claims 3, 4, and 6 by reference primarily to the memory, FPGA, and processor stack as depicted in Zavracky’s Figure 13. See id. at 31-33. Claim 6 depends from claim 5 and recites Petitioner “[t]he processor module of claim 5 wherein said third integrated circuit die element comprises a memory.” Petitioner refers to its showing with respect to claims 4 and 5, as summarized above. Pet. 33 (citing Ex. 1003, Fig. 13.; Ex. 1002 ¶¶ 318, 322) . Claim 7 depends from claim 1 and recites “[t]he processor module of claim 1 wherein said programmable array is reconfigurable as a processing element.” Petitioner relies on Zavracky’s statement that the “programmable logic array 802 . . . can be programmed to provide for user-defined communication protocol.” Pet. 33 (citing Ex. 1003, 12:28- 38). Petitioner explains that [a] POSITA would have understood that Zavracky’s programmable array-when programmed (or reconfigured) according to the user-defined communication protocol- functions as a processing element. In this configuration, as the POSITA would have understood, the programmable array processes data received from the microprocessor or “off-chip resources” into and out of the user-defined protocol. Pet. 33-34 (citing Ex. 1002 ¶ 302; Ex. 1040, 319). Petitioner also relies on one of Chiricescu’s touted “key features,” namely “that its FPGA can be ‘quickly reconfigured’ to implement ‘arbitrary IPR2020-01570 Patent RE42,035 E 38 logic.’” Id. at 34 (quoting Ex. 1004, II-234 § 3). Petitioner also relies on Chiricescu’s teaching for “reconfiguring the FPGA” wherein the “FPGA is reconfigured from performing AxB to AxC or vice versa.” Id. (citing Ex. 1002 ¶ 303; Ex. 1004, 234 (the “example shown is the multiplication of a 4- bit variable”)). Citing § VII.A.4 (motivation for combining references) of the Petition, Petitioner contends that “for multiple reasons the POSITA would have been motivated to modify Zavracky’s programmable array to do more than process communication data, including to perform math calculations (e.g., multiplication operations in signal processing or image processing, such as taught in Akasaka.” Id. (citing Ex. 1005, 1704-05, 1707, 1709; Ex. 1002 ¶¶ 229, 235; Ex. 1048; Ex. 1021). Claim 8 recites “[t]he processor module of claim 1 wherein said die elements are thinned to a point at which said contact points traverse said thickness of said die elements.” Petitioner relies on “[t]he Zavracky- Chiricescu-Akasaka Combination” as its basis, supplemented by the general knowledge of the artisan of ordinary skill, as evidenced by an admission in the ’035 patent. See Pet. 34-37. The relied-upon admission from the ’035 patent follows: Tru-Si Technologies of Sunnyvale, Calif. (http://www.trusi.com) has developed a process wherein semiconductor wafers may be thinned to a point where metal contacts can traverse the thickness of the wafer . . . [.] By using a technique of this type in the manufacture of microprocessor, cache memory and FPGA wafers, all three die, or combinations of two or more of them… Id. at 35 (quoting Ex. 1001, 2:19-30). Petitioner also points to evidence in the “the ’035 original patent’s file wrapper” as disclosing this known wafer thinning technique. Id. (citing Ex. 1012, 88 (teaching “thru-silicon . . . vias [wherein] the wafer is thinned IPR2020-01570 Patent RE42,035 E 39 . . . carefully exposing the deep thru-silicon vias.”), 108 (“[T]he wafer is simply thinned until the contacts are exposed.”)). In other words, Petitioner relies on the knowledge of the ordinarily skilled artisan as evidenced by the admission in the ’035 patent and Exhibit 1012 such an artisan would have been aware of the technique of thinning die elements as recited in claim 8. Petitioner lists several reasons to employ this general knowledge to Zavracky’s modified 3-D stack, including to allow “many die element layers to fit within a standard size package.” See id. at 36-37.15 Petitioner provides evidence of predictability and a reasonable expectation of success based on this general knowledge supplemented by the testimony of Dr. Zavracky. See id. (citing Ex. 1002 ¶¶ 262-66; Ex. 1012, 107 (“It is now mandatory to thin . . . to fit chip stacks inside standard-size 3-D packages”), 104 (“The goal of the technology . . . is to create a stack of 10 wafers equal to the height of a single wafer.”); Ex. 1020)). Petitioner also explains that Zavracky “suggest[s] . . . a need for thin stacks and contact point traversal,” which “would have motivated the POSITA to employ the general knowledge of thinning to expose thru-silicon vias.” Id. at 36 (citing Ex. 1002 ¶ 265; Ex. 1003, 13:55-60).16 15 The admitted prior art here evidences the knowledge of the ordinary artisan and does not form the “basis” of the rejection. Cf. Apple Inc. v. Qualcomm Inc., 2022 WL 288013, slip op. at *5 (Fed. Cir. Feb. 1, 2022) (holding that that applicant admitted prior art (AAPA) may not form the “basis of a ground in an inter partes review because it is not contained in a document that is a prior art patent or prior art printed publication.”). 16 On its face, claim 8 recites a product-by-process limitation and reads on the combination of Zavracky, Chiricescu, and Akasaka as evidenced by Petitioner’s showing with respect to claim 1. That is, “said contact points [of the Zavracky-Chiricescu-Akasaka stack] traverse said thickness of said die elements.” See Ex. 1005, Fig. 4 (vias traversing die elements); Ex. 1003, IPR2020-01570 Patent RE42,035 E 40 Independent claim 9 is a system claim. As Petitioner contends, “[c]laim 9 takes limitations from claim 1 and combines them with a generic processor and memory.” Pet. 37. Specifically, claim 9 recites “[a] reconfigurable computer system comprising: a processor; a memory;” and “at least one processor module” that materially recites the same limitations as the “processor module” of claim 1. The processor module of claim 1 reads on the “Zavracky-Chiricescu-Akasaka Combination” as determined above. Other than at most implying some type of electrical connection through the recitation of “a reconfigurable computer system comprising” in the preamble, claim 9 does not specify any electrical communication between the processor, memory, and “processor module.” Petitioner contends that “Zavracky-Chiricescu-Akasaka Combination in further combination with general knowledge of the POSITA renders obvious claim [9].” Pet. 37. Petitioner explains that the “the Zavracky- Chiricescu-Akasaka Combination teaches the use of numerous microprocessors and numerous memories - any of which can satisfy the additional requirement for one more processor and one more memory in claim 9, and indeed, the teachings of Figure 13 already shows such a reconfigurable computer system.” Id. “Beyond this,” Patent Owner contends that a person of ordinary skill would have known to connect an FPGA of the Zavracky-Chiricescu-Akasaka Combination in a system with memory and a processor as evidenced by admissions in the ’035 patent, including admitted prior art Figure 1, which shows a “prior art ‘MAPTM’ Fig. 13 (same). Therefore, by definition, “said die elements [of claim 1] are thinned to a point at which said contact points traverse said thickness of said die elements.” IPR2020-01570 Patent RE42,035 E 41 element . . . taught to ‘comprise a field programmable gate array “FPGA” [and] read only memory.’” Id. at 37-38 (quoting Ex. 1001, 3:22-24; citing id. at Fig. 1). Petitioner points out that admitted prior art Figure 1 is one example that evidences the general knowledge of an artisan of ordinary skill, and “[t]he general knowledge of the POSITA would have other examples of reconfigurable computer systems with a processor, memory, and processor module.” Id. at 38 (citing Ex. 1002 ¶¶ 267-73, 289; 1026).17 Petitioner contends that prior art Figure 1 shows microprocessor 12 and system memory 16 coupled electrically with the MAPTM (which includes an FPGA). Pet. 38 (annotating Ex. 1001, Fig. 1). Petitioner asserts that it would have been obvious to employ the Zavracky-Chiricescu-Akasaka 3-D stack in a system with processor and memory in order to configure the FPGA using off-chip resources during start-up with a reasonable expectation of success where such systems were well-known. See id. at 38-39 (citing Ex. 1003, 12:37; Ex. 1002 ¶¶ 272-73; Ex. 1004, II-234 (describing “during the initiation phase of the application . . . loading configuration data . . . from memory off-chip”)). Independent claim 17 is materially similar to claim 1 but includes at least a third integrated circuit die element in addition to the at least first and second integrated circuit die elements, with the three die elements electrically coupled by contact points distributed throughout the surfaces of 17 In other words, the admitted prior art here evidences the knowledge of the ordinary artisan and does not form the “basis” of the rejection. Cf. Apple Inc., 2022 WL 288013, slip op. at *5 (holding that that applicant admitted prior art (AAPA) may not form the “basis of a ground in an inter partes review because it is not contained in a document that is a prior art patent or prior art printed publication.”). IPR2020-01570 Patent RE42,035 E 42 the die elements and extending through a thickness thereof. To address claim 17, Petitioner primarily relies on its analysis of claims 1, supplemented by its analysis of claims 3, 5, and 6, which we address below. See Pet. 41-43. Independent claim 36 is similar to claim 17 but broader in that the at least third integrated circuit die element electrically couples only to at least one of the other two die elements. To address claim 36, Petitioner relies on its analysis of claims 1 and 23. Pet. 53. Dependent claims 10-16 and 18-22 recite limitations that track the limitations addressed above in claims 1-6, 8, and 9. Petitioner refers to its showing with respect to claims 2-6, 8 and 9 to address these claims. See Pet. 36-40, 43-44. As such, the Petition relies on the combined teachings of Zavracky, Chiricescu, and Akasaka, as teaching or suggesting these added well-known circuit or die elements and their functionality by relying on specific teachings in the references, supported by the knowledge of an artisan of ordinary skill (evidenced partly by admissions in the ’035 patent) and the testimony of Dr. Franzon, and setting forth rationale and reasons to combine, where appropriate. See id. at 36-40, 43-44. Dependent claim 38 recites “[t]he programmable array module of claim 36 wherein said third integrated circuit die element includes an I/O controller.” Petitioner relies on Zavracky’s “‘controller’ as controlling connections ‘to and from the common data bus’ and containing ‘arbitration logic, hosted in the controller [run] in accordance with [a] bus arbitration protocol.’” Pet. 54 (quoting Ex. 1003, 5:54-60). According further to Petitioner, Zavracky’s Figures 1 and 13 illustrate the same or similar controller, and Zavracky discloses a bus controller that arbitrates logic under IPR2020-01570 Patent RE42,035 E 43 a bus arbitration protocol to communicate with off-chip resources as “a third IC die element.” See id. at 54-55 (citing Ex. 1002 ¶¶ 324-325; Ex. 1003, 6:58-60). Petitioner alternatively relies on another controller in Zavracky that provides communication protocols between microprocessor and peripheral devices, and contends that “Zavracky teaches that such a programmable I/O controller ‘can be formed in any of the layers of a multilayer structure as described elsewhere herein.’” Id. at 55 (quoting Ex. 1003, 12:28-38; citing Ex. 1002 ¶¶ 325-326). We adopt and incorporate Petitioner’s showing as to claims 1-22, 36, and 38, as set forth in the Petition and summarized above, as our own. See Pet. 7-44, 53-55. 5. Arguments with Respect to Alleged Obviousness Based on Zavracky, Chiricescu, and Akasaka Patent Owner does not argue any of claims 1-22, 36, and 38 individually, but groups various claims together in separate arguments, as discussed below. Sections below address claims 23-35 and 37, although Patent Owner groups some of these claims together with claims 1-22, 36, and 38 in generic arguments or more specific arguments, so we address some of the more generic arguments in this section and other more specific arguments below. See infra §§ II.D.6-8; II.E-G. Patent Owner argues generally that Petitioner misrepresents the teachings, relies on hindsight to combine the references, and “fails to explain how a POSITA would have combined the references and had a reasonable expectation of success in doing so.” PO Resp. 27 (citing Ex. 2011 ¶ 67). Patent Owner also argues that “Petitioner asserts that ‘Chiricescu employs Zavracky’s principles to solve a known problem with FPGAs-“high configuration time,”’ that is simply not true.” Id. at 28 (quoting Pet. 17). IPR2020-01570 Patent RE42,035 E 44 Rather, Patent Owner explains that “Chiricescu teaches the use of ‘on-chip’ memory to mitigate the time it takes to transfer configuration data from ‘off- chip,’ rather than making any use of Zavracky’s die-area vertical interconnections to transfer configuration data from the ‘on-chip’ memory into the FPGA.” PO Resp. 28 (citing Ex. 1004, 1, 3). Patent Owner’s arguments are unavailing. Both Chiricescu and Zavracky teach memory layers in a 3-D stack to transfer data to FPGAs, as Petitioner persuasively shows as summarized above. See, e.g., Ex. 1003, Fig. 13 (depicting FPGA/PLD 802 in communication by bus with RAM 808); Ex. 1004, Fig. 21 (depicting memory layer in communication with FPGA RLB layer, connected by “vias” “placed anywhere on the chip” according to Zavracky’s teachings (i.e., the “Northeastern University”) technology)); supra § II.D.1-2). Patent Owner attempts to divorce the numerous advantages of using multiple vias in Zavracky’s modified 3-D stack as Petitioner outlines as summarized above, from what Patent Owner implies is separate from the same advantages gained from an “on-chip” memory. There is no support for this line of argument. See infra note 20 (discussing the same issue). In other words, Patent Owner’s arguments do not address Petitioner’s persuasive reliance on multiple vertical vias in the stacked memory chip structure of Zavracky, as modified by the teachings of Chiricescu and Akasaka, in order to, for example, “improve Zavracky’s stacks in applications requiring parallel processing,” and “increase bandwidth and processing speed through better parallelism and increased connectivity.” Pet. 19 (citing Ex. 1002 ¶ 233; Ex. 1003, 6:43-47; Ex. 1005, 1705; IPR2020-01570 Patent RE42,035 E 45 Ex. 1021; Ex. 1048); see also id. at 7-12, 16-28 (similar showing). For example, Petitioner persuasively notes that “[t]he POSITA would have known [about] many references teaching stacked dies with thousands of distributed connections. Id. at 20 (citing Ex. 1002 ¶¶ 238-239; Ex. 1020; Ex. 1021). Discussing Akasaka, Petitioner persuasively contends that Akasaka teaches that “tens of thousands of via holes” permit parallel processing by utilizing the many interconnections. Id. at 16 (citing Ex. 1005, 1705). Petitioner adds that [a]s a result of this parallel processing, “the signal processing speed of the system will be greatly improved.” Due to “shorter interconnection delay time” arising from stacking and “parallel processing” made possible from the area-wide interconnects, Akasaka states that “twice the operating speed is possible in the best case of 3D ICs” as compared to conventional designs. Id. (quoting Ex. 1005, 1705; citing Ex. 1005, Fig. 4). With respect to all challenged claims, Patent Owner also argues that “Petitioner and Dr. Franzon fail to explain how a POSITA would have integrated Akasaka’s thousands of distributed contact points with Zavracky- Chiricescu’s design to achieve the claimed 3-D processor modules and would have had a reasonable expectation of success in doing so.” PO Resp. 38 (citing Ex. 2011 ¶ 79). According to Patent Owner, “Petitioner and Dr. Franzon concede that Zavracky and Chiricescu both disclose only a small number of interconnect paths (e.g., the address and data buses) that provide for vertical communications between functional blocks (such as memory elements, logic unit, etc.) of the multi-layer microprocessor.” Id. (citing Ex. 1003, 11:62-12:39; Ex. 1004, 1-2). According further to Patent Owner, “Dr. Franzon’s analysis, like Petitioner’s analysis, seems to say no more than that a POSITA would have understood that the references could be IPR2020-01570 Patent RE42,035 E 46 combined.” Id. at 40 (citing Ex. 1002 ¶ 239). Patent Owner also asserts that “[a]t the time of the invention, a POSITA was aware of numerous []TSV interconnection issues, such as routing congestion, TSV placement, granularity, hardware description language (‘HDL’) algorithms, which must be considered.” Id. at 41 (citing Ex. 2011 ¶ 82; Ex. 2014, 85, 87, 89). Patent Owner’s arguments are unavailing. As discussed above, Petitioner persuasively relies on the knowledge of the artisan of ordinary skill and the combined teachings of Zavracky, Chiricescu, and Alexander supported by specific reasons and rational underpinning to show how and why the combination teaches or suggests increasing the number of contact points or via holes for electrically coupling FPGA, memory, and processors together to allow for parallel data transfers with a reasonable expectation of success. As indicated above, Zavracky already specifically describes connecting several bus lines (depicting 4 in Fig. 13) from the FPGA/PLD to other circuits, including memory and a processor. See Pet. 13. Zavracky indicates that 32 bit microprocessors were routine in 1993, years before the effective date of the invention, indicating that Zavracky’s microprocessor buses at least handled 32 bits in parallel. Viewed through the lens of an artisan of ordinary skill at the time of the invention of the ’035 patent, Zavracky’s disclosure indicates the ability to handle known microprocessors, memories, and FPGAs, whatever the capabilities of those devices and bus widths were. See Ex. 1003, 1:6-8 (continuity date of 1993), 31-40 (discussing prior art microprocessors). Moreover, Petitioner shows a number of other stacked dies or layers with multiple connections, including Akasaka (Ex. 1005, Fig. 4), Franzon (Ex. 1020, Fig. 4), Koyanagi (Ex. 1021, IPR2020-01570 Patent RE42,035 E 47 Fig. 1(a)), and Alexander (Ex. 1028, Fig. 2(g). See Pet. 26-27. As discussed further below, Trimberger (Ex. 1006) shows parallel loading by “flash reconfiguring all [100,000] bits in logic and interconnect array [i.e., an FPGA] . . . simultaneously from one memory plane,” further evidencing a reasonable expectation of success. See infra § II.E.1 (quoting Ex. 1006, 22).18 And also as noted above, Patent Owner concedes Zavracky and Chiricescu each show how to connect “memory, logic, etc.” using “address and data buses,” albeit on what Patent Owner describes as “only a small number of interconnect paths.” PO Resp. 38 (“Zavracky and Chiricescu both disclose only a small number of interconnect paths (e.g., the address and data buses) that provide for vertical communications between functional blocks (such as memory elements, logic unit, etc.) of the multi-layer microprocessor.”) But Patent Owner also agrees that the number of interconnects is not critical to the claimed invention. See supra § II.C (discussing Oral Hearing arguments); Tr. 49:1-9 (answering “yes, . . . if you have a very, . . . small FPGA, the number of bits can be . . . relatively smaller, but what’s critical is not the number of bits and . . . . [i]t’s not necessarily the number of bits that’s in the configuration data port, but how they’re arranged”). Notwithstanding Patent Owner’s allegation of a lack of a reasonable expectation of success, Patent Owner acknowledges that “[a]t the time of the 18 Petitioner employs Trimberger to address challenged claims 31, 32, and 34 as discussed further below, but it is further evidence of a reasonable expectation of success as it relates to connecting several thousands of bit lines in parallel. IPR2020-01570 Patent RE42,035 E 48 invention, a POSITA was aware of numerous []TSV interconnection issues, such as routing congestion, TSV placement, granularity, hardware description language (‘HDL’) algorithms.” PO Resp. 41 (emphasis added) (citing Ex. 2011 ¶ 82; Ex. 2014, 85, 87, 89). Here, the challenged claims are broad and do not specify a minimal number of interconnections, FPGA size, or chip size that would even raise TSV congestion or other issues. The ’035 patent says nothing about interconnection issues or congestion issues. Even if such issues were a consideration and relevant to a reasonable expectation of success given the breadth of the challenged claims, as Petitioner persuasively argues, “[t]he supposed ‘TSV interconnection issues’ that [Patent Owner] cursorily identifies were at most normal engineering issues, not problems preventing a combination.” Reply 20 (citing Ex. 1070 ¶¶ 13- 28 (Dr. Franzon addressing Dr. Souri’s testimony as to the purported TSV issues)). For example, as Dr. Franzon credibly testifies, even if routing congestion or TSV placement were an issue, Kim gives several solutions that would have been known to POSITA, such as to change the TSV “coarseness” or to “increase the chip area to address the placement and routing congestion caused by TSV insertion.” [Ex. 2014 (Kim), 85]. But again, the [’035] patent[] and claims are silent on any of these issues; Kim is at worst irrelevant, and at best would have actually encouraged the combination. Ex. 1070 ¶ 26. With respect to alleged HDL (hardware description language) issues, Dr. Franzon also credibly testifies that Alexander (Ex. 1009) has a whole section titled “Placement and Routing in 3D” (Ex. 1009, p. 256). Alexander names then- existing CAD tools that performed these functions, includingDAGmap and Mondrian. Designing distributed 3D interconnects was a routine engineering problem by the time of the Huppenthal Patents, and not an impediment to reasonable IPR2020-01570 Patent RE42,035 E 49 expectation of success in making the Zavracky, Chiricescu, Akasaka combination. Ex. 1070 ¶ 27. Petitioner provides other evidence that at the time of the invention, an artisan of ordinary skill would have had a reasonable expectation of success in combining the references to arrive at numerous vias connecting circuits (including memory arrays) on stacked chips or circuit layers and to allow for parallel processing or data transfers. See, e.g., Pet. 12 (discussing known wafer processing technology by artisans of ordinary skill (citing Ex. 1002 ¶¶ 262-266; Ex. 1001, 2:29-35; 5:13-18)), 24-25 (pointing to Zavracky’s memory as an example vertical integrated circuit on stacked dies connected via connections including vertical buses placed anywhere on the die and providing evidence that “each of the programmable array, microprocessor, and memory are pairwise stacked with and electrically coupled with each other” (citing Ex. 1003, 2:7-8, 2:18-22, 2:27-35, 6:43-63, 10:8-21, 11:63- 12:2, 12:13-39, 14:51-63, Fig. 13; Ex. 1002 ¶¶ 278-280)), 25-26 (further relying on Akasaka as teaching thousands of via holes to connect upper and lower circuit layers (citing Ex. 1005, 1705, 1707; Ex. 1002 ¶¶ 327-332)). Furthermore, the ’035 patent describes “recently available wafer processing techniques” including those developed by “Tru-Si Technologies,” indicating, for purposes of institution, that artisans of ordinary skill would have been aware of any such wafer processing techniques for forming vias at the time of the invention. Ex. 1001, 2:20-30. Therefore, Petitioner persuasively shows ample evidence of a reasonable expectation of success. In addition, as noted above, Patent Owner argued during the Oral Hearing that the number of vias is not important, depending on the size of the FPGA, provided that the contacts allow for parallel processing. See IPR2020-01570 Patent RE42,035 E 50 supra § II.C (discussing Tr. 49:1-9 (Patent Owner arguing that the number of vias “could be as small as 32 bits . . . if you have a small FPGA, . . . . [and] [i]f you want to update something in parallel, you could update 32-bit with 32 bits,” further stating that “if you have a very . . . small FPGA, the number of bits can be . . . relatively smaller, but what’s critical is not the number of bits”). As summarized above, Petitioner provides persuasive motivation with a reasonable expectation of success to explain why a person of ordinary skill would have increased the number of vias using known techniques, relying on teachings that providing multiple vias in stacked chips using conventional via and metallization processing allowed for better processing speeds and reconfiguration times, shorter latency, higher bandwidth, and parallel processing. See Pet. 7-12, 16-20; Ex. 1002 ¶¶ 212-239. Dr. Franzon also reasonably shows that the combined teachings of Zavracky and Chiricescu suggest differing “processing tasks . . . [in] co-stacked microprocessors and memories . . . . as good applications for 3-D stacked chips that required parallel computation.” Ex. 1002 ¶ 229. As Petitioner also persuasively notes, Zavracky does not limit the number of connections, contrary to Patent Owner’s arguments. For example, Petitioner quotes Zavracky as describing “inter-layer connections [that] provide for vertical communication. . . . [and] [s]uch connections can be placed anywhere on the die and therefore are not limited to placement on the outer periphery.” Reply 5 (citing Ex. 1003, 6:43-47) (emphasis by Petitioner). Petitioner quotes Zavracky as teaching “buses run vertically through the stack by the use of inter-layer connectors” in describing Figures 12 and 13. Id. (quoting Ex. 1003, 12:24-26). Petitioner persuasively IPR2020-01570 Patent RE42,035 E 51 explains that “Zavracky visually shows a number of vertical contacts that traverse the memory die in the internal periphery of the die and provide contacts on the surface of the memory die, just as the Board’s construction requires.” Id. at 5-6 (annotating Ex. 1003, Figs. 12, 13). Patent Owner contends that “Zavracky proposes using these vertical connections ‘for the same reasons any lines otherwise restricted to a single layer are used.’” PO Resp. 10 (quoting Ex. 1003, 6:48-49). This argument supports Petitioner, because it shows that an artisan of ordinary skill easily would and could have re-routed planar connections for known circuitry using vias in a stack of chips or layers. Patent Owner argues that “in Akasaka, the 3-D chip design that uses vertical interconnections is only mentioned for a flip-chip design and a monolithic design, which means it is fabricated as a single piece of silicon with multiple layers.” PO Resp. 16. Patent Owner argues that “Akasaka explains that among the expected improvements are the use of ‘[s]everal thousands or tens of thousands of via holes’ in monolithic chips to take advantage of parallel processing.” Id. at 17 (quoting Ex. 1005, 1705). According to Patent Owner, Akasaka’s “flip-chip design is limited . . . in that ‘the number of connections are restricted by reliability and bump size constraints.’” Id. at 16 (quoting Ex. 1005, 1704). Contrary to these arguments, Akasaka states that with respect to flip chips, “the number of connections will be greatly increased by this technology.” Ex. 1005, 1704. Moreover, Akasaka refers to the flip chip structures in a section titled “3-D IC Structure.” Id. And contrary to Patent Owner’s arguments, Akasaka generally indicates that for all “3-D structures” “[s]everal thousands or several tens of thousands of via holes are present in IPR2020-01570 Patent RE42,035 E 52 these devices, and many information signal scan be transferred from higher to lower layers or vice versa through them.” Id. at 1705; see also Reply 20 n.6 (showing that 3-D die stacking with numerous chips was well-known (citing Ex. 1002 ¶¶ 328, 332); id. at 21 n. 8 (persuasively showing that Patent Owner “describes Akasaka’s teachings inaccurately” (citing Ex. 1002 ¶¶ 233-239; Ex. 1070 ¶¶ 59-66); Ex. 1070 ¶¶ 60-61 (disputing Dr. Souri’s testimony and stating that Akasaka shows “vertical interconnections between multiple chips and other chip attachment mechanisms,” and testifying that “Akasaka does not limit its via fabrication teachings to two layers or a monolithic chip”); Ex. 1002 ¶ 238 (testifying that chip stacking was known and “[t]here were many references teaching stacked dies with thousands of distributed connections, including those discussed in my technology backgrounder above, Section V, and the papers in Section IX”). Akasaka also indicates that even in 1986, about five years before the 2001 date of the invention, artisans of ordinary skill would have mixed flip chip technology and monolithic technology to provide stacked layers. “Mixing of assembly technology with monolithic chip technology can also provide 4 layers or 6 layers from 2-layer or 3-layer stacked monolithic ICs, respectively.” Ex. 1005, 1713. Even though claim 1 does not recite the “functional to accelerate” clauses (which claims 23, 24, 30, 32, and 33 recite), as motivation for all claims, as summarized above, Petitioner persuasively relies on Zavracky’s teaching that “this approach accelerates communication between the dies in the chip by way of ‘smaller delays and higher speed circuit performance.’” See Reply 6 (emphasis by Petitioner) (quoting Ex. 1003, 3:4-14). Petitioner persuasively notes that Chiricescu describes Zavracky’s teachings as IPR2020-01570 Patent RE42,035 E 53 “allow[ing] us” to build stacked circuit layers on a chip “with vertical metal interconnections (i.e., interlayer vias) placed anywhere on the chip.” See id. (quoting Ex. 1004, 232). Petitioner also persuasively argues that Chiricescu teaches the recited “functional to accelerate” clauses, with “significantly improved[d FPGA] reconfiguration time” through its “interconnected layers, including a memory layer configured as a cache for fast access to ‘configuration data . . . from memory off-chip.’” Id. at 6-7 (quoting Ex. 1004, 232) (emphasis by Petitioner). Other than disclosing an 8-bit configuration port as prior art with respect to Figure 3, the ’035 patent does not specify how many via interconnections the claimed “accelerate” functionality requires. See Ex. 1001 2:55-61 (describing stacking an FPGA with a “memory die” “for the purpose of accelerating FPGA reconfiguration” and “for the purpose of accelerating external memory references” and stacking “a microprocessor, memory and FPGA . . . for the purpose of accelerating the sharing of data”), 4:31-35 (describing cache memory purpose of serving “its traditional role of fast access memory”). Patent Owner limits Chiricescu as teaching only “the use of ‘on-chip’ memory to mitigate the time it takes to transfer configuration data from ‘off- chip,’ rather than making any use of Zavracky’s die-area vertical interconnections to transfer configuration data from the ‘on-chip’ memory into the FPGA.” See PO Resp. 28 (citing Ex. 1004, 1, 3). Patent Owner also argues that “[n]either Zavracky nor Chiricescu even contemplate using die- area inter-layer vertical interconnections to move data between a programmable array and a memory, such as is recited in Claims 4, 9, 14, 20, and 23-28.” Id. (citing Ex. 2011 ¶ 66). The record does not support this line of argument. As discussed above, Zavracky’s Figure 13 shows that IPR2020-01570 Patent RE42,035 E 54 Zavracky contemplates moving data on vertical buses between RAM memory 808 (and RAM memory on processor layer 806) and programmable array 802 (Ex. 1003, 12:29-39), and Chiricescu’s Figure 2 shows that Chiricescu contemplates moving data on “vertical metal interconnections (i.e., interlayer vias) placed anywhere on the chip” (based on Chiricescu’s characterization of Zavracky) between memory layer and the “sea of gates FPGA” RLB layer (Ex. 1004, II-232); see also Ex. 1004, II-232 § 1 (“Another feature of our architecture is that a layer of on-chip random access memory is provided to store configuration information.”). Also, Petitioner shows persuasively an artisan of ordinary skill would have recognized that speed improvement emanates partly from shorter interconnection distances and/or parallel processing using a larger number of vias (as compared to connections on the same plane). See Reply 6 (arguing Zavracky’s “approach accelerates communication between the dies in the chip by way of ‘smaller delays and higher speed circuit performance’” (emphasis by Petitioner (quoting Ex. 1003, 3:4-14)), and arguing that “Zavracky’s short interior ‘inter-layer connectors’ to stacked ‘random access memory . . . results in reduced memory access time, increasing the speed of the entire system.’” (emphasis by Petitioner (quoting 11:63-12:2)). Patent Owner concedes that the “[t]he ’951 Patent provides accelerated external memory references due to its technique of stacking a programmable array with a memory die using through-silicon vias (TSVs),” and Patent Owner quotes the ’951 patent as providing “increased” “bandwidth” and providing the “traditional role of fast access memory.” See PO Resp. 19-20 (quoting Ex. 1001, 4:31-44). These arguments support Petitioner’s showing, because the combined Zavracky-Chircescu-Akasaka stack includes IPR2020-01570 Patent RE42,035 E 55 the same structure, including numerous vias, as the short via connections as disclosed in the ’035 patent. Patent Owner agrees that “Chiricescu says . . . [that] ‘[t]he elimination of loading configuration data on an as needed basis from memory off-chip significantly improves the reconfiguration time for an on-going application.’” Sur-reply 5 (quoting Ex. 1004, 234). However, Patent Owner argues that “Petitioner concocts its hypothetical structure based on its demonstrably false claim that Chiricescu’s improved FPGA reconfiguration time ‘is achieved by its interconnected layers, including a memory layer configured as a cache for fast access to “configuration data . . . from memory off-chip.”’” Id. at 4 (quoting Reply 6-7; last internal quote quoting Ex. 1004, 234). Patent Owner contends that “Chiricescu says just the opposite.” Id. at 5 (citing Ex. 1004, 234). Contrary to this line of argument, Patent Owner mischaracterizes Petitioner’s showing. Petitioner shows that Chiricescu improves FPGA reconfiguration time because Chiricescu’s cache pre-stores and holds configuration data on-chip that it obtains from an external source (i.e., off- chip memory)--so that the FPGA (in Zavracky and Chiricescu) need not access that external (off-chip memory) source to load the FPGA through a “typical narrow configuration data port” (Sur-reply 5) during FPGA reconfiguration. See Reply 6-8; Ex. 1004, II-234 (“The elimination of loading configuration data on an as needed basis from memory off-chip significantly improves the reconfiguration time for an on-going IPR2020-01570 Patent RE42,035 E 56 application.”); infra § II.D.6 (discussing Petitioner’s reliance on Chiricescu’s cache memory teachings).19 19 Throughout its briefing, Patent Owner limits all “on-chip” advantages to a single die and confuses issues by arguing that even chips in the same stack are “off-chip” relative to each other, such that all “off-chip” vias are part of a “narrow” data port--even with thousands of vias connecting chips in the same stack as proposed by Petitioner. On the other hand, Petitioner, like Zavracky, generally refers to “off-chip resources” to include a resource outside of a chip stack. See e.g., Pet. 34 (“[T]he the POSITA would have understood, the programmable array [of Zavracky] processes data received from the microprocessor or ‘off-chip resources’ into and out of the user- defined protocol.”); Ex. 1003, 5:53-54 (“Paths which connect off-chip are routed to bonding pads 226 [Fig. 1], which are bonded to the chip carrier pins.”); Ex. 1070 ¶ 44 (Dr. Franzon noting that “Dr. Souri apparently means ‘chip’ here as limited to a single die.”). Patent Owner exploits this difference of use in the terminology to confound issues, characterizing, for example, Dr. Franzon’s testimony as follows: “Dr. Franzon’s testi[ies] that ‘off-chip access [e.g., off-chip memory separate from the FPGA die] can’t be, for example, 100,000 bits wide.” Sur-reply 9 (emphasis added) (second bracketed information by Patent Owner). As another example, Patent Owner argues that Petitioner “rel[ies] on Dr. Franzon’s discussion that thousands of interconnections for off-chip access of a 3D stacked structure is not feasible.” Id. (emphasis added (citing Reply 18)). This conflation represents the opposite of Dr. Franzon’s testimony and Petitioner’s showing. The thrust of Dr. Franzon’s testimony and Petitioner’s showing is that numerous stacked via connections in a stack of chips (dies) or layers of a single chip are better (faster) than connections on the same plane. See, e.g., Reply 17-18 (characterizing Dr. Franzon’s testimony as “noting the routine use of on-chip area-wide connections in 3D stacks, including his prior work.” (citing Ex. 1020; Ex. 1002 ¶¶ 47-51; Ex. 1070 ¶¶ 65, 68)); Ex. 1070 ¶ 44 (“But a POSITA would have recognized that [a] 3D chip that consists of multiple dies would do a better job than the 2D chip and provid[e] fast large connectivity. . . . The point here is that a shorter vertical interconnect allows for a shorter ‘longest path’ and a faster chip. This was commonly understood in the other art as well. . . . [such as] Akasaka’s . . . 3-D ‘high speed performance’” (citing Ex. 1005, 1705)). IPR2020-01570 Patent RE42,035 E 57 Addressing claims 4, 9, 14, 20, and 23-38 as a group, Patent Owner argues that “neither Zavracky nor Chiricescu even contemplate using die- area inter-layer vertical interconnections to move data between a programmable array and a memory, such as is recited in Claims 4, 9, 14, 20, and 23-38.” PO Resp. 28. As noted in summarizing Petitioner’s analysis of claim 4 above, claim 4 recites “[t]he processor module of claim 1 wherein said second integrated circuit die element comprises a memory.” See Pet. 32. Claim 4 does not specifically require moving data between a programmable array and a memory or even the capability to do so. Claim 9 does not specifically recite a connection between the programmable array (FPGA) and memory--it recites a “system” in the preamble that includes those components. Claims 23, 24, and 28 also do not specifically require moving data between a programmable array and memory. See Pet. 44-47, 50 (addressing these claims); infra § II.D.6-8 (summarizing and addressing Petitioner’s showing and Patent Owner’s arguments for claims 23, 24, and 28). Rather, claim 23 and dependent claims 24 and 28 recite “a memory array stacked with and electrically coupled to said field programmable gate array.” Instead of a data transfer to or from memory, claim 25 recites “whereby said processor and said programmable array are operational to share data therebetween” (emphasis added). See Pet. 48-50; infra II.D.8. Although claim 25 recites a “reconfigurable processor” in the preamble, this is broad enough to include the capability for reconfiguration from an external memory source (i.e., external to Zavracky’s stack). Dependent claim 26 recites “[t]he reconfigurable processor module of claim 25 wherein said memory is operational to at least temporarily store said data,” so it may imply some ability to move shared data to memory as discussed above. See IPR2020-01570 Patent RE42,035 E 58 infra § II.D.8. Claims 36 and 38 recite electrical coupling between an FPGA and memory array, which also implicitly requires the ability to “move data between a programmable array and a memory.” In any event, even assuming a requirement to move data as argued, Patent Owner’s arguments are unavailing. As summarized above in connection with claim 1, Petitioner shows that Zavracky’s Figure 13 specifically shows via bus connections (i.e., electrical coupling) from PLD 802 to microprocessor 804/806, RAM memory 808, and also RAM memory associated with microprocessor 806. Ex. 1003, Fig. 13, 12:29-39; supra § II.4. Chiricescu also shows electrical coupling between a memory layer and FPGA layer for configuring the FPGA, as Petitioner also shows. See, e.g., Pet. 15-16 (showing that “Chiricescu . . . describes configuring the FPGA as a processing element (‘multiplication of a 4-bit variable,’ . . . and accelerating the reconfiguration of the FPGA as a processing element by utilizing the on-3D-chip memory to ‘significantly improve[] the reconfiguration time’” (quoting Ex. 1004, II-234)). Moreover, Petitioner relies on the combined teachings of the references and shows persuasively that moving data using numerous inter-layer vias was well-known to produce distinct increased speed advantages, as noted above and below in connection with claims 1 and 23-29. See supra II.D.4; infra §§ II.D.6-8. Also, with respect to independent claim 9, as summarized above (§ II.D.4), Petitioner shows that it would have been obvious and well-known by artisans of ordinary skill for systems to move or transfer data between an FPGA and memory. See Pet. 38 (showing data bus lines between the recited claim elements in admitted prior art Figure 1 of the ’035 patent as IPR2020-01570 Patent RE42,035 E 59 evidencing the knowledge of the skilled artisan and relying on Zavracky’s teachings for its similar showing). Patent Owner addresses claims 3, 11, 19, and 28 as a group. These dependent claims recite “wherein said second integrated circuit die element comprises a microprocessor” or “wherein said processor of said second integrated circuit die element comprises a microprocessor.” Patent Owner argues that because Chiricescu discloses storing configuration data in on- chip memory, removing data “from the microprocessor cache and plac[ing it] in the FPGA’s on-chip memory,” per “the approach of Zavracky- Chircescu,” “mak[es] it much harder for the microprocessor, as recited in Claims 3, 11, 19, and 28.” PO Resp. 28-29 (citing Ex. 2011 ¶ 67). Patent Owner contends that this approach “result[s] in significantly decreased processing speeds for any data that might be shared between Chiricescu’s FPGA and Zavracky’s microprocessor, thus not leading to an improvement in the reconfiguration time.” Id. at 29. These arguments do not address Petitioner’s showing and the scope of claims 3, 11, 19, and 28. None of the claims require, and Petitioner does not propose, removing data from a microprocessor cache, or removing it and placing it in another on-chip memory. See Pet. 31-32, 40, 43, 50. Here, Patent Owner explains that Chiricescu’s FPGA and Zavracky’s microprocessor and FPGA “might” share data by using Zavracky’s microprocessor cache memory. See infra § II.D.8.20 Assuming this is 20 This argument contradicts Patent Owner’s arguments advanced with respect to claims 25-29 that sharing data between a microprocessor and FPGA from an “on-chip” memory would not have been obvious. See infra § II.D.8. IPR2020-01570 Patent RE42,035 E 60 correct, Petitioner relies generally on a Akasaka’s teachings as motivation to provide a separate memory layer to provide cache coherence. Pet. 19-20 (arguing that “the POSITA knew of the need for replicated ‘common data memory’ in stacked designs, including as taught in Akasaka, to enable, e.g., multi-processor cache coherence” (citing Ex. 1002 ¶ 236; Ex. 1034, 466- 469; Ex. 1005, 1713, Fig. 25). Patent Owner’s arguments do not address this persuasive rationale, but support it. Petitioner also relies on Chiricescu’s cache memory teachings to suggest a separate memory layer in addressing claims 23, 24, 30, 32, and 33. Infra § II.D.6, E.2 With respect to Patent Owner’s argument that Petitioner does not relate “arbitrary logic functions” to the claimed invention (see PO Resp. 29), Petitioner persuasively points out that Dr. Franzon testifies that a “POSITA would appreciate that Chiricescu teaches and praises as one of its ‘key features’ that its FPGA can be ‘quickly reconfigured’ to implement ‘arbitrary logic.’” See Reply 17 (quoting Ex. 1002 ¶¶ 215-217). In other words, in context, Petitioner persuasively shows that changing logic functions by reconfiguring (i.e., on the fly) an FPGA in stacked dies or layers using numerous distributed via connections to memory increases reconfiguration speed and produces other benefits, including the ability to perform different logic functions quickly. See Pet. 17-18. As another example, Petitioner argues persuasively that “[i]mproved reconfiguration times through this integration would predictably mitigate undesirable packet flow interruption when reconfiguring.” Id. Petitioner also persuasively argues that “a POSITA would have taken Chiricescu’s suggestion of a[n] FPGA to perform ‘arbitrary logic functions,’ Ex. 1004, 233, as a cue to enhance and expand upon the packet processing task performed by the IPR2020-01570 Patent RE42,035 E 61 programmable logic device in Zavracky, e.g., to perform image and signal processing tasks that would have taken advantage of co-stacked microprocessors and memories as taught in Zavracky.” Id. at 19 (citing Ex. 1002 ¶¶ 229-30; Ex. 1005, 1705; Ex. 1003, 12:25-30; Ex. 1004, II-232; Ex. 1058, 41; Ex. 1048)). Addressing claims 1-38 as a group, Patent Owner argues that Petitioner fails to show the obviousness of connecting “large numbers of vertical interconnections between an IC die with a programmable array and any other type of die.” PO Resp. 41. Contrary to this argument, which repackages arguments addressed above, Petitioner shows it would have been obvious for the reasons noted and well within the skill of an ordinary artisan. See Reply 16-19; Pet.19-20 (citing, inter alia, Ex. 1002 ¶¶ 237-38, 41-51 (citing and describing additional successful prior art including art with programmable arrays)); supra § II.D.4; infra § II.D.6, 8. Patent Owner contends that “merely disclosing the availability of large numbers of vertical interconnections between IC dies (as Akasaka does), does not demonstrate that a POSITA would or could have employed those interconnections between a programmable array and any other type of IC die with a reasonable expectation of success.” PO Resp. 41-42. To support this argument, Patent Owner argues that “the ’035 Patent itself does not purport to have invented TSVs (or any other types of ‘contact points distributed throughout the surfaces of said die elements . . . [which] traverse said die elements through a thickness thereof’).” Id. at 42 (citing Ex. 1001, 2:19-23). Advancing this point, Patent Owner admits that the ’035 patent “disclos[es] that the various embodiments of the ’035 Patent were enabled by Tru-Sci Technologies’ process.” Patent Owner similarly argues that it IPR2020-01570 Patent RE42,035 E 62 invented “use cases for such contact points (e.g., interconnecting a programmable array with a different type of IC).” Id. at 42. The record does not support this line of argument. The ’035 patent also states “the use of the through-die area array contacts 70 . . . . is not known to be possible with any other currently available stacking techniques since they all require the stacking contacts to be located on the periphery of the die.” Ex. 1001, 5:13-20 (emphasis added). This disclosure and others (including the disclosure of speed and bandwidth gains, reduced power and signal strength based on short via connections (id. at 4:62-67)) suggests that through-vias throughout the dies (as opposed to merely on the periphery) is a concept central to the disclosed and claimed invention. Moreover, the ’035 patent provides a low level of detail in block form relating to connecting some contact points together for these alleged “use cases,” further supporting the finding that the central focus of the invention was the large number of vias throughout the dies and implying that artisans of ordinary skill already knew how to connect circuits together (in parallel or otherwise) regardless of the types of circuits number of contacts involved. See, e.g., Ex. 1001, Fig. 4, Fig. 5; Ex. 1002 ¶ 98 (discussing Figures 4 and 5), ¶¶ 235- 236 (describing known implementations of parallel processing using stacked dies and testifying that “[b]eing able to do that in one massive shot over the image or set of frames in parallel would have been recognized as an advantageous way to apply Akasaka’s teaching to the Zavracky-Chiricescu combination” (citing Ex. 1048 (Villasenor); Ex. 1021 (Koyanagi)), ¶ 332 (describing stacked structures with numerous vias throughout the dies as “ubiquitous in the prior art” (citing Ex. 1020, 9-10; Ex. 1021, Fig. 4, 17; Ex. 1028, Fig. 9). IPR2020-01570 Patent RE42,035 E 63 And as Petitioner persuasively explains, bus connections between a programmable array, memory, and a processor in these “use cases” were already taught in at least Zavracky (programmable array interconnected to memory and processor) and Chiricescu (programmable array interconnected to memory), and the teaching and advantages of a large number of interconnections between dies was well known. See, e.g., Ex. 1009 (Alexander with large number of vertical interconnections between programmable array dies), Ex. 1021 (Koyanagi with large number of vertical interconnections between processor and memory dies), Ex. 1020, 2-10 (survey paper by Dr. Franzon describing general applicability and advantages of “area interconnection” with table listing “companies which provide area interconnection between stacked [chips]”). Reply 21. Also, based on the above discussion, Petitioner does not rely on “merely disclosing the availability of large numbers of vertical interconnections between IC dies,” as set forth above. See PO Resp. 41. As another example, Petitioner relies on Zavracky’s teaching of “interconnection pads [for signals to] run in a vertical direction (the third dimension) between functional blocks” (Ex. 1003, 2:43-52) and descriptions involving Figures 12 and 13, which show similar buses connecting memory, FPGA, and a microprocessor. See Reply Br. 10; supra § II.D.4. Patent Owner also argues that Petitioner provides no argument, let alone evidence, demonstrating that modifying the combination of Zavracky and Chiricescu to provide the type of wide configuration data port responsible for the accelerating features of the challenged claims (or to arrange a microprocessor and programmable array such that the two components share data) was either known in the art or within the skill of a POSITA. IPR2020-01570 Patent RE42,035 E 64 PO Resp. 32. This argument repackages arguments, including unavailing claim construction arguments, addressed above in connection with claim 1 and below in connection with 23-25. See supra § II.D.4; infra §§ 6, 8. Other than numerous via connections, none of the challenged claims here recite or require other structure of a WCDP. Sharing data between a microprocessor and programmable array was well within the knowledge of an artisan of ordinary skill (as, for example, admitted for in connection with prior art Figure 1 of the ’035 patent as discussed in connection with claims 9 and 25 above and as disclosed in Zavracky’s Figure 13). Petitioner shows that implementing a WCDP in the context of the challenged claims, which Figure 5 of the ’035 simply depicts as a black box, at most involves connecting large numbers of vias to connect circuits on stacked dies, and that such a scheme provides for parallel processing for different types of well-known circuits, all of which also was well-known and taught by the prior art of record. See supra § II.D.4, infra §§ 6, 8; Reply 9 (discussing a WCDP versus a narrow configuration port). Based on the foregoing discussion and a review of the full record, including evidence and arguments addressed in sections below that tend to overlap to a certain extent with issues in the instant section due to the format of the Response, Petitioner persuasively shows that claims 1-22, 36, and 38 would have been obvious. 6. Claims 23 and 33 Claims 23 and 33 are similar to claim 1, with the added limitations, “wherein said memory array is functional to accelerate external memory references to said processing element.” Similar to the “programmable array” of claim 1, the “processing element” of claims 23 and 33, is a “field IPR2020-01570 Patent RE42,035 E 65 programmable gate array” (FPGA). Petitioner relies on its showing with respect to claim 23 to address claim 33. See Pet. 52-53. Petitioner relies its showing with respect to claim 1, including relying on Zavracky’s programmable logic array 802 as the claimed FPGA and random access memory 808 as the claimed memory array. See Pet. 44-47, 52-53. Petitioner also relies on the combined teachings of Zavracky and Chiricescu: “Chiricescu describes a system where the focus of the 3D module is on a FPGA layer and a memory layer designed to accelerate external references (and specifically, the reconfiguration data) to the FPGA layer (a programmable array), again providing a programmable array module.” Id. at 45 (citing Ex. 1004 at II-234; Ex. 1002 ¶¶ 282-288). Petitioner also relies partly on its showings above with respect to the second integrated circuit in limitations [1.2] and [1.4], to include Zavracky’s memory array stacked and electrically coupled to the first IC programmable array, connected via multiple connection points. See id. at 24-25 (addressing limitation [1.2] relying on vertical buses, stacking, via holes, etc.), 28 (addressing limitation [1.4], which refers to limitation [1.3], collectively relying on multiple via connections including an array of contacts to provide vertical connections), 45 (referring to the analyses of limitation [1.2] and claim 2). For example, with respect to claim 2, Petitioner contends that “Chiricescu literally describes Zavracky as teaching technology ‘to build 3-D layered FPGAs which can have vertical metal interconnections (i.e., interlayer vias) placed anywhere on the chip.’” Id. at 30 (quoting Ex. 1004, II-232; reproducing Ex. 1003, Fig. 13, which shows multiple via bus layers). IPR2020-01570 Patent RE42,035 E 66 In addition to the multiple short through-vias, Petitioner also relies on Chiricescu’s RAM “cache memory” array teachings to show that on-chip memory (chips or layers in the same 3-D stack) accelerates configuration times relative to off-chip (chips or layers not in the same stack): The Zavracky-Chiricescu-Akasaka Combination provides this element. Chiricescu observes that “[t]he main bottleneck in the implementation of a high performance configurable computing machine is the high configuration time of an FPGA.” Ex. 1004 at II-232; Ex. 1002, ¶¶304-07. This bottlenecking problem is caused in part by having to load configuration data from off-chip memory. Chiricescu’s proposed solution used a “memory layer” where the “random access memory is provided to store configuration information.” Ex. 1004 at II-232. Rather than having to go “off-chip” each time new FPGA reconfiguration data is referenced, Chiricescu’s random access memory (i.e., a memory array) acts as a “cache memory” for that reconfiguration data, accelerating the FPGA (processing element)’s access to those external memory references. Ex. 1004, II-234. Therefore, the Zavracky-Chiricescu-Akasaka Combination, which includes Chiricescu’s FPGA and memory layers, provides this claim element. Ex. 1002 ¶¶304-07. Pet. 46-47. Petitioner also relies on “the Zavracky-Chiricescu-Akasaka Combination, which includes Chiricescu’s FPGA and memory layers.” Id. at 47 (citing Ex. 1002 ¶¶ 304-307). As summarized above in connection with claim 1, Petitioner relies on the knowledge of the artisan of ordinary skill and provides several reasons for combining the references to arrive at stacked chips with short via connections, for example, to increase processing speed based on shorter connections (decreasing propagation delays), increase bandwidth, and to increase processing based on parallel processing- -thereby meeting the “functional to accelerate” limitation. Pet. 7-12, 16-20. Addressing claims 23 and 33 as a group, Patent Owner contends that “[t]he Zavracky-Chiricescu-Akasaka combination fails to teach or suggest a IPR2020-01570 Patent RE42,035 E 67 3-D processor module that includes a second integrated die element, separate from a first integrated die element having a programmable array, including a ‘memory array is functional to accelerate external memory references to said processing element.’” PO Resp. 19. According to Patent Owner, “Chiricescu suffers precisely the same problems as the prior art distinguished in the ’035 Patent,” because Chiricescu’s’ “narrow configuration data port still loads configuration data ‘in a byte serial fashion and must configure the cells sequentially.’” Id. at 21 (quoting Ex. 1001, 3:66-4:1; citing Ex. 2011 ¶ 57). Patent Owner also argues that the “claims require” a “wide configuration data port.” Id. at 20. Patent Owner also asserts that “as Dr. Franzon acknowledges, Chiricescu describes only a narrow configuration data port between the RLB [routing logic block] and memory layers.” Id. at 21 (citing Ex. 2012, 80:10-22). Patent Owner also argues that “because Petitioner has not demonstrated that its combination of references ‘accelerates external memory references to said processing element’ over the baseline of the relatively narrow configuration port distinguished in the ’035 Patent (and taught in Chiricescu), Petitioner’s argument fails.” Id. at 22 (citing Ex. 1001, 1:44-49, 4:42-47; Ex. 2011 ¶ 58). Patent Owner also indicates the claims require “utilizing a portion of the memory array as a wide configuration data port including buffer cells.” Id. (citing Ex. 1001, 4:47-52). These arguments do not undermine or address Petitioner’s specific showing. Regarding separate wafers or dies, the Petition quotes Zavracky as disclosing “dies” and “individual dies,” and persuasively argues that “[b]y the references to interconnected circuit elements or dies, the POSITA would IPR2020-01570 Patent RE42,035 E 68 have understood Zavracky to be describing stacked layers of integrated circuit die elements and depicting these in Fig. 13 and other figures.” Pet. 22 (quoting Ex. 1003, 4:63-65; citing id. at Fig. 6, Ex. 1002 ¶¶ 278- 280). Regarding the WCDP claim construction arguments, apart from numerous via connections as set forth in our claim construction (supra § II.C), the challenged claims do not require other structure of a WCDP or buffer cells under our claim construction, and the specification does not describe the WCDP (depicted as black box) in Figure 5 as part of a memory array. See supra § II.C; Ex. 1001, Fig. 5. As Petitioner persuasively argues and as summarized above, the Petition relies on the combined teachings of Zavracky, Chiricescu, and Akasaka to teach the “functional to accelerate clause,” and this combination is wider than a narrow port or any baseline. See Reply 4-9. As Petitioner also persuasively argues, even if the claims require a WCDP, according to Patent Owner’s expert in the IPR2020-01020, IPR2020-01021, and IPR2020-01022, a “configuration data port . . . is . . . just a data port used for configuration . . . And data port is just an interface to send data from one place to another.” Id. at 9 (quoting Ex. 1075, 163:8-163:21). “And ‘the reason it’s a very wide configuration data port is because it has a lot of connections through these TSVs between the memory die and the FPGA die.’” Id. (quoting Ex. 1075, 157:23-158:3). In other words, under Petitioner’s persuasive showing, even if the claims require a WCDP, the combined teachings meet the challenged claims for the reasons noted. Petitioner also persuasively shows that Patent Owner “misrepresents Dr. Franzon’s testimony” regarding an alleged narrow port in Chiricescu. IPR2020-01570 Patent RE42,035 E 69 See Reply 11. As Petitioner persuasively argues, “Dr. Franzon’s cited testimony: (1) has nothing to do with Chiricescu; (2) was given in response to a question about Trimberger; and (3) was discussing the connection to “an off-chip memory” Id. (citing Ex. 2012, 80:10-22). Dr. Franzon’s cited deposition testimony supports Petitioner. Dr. Franzon’s cited deposition testimony refers to Trimberger in the context of “off-chip memory that loads in through the data port,” and Dr. Franzon testifies “a POSITA would interpret figure 5 [of the ’035 patent] as [including an undepicted] similar narrow structure on the left of the very wide configuration data port” to load data from an external source. See Ex. 2012, 80:3-22. In other words, Dr. Franzon’s testimony does not describe Chiricescu’s stacked memory layer as using a narrow port to transfer reconfiguration data to the RLB (with FPGA gates) layer from an “on-chip” memory within the 3-D stack. See Ex. 1004, Fig. 2; supra § II.D.2. Even if claims 23 and 33 require the capability to process data in parallel through the “functional to accelerate” limitations, as it shows for claim 1 (§ II.D.4), Petitioner persuasively shows that the Zavracky- Chiricescu-Akasaka 3-D module uses numerous vias throughout the dies to transfer data between the dies--i.e., acting to accelerate all manner of data and signals in parallel. See, e.g., Pet. 16 (showing that Akasaka teaches that “‘tens of thousands of via holes’ permit parallel processing by utilizing the many interconnections,”; “as a result of this parallel processing, ‘the signal processing speed of the system will be greatly improved’”; and “[d]ue to ‘shorter interconnection delay time’ arising from stacking and ‘parallel processing’ made possible from the area-wide interconnects, Akasaka states IPR2020-01570 Patent RE42,035 E 70 that ‘twice the operating speed is possible in the best case of 3D ICs’ as compared to conventional designs” (quoting Ex. 1005, 1705)), 19 (arguing that “it was a predictable advantage and also suggested by Akasaka itself that applying Akasaka’s distributed contact points, e.g., in the 3D stacks of Zavracky or Chiricescu, would increase bandwidth and processing speed through better parallelism and increased connectivity” (citing Ex. 1002 ¶ 233; Ex. 1005, 1705)). As Petitioner also argues, Patent Owner’s “‘narrow data port’ arguments are contrary to Chiricescu’s teachings” and do not address the combined teachings of Chiricescu, Zavracky, and Akasaka. Reply 12 (citing PO Resp. 20-21). Petitioner notes that Zavracky, which Chiricescu references, describes “interconnects as being ‘placed anywhere on the chip’ without restriction.” Id. (quoting Ex. 1004, 232 (emphasis added). In addition, Petitioner notes that Chiricescu “discloses ‘three separate layers with metal interconnects [including a “memory layer”] between them.’” Id. (quoting Ex. 1004, 232) (addition by Petitioner) (emphasis omitted). Vias running everywhere throughout the different stacked layers or dies as Zavracky, Chiricescu, and Akasaka individually and collectively teach distinguish over any alleged narrow port, and Petitioner provides well- known reasons for employing wide data ports, such as allowing for increased bandwidth and parallelism. See Pet. 7-12, 16-20; Ex. 1001, 5:16- 21 (describing “through-die array contacts 70 . . . routed up and down the stack in three dimensions” as “not known to be possible with any other currently available stacking techniques since they all require the stacking contacts to be located on the periphery of the die,” so that by placing IPR2020-01570 Patent RE42,035 E 71 contacts throughout, “cells that may be accessed within a specified time period is increased”). Patent Owner also argues that “[b]ecause Petitioner does not allege that any ‘external memory references’ occur in Chiricescu (let alone that such references are accelerated), Petitioner cannot have met its burden to establish that Claims 23, 24, and 33 are obvious.” PO Resp. 23.21 According to Patent Owner, “Petitioner misinterprets the term ‘external memory references,’ suggesting that this term too can be satisfied simply by storing a certain type of data in Chiricescu’s memory.” Id. (citing Pet. 47; Ex. 1002 ¶ 47). Patent Owner also argues that “memory references are not data, but are instructions directed to a particular place memory address [sic] in memory.” Id. (citing Ex. 2011 ¶ 60; Ex. 2015, 181; Ex. 2012, 49:11- 50:1). Dr. Souri’s cited declaration testimony does not tie his opinion that “[a] skilled artisan understands that memory references are not data” to claims 1, 5, 10, 16, and 23 as viewed in light of the ’035 patent specification. See Ex. 2011 ¶ 60. In addition to citing Dr. Franzon’s deposition testimony, which does not support Dr. Souri as indicated above, Dr. Souri cites “Ex. 2015 at 181.” This particular extrinsic evidence, which includes a single page out of what appears to be a text book, is not helpful because it does not have anything to do with accelerating memory references, and it describes types of “operands,” which are not at issue in the ’035 patent. Ex. 2015, 181 (“The third type of operand is a memory reference.”). In other words, Dr. Souri’s testimony is conclusory as it does not address how this extrinsic evidence 21 Claim 24 depends from independent claim 23. We address claim 24 below. See infra § III.D.7. IPR2020-01570 Patent RE42,035 E 72 relates to the recited “functional to accelerate external memory references” clause as recited in claim 23 and in the context of the cache memory or reconfiguration scheme as set forth in the ’035 patent specification. See Ex. 2011 ¶ 60 (citing Ex. 2015, 181). Patent Owner and Dr. Souri also do not explain clearly how the cited deposition of Dr. Franzon supports Patent Owner. See PO Resp. 23 (citing Ex. 2012, 49:11-50:1; Ex. 2011 ¶ 60); Ex. 2012, 49:11-50:1 (generally testifying that “Chiricescu’s FPGA processing element” is “agnostic” as “to what actually is stored in it”). Petitioner persuasively shows that caching external memory references in a stacked cache memory satisfies the “functional to accelerate” limitations relative to loading them from off-chip (outside of the stack), at least because of “caching” and “the use of short electrical paths, or significantly increased number of connections” including “Akasaka’s area- wide distributed interconnects.” See Reply 8 (citing Pet. 13-31, 44-47); see also id. at 13 (discussing hitting the cache with external memory references (citing Ex. 1002 ¶¶ 215-216; Ex. 2012, 42:9:14, 48:6-50:1). Petitioner also persuasively explains that even under Patent Owner’s narrow reading of “external memory references,” as related to memory addresses, Chiricescu teaches it because the memory address references will “hit” the cache. See Reply 12-13 (citing Ex. 1002 ¶¶ 215-216). Supporting Petitioner, Dr. Franzon persuasively testifies at the cited paragraphs of his declaration as follows: 215. . . . . The POSITA would recognize that what Chiricescu is teaching is to use that memory as a “cache” . . . . By doing so, the FPGA’s external memory references . . . will be accelerated because [they] will “hit” in the “cache” and be returned from the on-chip memory without having to go off-chip. IPR2020-01570 Patent RE42,035 E 73 216. Chiricescu is thus teaching to the POSITA to accelerate memory lookups that are directed to the external chip by sending them instead to the on-chip memory, perhaps keeping a relevant set of data to the application. This is what Chiricescu means when it says that “a management scheme similar to one used to manage cache memory can be used to administer the configuration data.” Ex. 1002 ¶¶ 215-216; Reply 13 (quoting part of the same two paragraphs). As Petitioner also persuasively argues, the ’035 patent does not limit “external memory references” in particular, but it does refer to cache memory and enhancing reconfiguration speed with such memory. See Reply 13 (citing Ex. 1001, 2:11, 2:25, 4:31, 4:57-58); Ex. 1001, 4:31-36 (referring to “cache memory 66” as serving its “traditional role of fast access memory,” and also including accessing by “both the microprocessor 64 and FPGA 68 with equal speed,” in the context of “reconfigurable computing systems”). Patent Owner also argues that “[b]ecause the claims require a ‘memory array is functional to accelerate external memory references to said processing element,’ Petitioner’s focus on the type of data stored in the array misses the mark.” PO Resp. 22. Contrary to this argument, as discussed above, Petitioner relies on a cache memory array as combined in a 3-D stack with short via connections, not the type of data. As discussed throughout this Final Written Decision, the Petition persuasively relies on such short and numerous distributed vias as structure for the “functional to accelerate” clauses, because such structure provides shorter path delays and allows for increased bandwidth and parallel data transfer. See supra §§ II.D.3 (Akasaka’s parallel processing and multiple via teachings), II.D.4- 5 (analyzing claim 1 motivation (which applies here) as Petitioner shows as IPR2020-01570 Patent RE42,035 E 74 including, inter alia, increased bandwidth, parallel processing, and decreasing path delays); Pet. 8-12 (background knowledge of an artisan of ordinary skill includes stacking chips with multiple distributed vias to minimize latency and maximize bandwidth), 16-20 (similar, listing multiple reasons to combine Zavracky, Chiricescu, Akasaka, including to accelerate data via shorter interconnection delay times, parallel processing, increased operating speed, etc.). Essentially, the cache memory relied upon by Petitioner carries all of these advantages, because it is within the 3-D stack instead of “off-chip.” In the Sur-reply, Patent Owner argues that “[t]he entire point of Chiricescu is that it achieves accelerated FPGA configuration by storing configuration data ‘on-chip’ so that it does not need to load configuration data from off-chip.” Sur-reply 5. Patent Owner also argues that “all off- chip connections are carried out through a typical narrow configuration data port, that suffers the same problems as the prior art distinguished in the ’035 Patent.” Id. Patent Owner then argues that “moving Chiricescu’s cache memory off-chip (i.e., into Zavracky’s 3D stacked memory die) eliminates the benefit gained from moving the memory on-chip, [so] a POSITA would not have contradicted Chiricescu’s fundamental teachings to arrive at Petitioner’s proposed combination.” Id. at 5-6. These arguments mischaracterize Petitioner’s showing and confuse the issues as discussed in the previous section. See supra § II.D.5; note 19. Patent Owner essentially conflates narrow ports having large signal delays over long electrical planar paths with “all off-chip connections” as applying to Zavracky’s 3-D stack (by referring to each separate chip in Zavracky’s modified 3-D stack as “off-chip” and ignoring the central fact that each chip IPR2020-01570 Patent RE42,035 E 75 connects to the other chips by numerous short vias). There is no support for this line of argument. Moreover, “Dr Franzon not[ed] the routine use of on- chip area-wide connections in 3D stacks, including his prior work.” Reply 18 (citing Ex. 1002 ¶¶47-51; Ex. 1070 ¶¶ 65; Ex. 1020; see also Ex. 1004, Fig. 2, II-232 § 1 (describing “on chip random access memory . . . provided to store configuration memory”--i.e., the memory layer of Figure 2); supra note 19. Patent Owner agrees that Chiricescu discloses “on-chip cache memory” as a separate layer in a chip, which further suggests a separate memory layer in a stack of dies. See Sur-reply 5. Nevertheless, Patent Owner contends that “the movement of Chiricescu’s on-chip cache memory to Zavracky’s off-chip memory would throttle” speed gains. Sur-reply 5. For the reasons explained above, this line of argument confuses issues and mischaracterizes Petitioner’s showing. See supra note 19. Chiricescu’s teachings bolster Zavracky’s FPGA teachings, and Petitioner shows that in this context, Zavracky describes a memory layer, microprocessor layer, and FPGA layer in a 3-D stack with each layer or chip connected by numerous short vias to increase speed. See, e.g., Pet. 14-15; Ex. 1003, Fig. 13. Patent Owner’s attempt to conflate all “off- chip” narrow port disadvantages to Zavracky’s modified stack of chips by calling that stack “off-chip” is unsupported. See Sur-reply 5. As Petitioner persuasively shows throughout its briefing, Zavracky’s stack of chips, connected by numerous vias, and bolstered by Akasaka’s numerous via and Chiricescu’s FPGA teachings, operates just like Chiricescu’s “on-chip” circuit layers in a single chip connected by numerous vias in terms of speed and acceleration. See Reply 6-7 (“Zavracky’s short interior ‘inter-layer connectors’ to stacked ‘random access memory . . . results in reduced IPR2020-01570 Patent RE42,035 E 76 memory access time, increasing the speed of the entire system,’” and “Chiricescu also teaches the acceleration advantages and ‘significantly improve[d FPGA] reconfiguration time’ achieved by its interconnected layers, including a memory layer configured as a cache for fast access to ‘configuration data . . . from memory off-chip.’” (quoting Ex. 1003, 11:63- 12:2; Ex. 1004, 23[4])), 7 (noting Akasaka’s “acceleration advantages” based on “teaching, e.g., that ‘[h]igh-speed performance is associated with shorter interconnection delay time and parallel processing’ and that ‘shortening of interconnections and signal transfer through vertical via holes in the 3-D configuration provides advantages for the design of large-scale systems.’” (quoting Ex. 1005, 1705)). In other words, as Petitioner shows, in addition to “stacking techniques,” “[t]he Zavracky-Chiricescu-Akasaka Combination also discloses the other ways that the ’035 patent even arguably implies increases speed-i.e., through caching, the use of short electrical paths, or significantly increased number of connections.” Id. at 8 (citing Pet. 13-31, 44-47); Ex. 1070 ¶ 44 (“[A] POSITA would have recognized that [a] 3D chip that consists of multiple dies would do a better job than the 2D chip and provid[e] fast large connectivity. . . . The point here is that a shorter vertical interconnect allows for a shorter ‘longest path’ and a faster chip.). Petitioner also persuasively addresses Patent Owner’s argument that the claims require acceleration over a “baseline” and other related arguments. See PO Resp. 20-21; Reply 12 (persuasively arguing that the combined teachings contribute to acceleration, the combination does not include a “narrow port,” and “Dr. Franzon testified in both his declaration and deposition that the Zavracky-Chiricescu-Akasaka combination provides IPR2020-01570 Patent RE42,035 E 77 acceleration compared to the baseline of other prior art with different structural characteristics.” (citing Ex. 1002 ¶¶ 212, 215-17, 304-05; Ex. 2012, 28:9-21, 28:9-21, 29:15-33:15)); see also supra §§ II.C (claim construction); II.D.1 (discussing claim construction and analysis of claim 1 in relation to prior art Figure 3’s 8-bit narrow port--i.e., one type of baseline). Zavracky indicates that 32 bit microprocessors were routine in 1993, years before the effective date of the invention, indicating that Zavracky’s microprocessor buses at least handled 32 bits in parallel. See Ex. 1003, 1:6-8 (continuity date of 1993), 1:31-40 (discussing prior art microprocessors). As noted above, Patent Owner indicated during the Oral Hearing that the challenged claims embrace devices transfer data over a port that “could be as small as 32 bits . . . if you have a small FPGA, right? If you want to update something in parallel, you could update 32-bit with 32 bits?” Tr. 49:1-9; supra § II.C (claim construction). Addressing claims 23, 30, and 33 together, Patent Owner argues that “major modifications would need to be made to the combination of Zavracky and Chiricescu in order to configure a stacked module to meet the acceleration limitations of Independent Claims 23, 30, and 33.” PO Resp. 31. Patent Owner explains that this major modification requires a “wide configuration data port (or other similar structure) between the memory and the FPGA.” Id. Patent Owner also argues that such a modification would “alter Chiricescu’s principle operation, which relies on an entirely different strategy for routing data throughout the FPGA, namely its narrow RLB Bus and its ‘routing layer,’ which Chiricescu declares ‘is of critical importance since it is used for the implementation of the interconnection of the non- IPR2020-01570 Patent RE42,035 E 78 neighboring RLBs.’” Id. at 31-32 (quoting Ex. 1004, 2) (emphasis by Patent Owner). Here, Patent Owner concedes that “the ’035 Patent discloses a memory array that achieves the claimed acceleration (i.e., utilizing a portion of the wide configuration data port), which significantly reduces the amount of time it takes to move data from a memory die into a programmable array.” PO Resp. 32 (emphasis added). Patent Owner does not describe what “portion” of the WCDP (which Figure 5 of the ’035 patent depicts as a black box) that the claimed “functional to accelerate” limitations require. In any event, as Petitioner argues and as adopted as our claim construction above, the ’035 patent shows that “functional to accelerate” limitations include “a number of vertical contacts distributed throughout the surface of and traversing the memory die in a vertical direction (vias) to allow multiple short paths for data transfer between the memory array and processing element.” See supra § II.C (claim construction). For the reasons explained above in connection with claim 1 and within this section, the combined teachings of Zavracky, Chiricescu, and Akasaka satisfy the “functional to accelerate” limitation of claim 23. See supra II.D.4-5. With respect to Chiricescu’s principle of operation, as Petitioner also persuasively argues, no “‘modifications’ are required to Chiricescu at all because the Petition’s combination involves ‘fold[ing] in Chiricescu’s teachings (including using stacked memory to reconfigure[] the FPGA) with Zavracky’s 3D stacks.” Reply 17-18 (quoting Pet. 17). Even if employing Chiricescu’s FPGA structure also suggests implementing its routing layer on a separate layer, contrary to Patent Owner’s arguments, Chiricescu does not describe its routing layer as a narrow port, as also explained within the IPR2020-01570 Patent RE42,035 E 79 instant section above. See id. at 18 (noting that Dr. Franzon did not admit Chiricescu includes a narrow port and citing Dr. Franzon’s testimony that on-chip area-wide connections in 3-D stacks were well-known (citing Ex. 1002 ¶¶ 47-51; Ex. 1070 ¶¶ 65, 68)). Also, Chiricescu’s Figure 2 depicts connections between the memory layer, routing layer, and RLB layer (a “sea-of-gates FGPA structure”) with connections that are distinct from the RLB bus. Ex. 1004, II-232 § 2.1, Fig. 2. Chiricescu notes that “routing congestion will also be improved by the separation of layers,” further suggesting that vias connected throughout including to the routing layer is not a narrow port. Id. at II-232. As Petitioner persuasively argues, “Chiricescu describes ‘vertical metal interconnections (i.e., interlayer vias),’ and ‘three separate layers with metal interconnects between them.’” Reply 16 (citing Ex. 1004, II- 232). Also, Chiricescu’s “express ‘architecture is based on’ technology developed by Zavracky at Northeastern University.” Id. (quoting Ex. 1004, II-232). And Chiricescu states that Zavracky’s architecture provides “3-D layered FPGAs which can have vertical metal interconnections (i.e., interlayer vias) placed anywhere on the chip.” Ex. 1004, II-232 (emphasis added). Therefore, contrary to Patent Owner’s arguments, Chiricescu’s principle of operation does not require a narrow port. See also Reply 16 (“The combination involves ‘fold[ing] in Chiricescu’s teachings (including using stacked memory to reconfigure the FPGA) with Zavracky’s 3D stacks.’” (citing Pet. 17)). Moreover, increasing via connections based further on Akasaka’s teachings would have been obvious by facilitating more connections between well-known available circuits such as memory, IPR2020-01570 Patent RE42,035 E 80 FPGA, and processors. See, e.g., Reply 19 (“Zavracky and Chiricescu envision connections ‘anywhere on the die.’” (citing Pet. 14-15; Ex. 1002 ¶¶ 41-51, 237-238)); Pet. 20 (“Akasaka’s distributed contact points would have been the logical extension to Zavracky and Chiricescu’s teaching of connections anywhere, especially in view of the POSITA’s background knowledge.” (citing Ex. 1002 ¶ 239)). Accordingly, Patent Owner’s arguments alleging “major modifications . . . in the combination of Zavracky and Chiricescu in order to configure a stacked module to meet the acceleration limitations of Independent Claims 23, 30, and 33,” related arguments including the “principle [of] operation” of Chiricescu, and claim construction arguments, as summarized above, are unavailing. We adopt and incorporate Petitioner’s showing as to claims 23 and 33, as set forth by the Petition and summarized above, as our own. See Pet. 7- 20, 44-47, 52-53. Based on the foregoing discussion and a review of the full record, including evidence and arguments addressed in sections above and below that may overlap with issues in the instant section due to the format of the Response, Petitioner persuasively shows that claims 23 and 33 would have been obvious. 7. Claims 24 and 30 Claim 24 depends from claim 23 and recites “[t]he programmable array module of claim 23 wherein said memory array is functional to accelerate reconfiguration of said field programmable gate array as a processing element.” Petitioner contends that “[t]he ‘external memory references’ analyzed in [23] comprise reconfiguration data, thereby providing this claim. Chiricescu describes that the accelerated IPR2020-01570 Patent RE42,035 E 81 reconfiguration data is used to reconfigure the FPGA as a processing element.” Pet. 47 (citing Ex. 1004, II-234 (describing “when the FPGA is reconfigured from performing A x B to A x C or vice versa.”); Ex. 1002 ¶¶ 304-07). Independent claim 30 is materially similar to dependent claim 24 (both reciting, inter alia, “wherein said memory array is functional to accelerate reconfiguration of said field programmable gate array as a processing element”). Petitioner refers to its showing of independent claims 1 and 23 and dependent claim 24 to address claim 30. Id. at 51-52. In other words, as discussed in the previous section addressing claims 23 and 33, Petitioner persuasively shows that the combined teachings accelerate external memory references (which include reconfiguration data) to the FPGA processing element, showing that the “memory array is functional to accelerate reconfiguration of said field programmable gate array as a processing element.” Addressing claims 24, 30, and 32 as a group, Patent Owner argues that “[t]he Zavracky-Chiricescu-Akasaka combination fails to teach or suggest a 3-D processor module that includes a second integrated die element, separate from a first integrated die element having a programmable array, wherein the ‘memory array is functional to accelerate reconfiguration of said field programmable gate array as a processing element.’” PO Resp. 23-24.22 Patent Owner recites the “functional to accelerate memory references” and “functional to accelerate reconfiguration” clauses, points to 22 The analysis of claim 32 is below. Claim 32 depends from claim 31, and Petitioner contends that the combination of Zavracky, Chiricescu, Akasaka, and Trimberger would have rendered claims 31, 32, and 34 above. See infra § II.E.2. IPR2020-01570 Patent RE42,035 E 82 Petitioner’s “same rationale” with respect to claims 23 and 33 discussed in the previous section (§ II.D.5), and concludes that claims 24, 30, and 32 “are therefore patentable.” Id. at 24 (noting that “Petitioner relies on the same rationale for this claim element as it did for the element discussed directly above, i.e. ‘memory array is functional to accelerate external memory references to said processing element’”). Patent Owner’s arguments with respect to claims 24, 30, and 32 as outlined herein do not undermine Petitioner’s persuasive showing as summarized above including for the reasons discussed above in connection with claims 23 and 33. See Pet. 46- 47, 51-52; supra § II.D.6. We adopt and incorporate Petitioner’s showing as to claims 24 and 30, as set forth by the Petition and summarized above, as our own. See Pet. 7- 20, 47, 51. Based on the foregoing discussion and a review of the full record, including evidence and arguments addressed in sections above and below that tend to overlap to a certain extent with issues in the instant section due to the format of the Response, Petitioner persuasively shows that claims 24 and 30 would have been obvious. 8. Claims 25-29 Like independent claim 17, independent claim 25 tracks the limitations of claim 1, and recites at least three die elements (instead of at least two as in claim 1), with the three die elements including a programmable array, processor, and memory electrically coupled together as in claim 17. See supra § II.D.4 (analyzing claims 1 and 17). Claim 25 also recites “whereby said processor and said programmable array are operational to share data therebetween.” IPR2020-01570 Patent RE42,035 E 83 Addressing claim 25, Petitioner relies on its showing for claims 1 and 17, including Zavracky’s disclosure of programmable logic array 802 in a stacked 3-D processor module with microprocessor layers 804 and 806 as Figure 13 depicts, and Chiricescu’s teaching of a 3-D chip comprising FPGA, memory, and routing layers. See Pet. 21-29, 41-43, 47-50. Petitioner also asserts that with respect to Zavracky’s Figure 13, “each of the programmable array, microprocessor, and memory are pair-wise stacked with and electrically coupled with each other.” Id. at 25. Petitioner also relies Akasaka’s teachings and on similar motivation as for claims 1 and 17. See id. at 17-20, 49-50 (“As discussed, §VII.A.4, a POSITA would have been motivated to employ Akasaka’s thousands of via holes in the context of Zavracky.” (citing Ex. 1002 ¶¶ 233-39, 347-48; Pet. § VII.A.4)). Addressing the claim 25 limitation “whereby said processor and said programmable array are operational to share data therebetween,” Petitioner relies partly on Akasaka’s disclosure of 3-D chips wherein “memory data are kept common by the interlayer (vertical) signal [so that] each processor can use the common memory data.” Pet. 49 (emphasis by Petitioner) (quoting Ex. 1005, 1713). In addition, Petitioner argues that “the POSITA knew of the need for replicated ‘common data memory’ in stacked designs, including as taught in Akasaka, to enable, e.g., multi-processor cache coherence.” Id. at 19-20 (citing Ex. 1002 ¶ 236; Ex. 1034, 466-469; Ex. 1005, 1713, Fig. 25). Petitioner further explains that “[t]hat structure would be more difficult to accomplish with a limited number of interconnections as in Zavracky,” further motivating “[a] POSITA . . . to seek out Akasaka’s distributed contact points in order to build a ‘common data memory.’” Id. at 20 (citing Ex. 1002 ¶ 237). IPR2020-01570 Patent RE42,035 E 84 Petitioner also relies on Akasaka’s teaching that that “information signals can be transferred” through “several thousands or tens of thousands of via holes . . . present in these devices” to further suggest employing Akasaka’s “thousands of via holes in the context of Zavracky” as further suggesting the claimed data sharing feature. Pet. 49-50 (first two quotes quoting Ex. 1005, 1705; citing Ex. 1002 ¶¶ 233-239, 347-348). As noted throughout this Final Written Decision, Petitioner also relies on known benefits of increased speed, bandwidth, and capability for parallel processing based on well-known teachings, to suggest stacking layers, including memory layers, using numerous vias, to combine the teachings of Zavracky, Chiricescu, and Akasaka. See id. at 8-9, 16-20. Petitioner explains that Zavracky also teaches that its programmable logic 802 is an FPGA and serves as “an intermediary between ‘the microprocessor and any off-chip resources.’” Pet. 48-49 (citing Ex. 1003, 12:28-36). Petitioner also relies on Zavracky’s “[i]nterconnect lines” operating as a “data bus.” Id. at 49 (quoting Ex. 1003, 6:39-42). According to Petitioner, a “POSITA would have recognized that communication between ‘the microprocessor and any off-chip resources’ via the FPGA (under the Zavracky-Chiricescu-Akasaka Combination as explained in [1.1], [1.2] and [2]) means that data is shared between the microprocessor and the FPGA.” Id. (citing Ex. 1002 ¶ 342). Claims 26-29 depend from independent claim 25. Claim 26 recites “wherein said memory is operational to at least temporarily store said data.” See Pet. 50. Petitioner argues that “[t]he POSITA would have understood that memory is-by definition-operational to at least temporarily store data.” Id. (citing Ex. 1002 ¶ 308 (citing Ex. 1039 (trade dictionary defining IPR2020-01570 Patent RE42,035 E 85 memory)). Petitioner also relies on Akasaka’s shared memory as discussed above and further below in connection with claim 25. See id. at 47-50 (citing Ex. 1005, 1713). Petitioner asserts that the added claim limitations of claims 27-29, which recite an “FPGA,” a “microprocessor,” and a “memory array,” respectively, read on Zavracky’s stack as depicted in Figure 13. See id. at 50-51 (relying on the analysis for claims 18-20, which in turn rely on the analysis for claims 1 and 3-6 (see id. at 43)). Patent Owner groups claims 25-29 together and argues that “[t]he Zavracky microprocessor and programmable logic are not operational to share data, such as might be stored in a stacked memory die, for example.” PO Resp. 25 (citing Ex. 2011 ¶ 63). Patent Owner reproduces the following diagram from Dr. Souri’s declaration to illustrate its point: Ex. 1012 ¶ 63. According to Patent Owner, Zavracky’s microprocessor on the left does not share data with the FPGA (PLD) on the right, because “it is the output of Zavracky’s microprocessor that is sent to the FPGA.” PO Resp. 25 (citing Ex. 1012 ¶ 63). Patent Owner attempts to distinguish “sharing” data and “transferring” data by arguing that “[t]he claims require more than a processor transferring data to a field programmable.” See PO Resp. 24-25. Neither the ’035 patent specification nor claims 25-29 requires this distinction. Nevertheless, Patent Owner argues that shared data “might be stored in a stacked memory IPR2020-01570 Patent RE42,035 E 86 die, for example.” PO Resp. 25 (emphasis added). Patent Owner similarly argues in its Sur-reply that “[a] POSITA would recognize that this data on the stacked memory die is literally ‘data shared between a microprocessor and an FPGA.’” Sur-reply 12 (citing Ex. 2011 ¶ 64; Ex. 1001, 1:59-67, 2:47-51, 4:31-36) (emphasis added). Contrary to this line of argument, claims 25-29 do not require a “stacked memory die” to hold data to support the recited shared data functionality. Although claim 26 recites “wherein said memory is operational to at least temporarily store said data,” claim 26 is broad enough to read on Zavracky’s modified memory (which is operational to store the shared data) after the microprocessor and FPGA (are operational to) share it per claim 25. See Pet. 50 (arguing that “[t]he POSITA would have understood that memory is-by definition-operational to at least temporarily store data” (citing Ex. 1002 ¶ 308 (citing Ex. 1039 (trade dictionary defining memory)).23 Moreover, even under Dr. Souri’s diagram of Zavracky’s process, Zavracky’s microprocessor processes the input data to create the shared output data, and then transfers that shared output data onto the data bus and then to the FPGA. See Reply 13-14 (citing Ex. 1070 ¶¶ 73-74; Ex. 1083); Ex. 1070 ¶ 73 (quoting Ex. 1083, 1:26-34 (describing computers “shar[ing] data” by “transfer[ing] data”)); Pet. 49 (citing Ex. 1002 ¶¶ 342, 349). As discussed further below, Petitioner also persuasively explains how 23 As indicated herein, Patent Owner does not address Petitioner’s persuasive showing for claim 26 separately from claim 25. Petitioner also persuasively relies on Akasaka’s shared memory for claims 25-29 as discussed further below. See Pet. 47-50 (citing Ex. 1005, 1713). IPR2020-01570 Patent RE42,035 E 87 Zavracky’s microprocessor and FPGA share and process the same data from off-chip resources to implement a user-defined protocol. See Pet. 48-49. Patent Owner also argues that Petitioner’s alternative theory based on Akasaka’s teaching and suggestion to share “‘common memory data’ does not cure this fundamental deficiency in Zavracky because it also does not involve any processing of data shared between a microprocessor and an FPGA (or any other type of chip).” PO Resp. 26. Claims 18-22 do not require “processing of [shared] data,” but even if the claims imply that interpretation, the combined teachings suggest it, as Petitioner persuasively shows as discussed next. To support its point, Patent Owner reproduces Zavracky’s Figure 25 as follows: PO Resp. 26. Figure 25(c) above depicts a “[c]ommon memory data system for a ‘3-D memory chip’ wherein processors 1, 2, n (on the left) share data on memory layers 1, 2, n (on the right).” Ex. 1005, 1713. Akasaka states IPR2020-01570 Patent RE42,035 E 88 that “memory in each chip belongs to corresponding independent microprocessors in the same layer, and the memory data are kept common by the interlayer (vertical signal) transfer.” Id. (emphasis added). Patent Owner argues that “although Akasaka proposes that memory data is ‘kept common by the interlayer (vertical) signal transfer,’ the individual microprocessors do not process any shared data because each only processes the data in its corresponding memory.” PO Resp. 26-27. This argument misses the mark, because Akasaka’s system transfers the same data between the memories so that each processor is operational to process the same data. Stated differently, Akasaka contradicts Patent Owner’s argument that transferring the same data at one memory location (the “common” data in Akasaka) to another memory location shows a lack of data sharing--i.e., Akasaka describes the data as “common.” See Ex. 1005, 1713. As to sharing data between a processor and an FPGA, Petitioner relies on Akasaka’s teaching as suggesting the sharing of common data through vertical data transfers in the combined 3-D structure of Zavracky, Chiricescu, and Akasaka, instead of relying on a bodily incorporation of the processor memory layer scheme of Akasaka. See Pet. 49-50; Reply 15 (arguing that Patent Owner “attacks the physical die-stacking technique in Akasaka-but Akasaka is not relied upon to teach die-stacking” and “Zavracky already teaches stacked memories that are interconnected to other dies in the stack, and also teaches memories can be at any layer” (citing Ex. 1003, 11:63-12:2, Figs. 10, 12)). Claims 25-29 are agnostic as to how the FPGA and microprocessor share data--i.e., with or without a separate memory in each layer--i.e., claim 25 recites “whereby said processor and IPR2020-01570 Patent RE42,035 E 89 said programmable array are operational to share data therebetween” without reference to the “memory” recited earlier in the claim. As proposed by Petitioner, it would have been obvious for the FPGA and microprocessor of Zavracky-Chiricescu, based on Akasaka’s teachings, to share data using numerous (e.g., thousands) of vertical vias to implement the data transfer and thereby increase processing speeds and bandwidth. See Pet. 49-50 (citing Pet. § VII.A.4 (reasons to combine the references); Ex. 1002 ¶¶ 233-239; 347-348). For example, as Petitioner shows, using Akasaka’s teaching to share data using thousands of vertical vias would have “increase[d] bandwidth and processing speed through better parallelism and increased connectivity.” See Pet. 19 (§ VII.A.4), 49-50; Ex. 1005, 1705; Reply 6-7 (citing known advantages of numerous vertical vias). Petitioner persuasively shows that artisans of ordinary skill would have recognized that sharing common data by an FPGA and processor using the dense via structure of Akasaka increases processing speed and ensures cache coherency. See Pet. 19-20 (Ex. 1002 ¶¶ 236-237; Ex. 1005, 1705). Patent Owner’s arguments do not address Petitioner’s more general showing that a “POSITA would have recognized that communication between ‘the microprocessor and any off-chip resources’ via the FPGA (under the Zavracky-Chiricescu-Akasaka Combination as explained in [1.1], [1.2] and [2]) means that data is shared between [and processed by] the microprocessor and the FPGA.” Pet. 49 (citing Ex. 1002 ¶¶ 342-44, 349). In other words, Dr. Souri’s diagram above only refers to data from the PLD (FPGA) as “DATA SENT TO THE OUTSIDE WORLD,” but this analysis does not address Petitioner’s persuasive showing that data from the outside world (off-chip) sources passes through the FPGA as an intermediary to the IPR2020-01570 Patent RE42,035 E 90 microprocessor. See Pet. 48-49 (citing Ex. 1003, 12:28-36). At the cited passage, prior to describing Figure 13, Zavracky states that “[p]rogrammable logic arrays can be used to provide communication between a multi-layered microprocessor and the outside world.” Ex. 1003, 12:29-31. Zavracky also states that “programmable logic array 802 [an FPGA in Figure 13] can be programmed to provide for user-defined communications protocol between the microprocessor and any off-chip resources.” Id. at 12:36-37. Figure 13 shows bus connections on the PLD 802 (FPGA) to the outside world, with bus connections from PLD 802 to microprocessor 804/806 and memory 808. See Ex. 1003, Fig. 13, 12:29-39. Therefore, as Petitioner argues, Zavracky shows that communication occurs between the microprocessor and the FPGA, thereby teaching the sharing of data between the two (in at least one of the two directions). See Pet. 48-49. In addition, in advancing another argument, Patent Owner admits that the combination teaches data sharing: “[T[he approach of Zavracky- Chiricescu would result in a structure in which data is removed from the microprocessor cache and placed in the FPGA’s on-chip memory,” and “data . . . might be shared between Chiricescu’s FPGA and Zavracky’s microprocessor.” PO Resp. 28-29 (emphasis added). Further addressing claims 25-29 as a group, Patent Owner argues that “to modify the Zavracky-Chiricescu system with Akasaka, . . . the stacked memory layer of Chiricescu would need to be moved into its RLB layer because Akasaka requires each memory layer to be located on the same layer as its associated processor,” thereby requiring a “major modification” of Chiricescu. PO Resp. 36-37. Patent Owner similarly argues that implementing the combination requires “adding more structure to IPR2020-01570 Patent RE42,035 E 91 Chiricescu’s RLB layer, in the form of Akasaka’s memory, destroys Chiricescu’s principle of operation, which relies on moving as much structure out of the RLB layer as possible.” Id. at 37. This line of argument incorrectly assumes that Petitioner must show how to bodily incorporate the common memory teachings of Akasaka into Chiricescu’s structure as part of its obviousness showing. This argument is unavailing, because Petitioner relies on Zavracky’s 3-D stack structure, including its memory as a separate layer, as modified by the common memory teachings of Akasaka, without any modification to Chiricescu’s FPGA teachings required. The common memory teachings of Akasaka are agnostic as to the memory location. That is, Akasaka does not “require[] each memory layer to be located on the same layer as its associated processor.” See PO Resp. 36. Even though Figure 25 of Akasaka shows a stack of processors and memory, with a processor and memory on the same layer, nothing in Akasaka states that the memory cannot be elsewhere in the stack on a separate layer. Rather, Figure 25 shows all memories connected together electrically with each memory connected electrically to its respective processor. See Ex. 1005, Fig. 25. These electrical connections suggest to an artisan of ordinary skill that the memory layer’s location is less important than the electrical connections. See id. Moreover, Petitioner relies on Zavracky’s separate layer for each memory in a stack with via connections to enhance speed, as the combination suggests. See Reply 15 (“Zavracky already teaches stacked memories that are interconnected to other dies in the stack, and also teaches memories can be at any layer” (citing Ex. 1003, Figs. 10, 12, 11:63-12:2 (“[A]n additional layer or several layers of random access memory may be IPR2020-01570 Patent RE42,035 E 92 stacked . . . . This configuration results in reduced memory access time, increasing the speed of the whole system”)). Addressing 23-30 and 33-35 as a group, Patent Owner contends that “Petitioner’s arguments for combining Zavracky and Chiricescu (see Petition at 18) also fail because they are untethered from the Challenged Claims and do not establish that it would have been obvious to ‘combine[] these particular references to produce the claimed invention.’” PO Resp. 29 (quoting Metalcraft of Mayville, Inc. v. The Toro Co., 848 F.3d 1358, 1367 (Fed. Cir. 2017) (emphasis by Patent Owner).). Patent Owner argues that is insufficient to “accelerate external memory references to said processing element” or “accelerate reconfiguration of said field programmable gate array as a processing element,” and Petitioner fails to articulate any reason that Chiricescu’s alleged teaching of performing “arbitrary logic functions” is related to the claimed invention. PO Resp. 30. Contrary to these arguments, Petitioner provides persuasive reasons to provide numerous vias throughout the Zavracky’s layers or dies based on the collective teachings of the references, showing that it was well-known that providing such vias allows for speed increases, increased bandwidths, parallel processing, and further allowing for accelerated external memory references and reconfiguration of an FPGA through the additional use of cache memory, as discussed above in connection with claims 1, 23-25, 30, and 33. See supra §§ II.D.4-7. Petitioner’s Reply also summarizes Dr. Franzon’s testimony showing that improving reconfiguration times by using the stacked memory techniques (including the distributed vias) as suggested IPR2020-01570 Patent RE42,035 E 93 by the combined references accelerates memory references. See Reply 16- 17 (citing Ex. 1002 ¶¶ 215-17, 221-230, 302-303). Further addressing claims 23-30 and 33 as a group, Patent Owner contends that “Dr. Franzon admitted that a wide configuration data port that accelerates a programmable array’s external memory references to a stacked memory die as compared with the slow narrow bus disclosed in Chiricescu was not obvious at the time of the invention.” PO Resp. 33 (citing Ex. 2012, 71:19-72:1). Based on this characterization, Patent Owner also argues that “the wide configuration data port of the ’035 Patent provides precisely the answer to what Dr. Franzon admits was practically impossible at the time of the invention.” Id. (citing Ex. 2012, 71:19-72:1, 80:3-22; Ex. 2011 ¶ 73). Patent Owner adds that this “skepticism of Petitioner’s own expert demonstrates that the challenged claims are patentable.” Id. (citing Ex. 2011¶ 73). Contrary to this line of argument, Dr. Franzon does not admit that a wide configuration data port was not obvious, and does not admit that Chiricescu discloses a narrow data bus. See Ex. 2012, 71:19- 72:1, 80:3-22. Rather, at the cited deposition testimony, Dr. Franzon testifies that “off-chip access can’t be, for example, 100,000 bits wide.” Id. at 71:21-23 (emphasis added). Here, in context, Dr. Franzon states that “you can’t have that number of IO . . . . in [the] case of Trimberger and the ’226 patent [which is related to the ’951 patent, see IPR2020-01571] memory going form the external to the module.” Id. at 71:23-72:1 (emphasis added). Here again, Patent Owner conflates a narrow data port from a source “external to the module” (i.e., external to the claimed 3-D stack), with a wide data port from a memory within the stack to other chips in the stack. See supra note 19. IPR2020-01570 Patent RE42,035 E 94 Further grouping claims 23-30 and 33 together, Patent Owner argues that Petitioner has not produced a single reference or combination of references that teaches or suggests stacking a processor with a programmable array in a manner in which is operational to share data therebetween, or a memory array functional to accelerate external memory references or accelerate reconfiguration of FPGA. PO Resp. 31. This line of argument repackages arguments addressed in this section and above in connection with claims 1, 9, 23-25. See supra §§ II.D.5-6, 8. As noted above, Petitioner relies on a combination of references under obviousness to address the “functional to accelerate” clauses. As also discussed above, Zavracky’s Figure 13 explicitly illustrates a stacked die structure with PLD 802 (FPGA), microprocessor 804/806, RAM memory 808 (memory array), and RAM memory (memory array) associated with microprocessor 806, all connected together with buses so that the circuits are operational to share data therebetween. Ex. 1003, Fig. 13, 12:29-39.24 We adopt and incorporate Petitioner’s showing as to claims 25-29, as set forth by the Petition and summarized above, as our own. See Pet. 7-20; 47-51. Based on the foregoing discussion and a review of the full record, including evidence and arguments addressed in sections above and below that may overlap with issues in the instant section due to the format of the 24 As discussed below (§ II.E.1), Trimberger provides another example of the prior art showing the direct connection between a large memory plane (block memory with 100,000 bits) and an FPGA for parallel reconfiguration in one cycle. Ex. 1006, 22-23, Fig. 1. IPR2020-01570 Patent RE42,035 E 95 Response, Petitioner persuasively shows that claims 25-29 would have been obvious. 9. Summary After a full review of the record, including Patent Owner’s Response and Sur-reply and evidence, Petitioner shows by a preponderance of evidence that the combined teachings of Zavracky, Chiricescu, and Akasaka would have rendered obvious claims 1-30, 33, 36, and 38. E. Obviousness, Claims 31, 32, and 34 1. Trimberger Trimberger, titled “A Time-Multiplexed FPGA” (1997), describes an FPGA with on-chip memory distributed around the chip. Ex. 1006, 22. Trimberger teaches that the memory “can also be read and written by on- chip [FPGA] logic, giving applications access to a single large block of RAM.” Id. Trimberger teaches this “storage [can] be used as a block memory efficiently.” Id. at 28. Trimberger’s Figure 1 follows: IPR2020-01570 Patent RE42,035 E 96 Figure 1 of Trimberger above depicts eight planes of SRAM (static random access memory) for an FPGA. See Ex. 1006, 22-23. “The configuration memory is distributed throughout the die . . . . This distributed memory can be viewed as eight configuration memory planes (figure 1). Each plane is a very large word of memory (100,000 bits in a 20x20 device).” Id. at 22. Trimberger also teaches accessing each plane of memory as one simultaneous parallel transfer of 100,000 memory data bits to reconfigure the FPGA quickly: “When the device is flash reconfigured all bits in logic and interconnect array are updated simultaneously from one memory plane. This process takes about 5ns. After flash reconfiguration, about 24ns is required for signals in the design to settle.” Ex. 1006, 22. 2. Claims 31, 32, and 34 Petitioner contends claims 31, 32, and 34 would have been obvious over the combination of Zavracky, Chiricescu, Akasaka, and Trimberger. See Pet. 55-60. Except for the final limitations in independent claims 31 and 34, claims 31 and 34 recite limitations similar to claims 23 and 33. Petitioner relies on its showing with respect to claims 23 and 33 (addressed supra § II.D.6) to address the overlapping limitations of claims 31, 32, and 34. See id. Claim 32 is materially similar to claims 24 and 30, as they each recite the same “functional to accelerate reconfiguration” clause. To address claim 32, Petitioner refers to and relies on its analysis of claim 24 (which relies on the analysis of claim 23). Pet. 47, 59. As indicated above in the analysis of claims 23, 24, 30, and 33, Patent Owner groups claim 32 with claims 24 and 30. Supra § II.D.6-7. For the reasons outlined above, Patent Owner’s IPR2020-01570 Patent RE42,035 E 97 arguments with respect to claims 24 and 30 are unavailing. Supra § II.D.6- 7. The same arguments with respect to claim 32 also are unavailing. See id. Turning back to claims 31 and 34, limitation [31.4] and limitation [34.5] each recite “wherein said memory array is functional as block memory for said processing element.” Petitioner relies on Trimberger’s block memory teachings to address this limitation. See Pet. 58-60. According to Petitioner, Trimberger teaches that its co-located “memory is accessible as block RAM for applications,” that are running in the FPGA, i.e., that the memory “can also be read and written by on-chip [FPGA] logic, giving applications access to a single large block of RAM.” Ex. 1006, 22. Trimberger teaches that “the configuration storage to be used as a block memory efficiently.” [Id. at 28]. Pet. 58 (emphasis by Petitioner) (quoting Ex. 1006, 22, 28). Petitioner contends that it would have been obvious to employ Trimberger’s block memory to support fast local memory in FPGA applications like that in the combined teachings of Zavracky, Chiricescu, and Akasaka. See id. at 56-57 (citing Ex. 1002 ¶ 247; Ex. 1048). Petitioner also contends that “[t]he POSITA would have known that FPGAs have limited programmable logic space, and that for certain tasks it would be more cost-efficient and silicon- efficient to use the FPGA for reconfigurable processing and to use a separate task-dedicated memory element for block memory.” Id. at 57 (citing Ex. 1002 ¶ 247). Petitioner advances other reasons for the combination. See id. at 57-58 (characterizing Trimberger’s on-chip block memory as faster relative to off-chip memory). Patent Owner argues that “[i]ndependent claims 31 and 34 . . . require that the ‘memory array [that] is functional as block memory’ is on a separate IPR2020-01570 Patent RE42,035 E 98 chip from the ‘first integrated circuit die element including a field programmable gate array.’” PO Resp. 44. According to Patent Owner “Trimberger . . . teaches away from having its block memory and FPGA on different chips as it attributes its quick FPGA reconfiguration to the massive connectivity within the chip.” Id. (citing Ex. 1006, 22; Ex. 2011 ¶ 88); see also id. at 50 (same argument (citing Ex. 2011 ¶ 97)). Patent Owner primarily relies on this “within the chip” or “on-chip memory” argument as the basis for its allegations of lack of motivation, lack of a reasonable expectation of success, teaching away, requirement for major modifications, and other related arguments. See id. at 43-51. For example, Patent Owner argues that “implementing Trimberger’s FPGA structure in Petitioner’s combination would result in a complete redesign of the hypothetical 3-D stacked structure of the Zavracky- Chiricescu-Akasaka Combination,” because “the block memory is no longer stacked with the FPGA, but instead located on Trimberger’s FPGA die as on-chip memory.” Pet. 49 (citing Ex. 2011 ¶ 95). Patent Owner explains that “Trimberger’s FPGA structure requires that its configuration memory planes are located on the same die as the FPGA’s logic cells, so that the FPGA can quickly switch between different configurations.” Id. at 50 (citing Ex. 2011 ¶ 97). Patent Owner asserts that “Petitioner admits this.” Id. (characterizing the Petition as stating that Trimberger teaches a time multiplexed FPGA with on-chip memory distributed around the chip) (citing Pet. 56)). Based on these assertions, Patent Owner contends that evidence lacks as to “how or why a POSITA would have had a reasonable expectation of success in making the combination.” Id. at 45. IPR2020-01570 Patent RE42,035 E 99 Petitioner persuasively shows that Trimberger does not teach away or support Patent Owner’s related arguments based on the single-chip theory, including hypothetical re-designs, and lack of a reasonable expectation of success and motivation. Petitioner does not admit that Trimberger “requires that its configuration memory planes are located on the same die as the FPGA’s logic cells.” See PO Resp. 50 (citing Pet. 56); Pet. 56 (describing Trimberger’s on-chip memory without characterizing it as a requirement). Petitioner persuasively responds that Trimberger does not “criticize, discredit, or otherwise discourage investigation into the invention claimed,” merely because it discloses embodiments having block memory and an FPGA within the same chip. Reply 22 (quoting Depuy Spine, Inc. v. Medtronic Sofamor Danek, Inc., 567 F.3d 1314, 1327 (Fed. Cir. 2009)). Petitioner persuasively argues that Patent Owner’s “‘massive connectivity’ observations about Trimberger confirm that the POSITA would have been further encouraged to make the combination.” Id. at 23 (citing Ex. 1070 ¶¶ 44-45); see PO Resp. 50 (arguing Trimberger’s block memory includes “massive connectivity” with the FPGA). Petitioner’s response, supported by Dr. Franzon’s testimony, is persuasive. Trimberger’s Figure 1 shows eight different memory planes on a single chip. Ex. 1006, 22. Trimberger states that “[t]he entire configuration of the FPGA can be loaded from this on-chip memory in 30ns.” Id. Trimberger does not teach, and Dr. Souri does not testify, that Trimberger’s “on-chip memory” requires each memory plane to be on the same layer as the FPGA of a chip, such as a multi-layered chip or stack of chips. See id.; Ex. 2011 ¶ 97 (describing Trimberger as employing “massive connectivity within the chip”). IPR2020-01570 Patent RE42,035 E 100 Dr. Franzon explains credibly that “Trimberger’s one-cycle teachings would be improved by applying its teaching to a 3D chip.” Ex. 1070 ¶ 44. Dr. Franzon explains that Trimberger’s reconfiguration clock cycle “(i.e., the delay in Trimberger) is set [by] determin[ing] the length of the longest path after routing.” Id. (quoting Ex. 1006, 27). Then, Dr. Franzon testifies that “[t]he point here is that a shorter vertical interconnect allows for a shorter ‘longest path’ and a faster chip” and “[t]his was commonly understood in the other art.” Id. (noting that “Akasaka taught that 3-D ‘high speed performance’ was enhanced because ‘[i]n 2-D ICs, the longest signal interconnection length becomes several to ten millimeters, but in 3-D ICs the length between upper and lower layers is on the order of 1-2 μm.’” (quoting Ex. 1005, 1705); also noting that Zavracky teaches that “[i]n the proposed approach, shorter busses will result in smaller delays and higher speed circuit performance” (quoting Ex. 1003, 3:4-14) (emphasis by Dr. Franzon)). This testimony goes hand-in-hand with Petitioner’s showing as summarized above in connection with claims 1, 17, and 23-25. That is, Petitioner shows persuasively that the combined teachings of Zavracky, Chiricescu, and Akasaka suggest short conductor runs using numerous distributed vias of a 3-D multi-layer chip to increase speed and bandwidth, decrease path delays, and facilitate parallel processing. See supra §§ II.D.3-6, 8; Pet. 8-12 (background knowledge of an artisan of ordinary skill includes stacking chips with multiple distributed vias to minimize latency and maximize bandwidth), 16-20 (similar, listing multiple reasons to combine Zavracky, Chiricescu, Akasaka, including to accelerate data via shorter interconnection delay times, parallel processing, increased operating IPR2020-01570 Patent RE42,035 E 101 speed, etc.). The Petition also persuasively points to a “concern[] with the speed of access between the FPGA and the block of memory” as a reason to use Trimberger’s “block memory . . . combined with Zavracky-Chiricescu- Akasaka’s teaching of having the memory stacked and electrically coupled nearby.” Pet. 57. Supported by Dr. Franzon’s testimony, Petitioner also persuasively responds that arranging a block memory on a separate layer from an (FPGA) processing element is not a major modification and the evidence shows that how to do it would have been well within the level of ordinary skill. See Reply 24; Ex. 1070 ¶ 46 (“Dr. Souri does not understand the combination being made. The Zavracky, Chiricescu, Akasaka combination already has a memory and an FPGA. It is already connected via a wide-area distributed set of interconnections as taught in Akasaka.”). Petitioner persuasively points to the Petition as stating that “[t]he POSITA would have sought Trimberger’s teaching of using memory as a block memory and combined that with Zavracky-Chiricescu-Akasaka’s teaching of having the memory stacked and electrically coupled nearby.” Reply 24 (citing Pet. 57). In other words, Petitioner does not propose “‘moving’ Trimberger’s on chip memory” to the same layer as the FPGA in Zavracky-Chiricescu-Akasaka’s stack, contrary to Patent Owner’s argument. See PO Resp. 50; see also Sur-reply 20. Rather, Petitioner proposes modifying the existing memory of Zavracky’s modified 3-D stack to function as a block memory according to Trimberger’s teachings. See Pet. 57; Reply 24. Moreover, Trimberger’s eight plane memory design suggests different layers at least for each plane of memory, and challenged claim 31 does not require more than one of Trimberger’s block memory IPR2020-01570 Patent RE42,035 E 102 planes. See Pet. 54 (describing “us[ing] a separate task-dedicated memory element for block memory”); Ex. 1006, Fig. 1 (showing eight time multiplexed memory planes); Ex. 1070 ¶ 45 (testifying that in Trimberger’s Figure 1 (see supra § II.E.1), “the fat arrow with a line in the traditional representation of ‘many signals’ - i.e., this is suggesting an architecture where different ‘planes of memory’ (i.e., layers of a die in a 3-D stack) are transferred from the configuration SRAMs to the FPGA”).25 In any event, claims 31, 32, and 34 do not preclude eight separate memory layers in a stack, or all eight memory planes on the same layer in the stack, or a multiplexor to select the different memory planes. Patent Owner essentially argues that an artisan of ordinary skill could and would have connected eight memory planes to an FPGA on a single layer as Trimberger describes to obtain a single reconfiguration of 100,000 bits, but such an artisan could and would not have connected the same circuits on separate layers together using vias with a reasonable expectation of success. The record shows otherwise, for the reasons outlined above. Petitioner persuasively points to testimony by Dr. Franzon cited in the Petition, who in turn relies credibly on evidence of record, to show a reasonable expectation of success, showing that implementing block 25 As summarized above, each memory plane in Trimberger contains 100,000 bits of memory. Supra § II.E.1. Also, “[w]hen the device is flash reconfigured all bits in logic and interconnect array are updated simultaneously from one memory plane. Id.; Ex. 1006, 22 (emphasis added). Contrary to Patent Owner’s arguments in connection with claims 1 and 23- 25 discussed above, Trimberger provides another example of the prior art showing the connection of a large plane of memory (block memory) directly to an FPGA for reconfiguration in one cycle. IPR2020-01570 Patent RE42,035 E 103 memory with an FPGA was well-known in the prior art. See Reply 24 (citing Pet. 57; Ex. 1002 ¶ 145, 248; Ex. 1003, Figs. 12, 13; Ex. 1003, 11:63-12:2; Ex. 1002 ¶ 145); Ex. 1002 ¶ 145 (testifying that “Cooke also discloses that the ‘memory planes not being used for configuration may be used as memory,’ i.e., an extra memory block for use by the FPGA” (citing Ex. 1032, 2:50-52), Ex. 1002 ¶ 144 (testifying that Casselman shows connecting “memory . . . directly to FPGA . . . through address and data busses.” (citing Ex. 1026)). As discussed above in connection with claims 1 and 23-25, Petitioner persuasively outlines several good reasons to combine related teachings from the references to arrive at a 3-D stack, reasons that apply to Trimberger’s block memory. See Pet. 8-20, 55-58. For example, Petitioner notes that Trimberger teaches a block memory to provide access to a “single large block of RAM” such that memory “can . . . be read and written by on- chip [FPGA] logic.” Pet. 58 (quoting Ex. 1006, 22). Petitioner also states that implementing Trimberger’s block memory teachings with the 3-D chip combination as suggested by Zavracky’s “stack [of] memories together with processors or the programmable array” addresses “concern[s] with the speed of access between the FPGA and the block memory.” See id. at 57. Petitioner notes that “FPGAs have limited programmable logic space” suggesting “a separate task-dedicated memory element for block memory.” Id. Petitioner also persuasively argues that applying Trimberger as a separate layer of memory in the 3-D stack of Zavracky, Chiricescu, and Akasaka “would have merely been a combination of prior art elements according to known methods to yield a predictable result” and “would have been a well-known use of a memory,” showing a reasonable expectation of IPR2020-01570 Patent RE42,035 E 104 success in “improv[ing] on the memory options of the FPGA.” Id. As outlined above, the record supports Petitioner. Patent Owner repeats or repackages its arguments addressed above, by arguing that “Trimberger does not cure any of the aforementioned deficiencies,” “Chiricescu does not employ Zavracky’s interconnections to connect a memory die to an FPGA die,” and Petitioner does not show why or how “the modification would have been achieved with any reasonable expectation of success.” See PO Resp. 46. Contrary to these arguments, as outlined above, Petitioner relies on the combined teachings of the references and the knowledge of an artisan of ordinary skill, and Trimberger provides more and persuasive evidence as to how and why an artisan of ordinary skill would have employed block memory as a single plane or several planes as separate layers in a 3-D stack, including to enhance reconfiguration speeds between a large block of memory and FPGA by facilitating a large parallel data transfer of 100,000 bits in one clock cycle. We adopt and incorporate Petitioner’s showing as to claims 31, 32, and 34, as set forth by the Petition and summarized above, as our own. See Pet. 7-20, 55-60. Based on the foregoing discussion and a review of the full record, including evidence and arguments addressed in sections above and below that tend to overlap to a certain extent with issues in the instant section due to the format of the Response, Petitioner shows by a preponderance of evidence that the combined teachings of Zavracky, Chiricescu, Akasaka, and Trimberger would have rendered obvious claims 31, 32, and 34. IPR2020-01570 Patent RE42,035 E 105 F. Obviousness, Claims 35 1. Satoh Satoh, titled “Semiconductor Integrated Circuit, Method for Testing the Same, and Method for Manufacturing the Same,” describes using an FPGA to generate test stimuli to test memory elements on the same chip. Ex. 1008, code (54). In one embodiment, Satoh describes a method for testing this semiconductor integrated circuit is such that, in a semiconductor integrated circuit incorporating a variable logic circuit (FPGA) for outputting a signal indicating whether or not a circuit is normal [wherein] . . . a memory test circuit is built for testing the memory circuits in accordance with a specified algorithm . . . without using an external high- performance tester. Ex. 1008, 46.26 Satoh also describes a “memory array” and testing DRAMs (dynamic random access memory arrays) such that “a test circuit . . . for testing the DRAMs 150 to 180 is formed in the portion of the FPGA 120 . . . , and the DRAMs 150 to 180 are tested in succession.” See Ex. 1008, 15, Fig. 7. 2. Claim 35 Petitioner contends claim 35 would have been obvious over the combination of Zavracky, Chiricescu, Akasaka, and Satoh. See Pet. 60-63. Claim 35 is similar to claims 23 and 33 (see supra § II.D.6), including an FGPA electrically coupled to a memory array stacked therewith by a number of distributed contact points, but unlike claims 23 and 33, claim 35 does not include the “functional to accelerate” “wherein” clause and instead includes the following “functional to provide test stimulus” “wherein” clause: “wherein said contact points are further functional to provide test stimulus 26 Page citations refer to original page numbers. IPR2020-01570 Patent RE42,035 E 106 from said field programmable gate array to said at least second integrated circuit die element.” Petitioner relies on its showing with respect to the “Zavracky- Chiricescu-Akasaka Combination,” which includes its showing for claims 23 and 33. See Pet. 61 (citing Ex. 1002 ¶¶ 240-245), 62-63 (referring to its analysis of claim 33, which materially tracks its claim 23 analysis). According to Petitioner, “[i]t was well-known to test stacked modules in order to avoid the expense and waste of silicon by creating ‘dead’ chips, and improve yield.” Id. (citing Ex. 1002 ¶¶ 240-245; Ex. 1009; Ex. 1043). Petitioner states that “Satoh specifically praised the use of an FPGA to test ‘memory circuits’ for ‘improving yield and productivity of the semiconductor integrated circuit.’” Id. (quoting Ex. 1008, 47:23-27). Addressing the “functional to provide test stimulus” “wherein” clause, Petitioner explains that Satoh describes an FPGA that “generates a specified test signal [and] supplies the test signal to the memory circuit.” Pet. 63 (citing Ex. 1002 ¶¶ 350-359; Ex. 1008, 5:1-28, 49:32-37). Petitioner maintains that Satoh’s test signal suggests a “test stimulus” to a second integrated circuit memory array to evoke a response therefrom. See id. (citing Ex. 1008, 49:32-37; Ex. 1002 ¶ 358). Based on Satoh’s teaching, Petitioner explains that “[i]n the Zavracky-Chiricescu-Akasaka-Satoh Combination,” it would have been obvious to implement “the test signal . . . through the contact points between the FPGA of the first IC die element and the memory of the second IC die element,” because that “is how those elements are stacked and electrically coupled.” See id. (citing Ex. 1002 ¶ 359). IPR2020-01570 Patent RE42,035 E 107 In addition to avoiding “dead chips,” Petitioner cites other reasons to combine Satoh’s testing functionality with the 3-D chip of Zavracky- Chiricescu-Akasaka: Recognizing the need to test the 3D stack of the Zavracky- Chiricescu-Akasaka Combination, the POSITA would have sought out Satoh’s teaching of using a FPGA for testing the co- stacked memory to achieve known predictable benefits: rigorous testing while avoiding a separate testing chip’s (1) additional expense, (2) chip real estate, and (3) design complexity. Ex. 1002 ¶242. Moreover, (4) a FPGA is reusable: after being configured for testing in manufacture, the FPGA would then be reconfigured for its normal “in the field” purpose. Id. (citing Ex. 1045 (“Another advantage . . . is that after testing is complete, the reconfigurable logic (FPGA 28) can be reconfigured for post- testing adapter card functions.”); Ex. 1046). Pet. 61-62. Petitioner also relies on the following evidence and rationale to support a reasonable expectation of success: It was well known to use a FPGA to test circuitry with 2-D chips as taught by Satoh. Ex. 1002 ¶241 (citing Ex. 1043). The POSITA would have recognized Satoh’s teaching would readily apply to the 3-D chip elements in the Zavracky-Chiricescu- Akasaka Combination. This includes because such a combination would have been a routine use of an FPGA, whose testing ability was not dependent on structure. Ex. 1002 ¶¶242- 43. The result of this combination would have been predictable, by known FPGA testing to the 3D stack according to known methods to yield a predictable result. Ex. 1002 ¶244. Pet. 62. Patent Owner relies on the same unavailing arguments it advances with respect to claims 1 and 23-25 that we address above. See PO Resp. 51 (“Because Petitioner does not contend that Satoh cures any of the deficiencies of the combination of Zavracky, Chiricescu, and Akasaka, as IPR2020-01570 Patent RE42,035 E 108 discussed above with respect to Ground 1, its reliance on the same rationales for Ground 3 also fail.”) Patent Owner also argues that “Petitioner’s contention that a POSITA would be motivated to make the combination because it was well-known to test stacked die and Satoh tested memory elements on the same semiconductor chip (see Petition at 60-61) is divorced from the claimed invention.” PO Resp. 52. Patent Owner contends that “Petitioner’s generic rationale for using FPGAs for testing is wanting in particularity as to why a POSITA would combine the references as recited in the Challenged Claim.” Id. Patent Owner contends that “[w]hether the use of Satoh’s FPGA is beneficial for testing does not sufficiently explain why a POSITA would have combined the references to yield the claimed invention.” Id. at 53. Patent Owner contends that Petitioner’s rationale fails “as it lacks sufficient motivation of how or why a POSITA would have been motivated to use Satoh’s FPGA for testing with the hypothetical 3-D structure of Zavracky- Chiricescu-Akasaka ‘in the way the claimed invention does.’” Id. (quoting ActiveVideo Networks, Inc. v. Verizon Commc’ns, Inc., 694 F.3d 1312, 1328 (Fed. Cir. 2012)). Patent Owner’s arguments appear to accept Petitioner’s showing that applying Satoh’s testing structure and technique in “the hypothetical 3-D structure of Zavracky-Chiricescu-Akasaka” would have been “beneficial” and “predictable.” See PO Resp. 52-53. That is, Patent Owner characterizes the rationale as “generic” without disputing it. See id. In any event, Petitioner provides specific reasons related to specific recitations in the claims as outlined above, including tying Satoh’s testing of a memory array using FPGA testing circuitry to the similar claim elements IPR2020-01570 Patent RE42,035 E 109 in claim 35. For example, using Satoh’s FPGA test circuitry and memory testing teachings to avoid “dead chips” is a specific “beneficial” reason, and tying these teachings to FPGA contact points in the Zavracky-Chiricescu- Akasaka” stack to test memory in that stack also is specific. See Reply 25 (re-listing reasons supplied in the Petition, including, for example, “the known problem of the need to test stacked modules to avoid the expense and waste of silicon by creating ‘dead’ chips” (citing Ex. 1002 ¶ 241; Ex. 1009; Ex. 1020; Ex. 1043); Pet. 63 (explaining that “[i]n the Zavracky-Chiricescu- Akasaka-Satoh Combination, the test signal is sent through the contact points between the FPGA of the first IC die element and the memory of the second IC die element, which is how those elements are stacked and electrically coupled” (citing Ex. 1002 ¶ 359)). As Dr. Franzon also credibly explains, Satoh’s use of generating a test signal “within an FPGA” to test a memory array is agnostic “to the particular way in which the FPGA is stacked.” See Ex. 1002 ¶ 245 (“The POSITA would thus have realized that Satoh could be used to solve the existing need (which was also recognized by Ex.1043, for example) to achieve the benefits discussed above.”). In other words, Petitioner persuasively shows a reasonable expectation of success with specific reasons to combine, all supported by the record, including beneficial testing to avoid dead chips and maintain reliable memory to reconfigure the 3-D stack’s FPGA post-manufacture, thereby showing how to apply the teachings to the claimed 3-D stack as suggested by Zavracky, Chiricescu, and Akasaka. Specifically, claim 35 recites “wherein said contact points are further functional to provide test stimulus from said [FPGA] to said at least second integrated circuit die element,” and Petitioner persuasively applies Satoh’s teachings to these contact points in IPR2020-01570 Patent RE42,035 E 110 order to avoid dead chips. Another set of specific and persuasive reasons to combine is “using a FPGA for testing the co-stacked memory to achieve known predictable benefits: rigorous testing while avoiding a separate testing chip’s (1) additional expense, (2) chip real estate, and (3) design complexity.” Pet. 61. As Petitioner also persuasively argues, Petitioner’s “evidence-backed assertions are uncontroverted, specific to relevant teachings of the references, and explain why a POSITA would have sought the Zavracky- Chiricescu-Akasaka-Satoh Combination to reach the ’035 patent’s claims.” Reply 25 (citing Ex. 1070 ¶¶ 76-77). Patent Owner advances a new (unresponsive) argument in its Sur- reply that “[t]he references Petitioner and Dr. Franzon cite do not disclose testing of 3-D stacked processor but instead disclose that individual die are tested independently and prior to any 3D packaging.” Sur-reply 22. This argument is not relevant to a claim limitation at issue here. Claim 35 does not require packaging or preclude “provid[ing] test stimulus from said field programmable gate array to said at least second integrated circuit die element” prior to any packaging. We adopt and incorporate Petitioner’s showing as to claim 35, as set forth by the Petition and summarized above, as our own. See Pet. 7-20, 60- 63. Based on the foregoing discussion and a review of the full record, including evidence and arguments addressed in sections above and below that tend to overlap to a certain extent with issues in the instant section due to the format of the Response, Petitioner shows by a preponderance of evidence that the combined teachings of Zavracky, Chiricescu, Akasaka, and Satoh would have rendered obvious claim 35. IPR2020-01570 Patent RE42,035 E 111 G. Obviousness, Claim 37 1. Alexander Alexander, titled “Three-Dimensional Field-Programmable Gate Arrays” (1995), describes “stacking together a number of 2D FPGA bare dies” to form a 3-D FPGA. Ex. 1009, 253. Alexander explains that “each individual die in our 3D paradigm has vias passing through the die itself, enabling electrical interconnections between the two sides of the die.” Id. Alexander’s Figure 2 follows: Figure 2(a) shows vertical vias traversing a chip with a solder pad and solder bump on top, and Figure 2(b) shows a stack of chips prior to connection by solder bumps. Ex. 1009, 253. Alexander explains that stacking dies to form a 3-D FPGA results in a chip with a “significantly smaller physical space,” lower “power consumption,” and greater “resource utilization” and “versatility” as compared to conventional layouts. Ex. 1009, 253. 2. Claim 37 Claim 37 depends from independent claim 36 and recites “[t]he programmable array module of claim 36 wherein said third integrated circuit die element includes another field programmable gate array.” As noted above, independent claim 36 is similar to independent claims 1, 17, and 23, IPR2020-01570 Patent RE42,035 E 112 and Petitioner refers to its showing of claims 1, 5, and 23 to address claim 36. See supra §§ II.D.4, 6; Pet. 53. Through its dependency from claim 36, claim 37 essentially recites three stacked integrated circuit die elements, the first one “including” an FPGA, the second one “including” a memory array, with “said first and second integrated circuit die elements being coupled by a number of contact points distributed throughout the surfaces of said die elements,” and “a third integrated circuit die element includ[ing]” “another” FPGA “stacked with and electrically coupled to at least one of said first or second integrated die elements.” Therefore, the module of claim 37 essentially requires two FPGAs and a memory array, with the circuit that includes one of the FPGAs simply “electrically coupled” to one of the circuits that includes the other FPGA or memory array, and the latter circuits “coupled by a number of contact points distributed throughout the surfaces of said die elements.” Petitioner contends claim 37 would have been obvious over the combination of Zavracky, Chiricescu, Akasaka, and Alexander. See Pet. 63-66. Addressing the two stacked FPGAs of claim 37, Petitioner relies on Alexander’s teaching of stacked FPGAs in a 3-D package, and contends as follows: The POSITA would have known (as Zavracky notes) that multiprocessor systems were needed for “parallel processing applications,” for example, “signal processing applications.” Ex. 1003, 12:13-28, Fig. 12; Ex. 1002 ¶258. But in this context, the POSTIA would have appreciated Alexander’s teaching of stacked FPGAs as preferable over alternatives, such as (1) general purpose microprocessors running software (too slow), or (2) customized parallel hardware (too expensive and inflexible). The POSITA would have sought out Alexander’s multiple stacked FPGAs to enhance the Zavracky-Chiricescu-Akasaka IPR2020-01570 Patent RE42,035 E 113 Combination by upgrading it for this type of application. 1002 ¶259. Pet. 65. Petitioner contends that Alexander’s similar structure of multiple stacked FPGAs, as similar to multiple processors stacked with multiple memories of the Zavracky-Chiricescu-Akasaka Combination, evidences a reasonable expectation of success of stacking FPGAs with memories, with multiple dies stacked and vertically interconnected including using thousands of contact point vias (holes).” See Pet. 65. Petitioner also asserts that “[t]he result of this combination would have been predictable, simply combining the extra FPGA of Alexander with the existing 3-D stack according to known methods to yield a predictable result.” Id. (citing Ex. 1002 ¶¶ 260-261). Patent Owner responds that “[w]hether 3D FPGA dies are preferable over general purpose microprocessors or customized parallel hardware have no bearing on whether a POSITA would have been motivated to combine Alexander with Zavracky-Chiricescu-Akasaka to reach a 3-D processor module having ‘a third integrated circuit die element [that] includes another field programmable gate array.’” PO Resp. 54-55 (citing Ex. 2011 ¶ 100). This argument appears to accept Petitioner’s showing that FPGAs are preferable to processors in a 3-D stack. Petitioner’s unchallenged showing of faster FPGAs relative to general purpose processors in the 3-D stack of Zavracky-Chiricescu-Akasaka, where Zavracky contemplates multiple layers of processors, memory layers, and an FPGA, is a persuasive reason for the combination. See Ex. 1003, Fig. 12 (stacked multiple processor and memory layers/chips), Fig. 13 (stacked processor, memory, and PLA/FPGA layers/chips). IPR2020-01570 Patent RE42,035 E 114 Patent Owner also argues that Petitioner’s “conclusory rationale is further discredited by Petitioner’s suggestions elsewhere in the Petition that Chiricescu discloses a FPGA application that enhances Zavracky.” PO Resp. 55. In particular, Patent Owner argues that the Petition elsewhere suggest that a “POSITA would have taken Chiricescu’s suggestion of a FPGA to perform ‘arbitrary logic functions,’ . . . as a cue to enhance and expand upon the packet processing task performed by the programmable logic device in Zavracky, e.g., to perform image and signal processing tasks that would have taken advantage of co-stacked microprocessors and memories as taught in Zavracky.” Id. (quoting Pet. 18). Patent Owner argues that “there is no reason . . . to combine Alexander with Zavracky- Chiricescu-Akasaka,” because “Petitioner acknowledges that, Chiricescu, like Alexander, offers FPGAs to enhance parallel processing image and signal tasks of Zavracky’s microprocessor.” Id. (citing Ex. 2011 ¶ 101). Patent Owner’s arguments are unavailing. For example, Patent Owner concedes that “Chiricescu, like Alexander, offers FPGAs to enhance parallel processing image and signal tasks of Zavracky’s microprocessor.” PO Resp. 55. Dependent claim 37 does not preclude employing a microprocessor, because it is open-ended and recites “comprising” and “at least” a “first,” “second,” and “third integrated circuit functional element.” To address claim 37, Petitioner specifically and persuasively argues that “[t]he POSITA would have known (as Zavracky notes) that multiprocessor systems were needed for ‘parallel processing applications,’ for example, ‘signal processing applications.’” Pet. 65 (citing Ex. 1003, 12:13-28, Fig. 12; Ex. 1002 ¶ 258). Petitioner also repeatedly points to Zavracky’s microprocessors 804 and 806 in Figure 13 to address claim 1, reproduces IPR2020-01570 Patent RE42,035 E 115 Figure 13 in addressing claim 23 (which it relies upon to address independent claim 36), and refers to the “Zavracky-Chiricescu-Akasaka Combination.” See id. at 44-45 (quoting Zavracky as stating that its “invention relates to the structure [of] vertically stacked and interconnected circuit elements for . . . programmable computing.” (citing Ex. 1003, 12:28- 38, Fig. 13), 53 (referring to its analysis of claims 1, 5, and 23 to address claim 36). Therefore, Patent Owner’s characterization that Chiricescu and Alexander “offer[] FPGAs to enhance parallel processing image and signal tasks of Zavracky’s microprocessor” and Petitioner’s argument that Chiricescu suggests FPGAs for performing arbitrary logic functions and expanding packet processing tasks with microprocessors, are specific and persuasive reasons to employ FPGAs in the stack of Zavracky-Chiricescu- Akasaka-Alexander. See PO Resp. 55; Pet. 18. In other words, as Petitioner also persuasively argues, “[a]s to the ‘why,’ the Petition shows that (i) the POSITA would have been prompted to pursue a ‘multiprocessor system’ to facilitate ‘parallel processing applications’; and (ii) the POSITA would have viewed Alexander’s “stacked FPGAs as preferable over alternatives” for achieving such a system.” Reply 26 (citing Pet. 65; Ex. 1002 ¶¶ 257-61). “And as to the ‘how,’ the Petition explains that ‘the POSITA would have realized that using multiple FPGA dies in the stack as taught by Alexander would work in a straightforward manner similar manner to stacking multiple memories, or multiple microprocessors, as already taught in the Zavracky-Chiricescu-Akasaka Combination.’” Id. (quoting Pet. 65). Patent Owner also alleges that the Petition fails to explain how to combine the references with a reasonable expectation of success. PO Resp. IPR2020-01570 Patent RE42,035 E 116 55-57. Patent Owner alleges that other sections of Alexander . . . [that] Petitioner wholly ignores . . . . do not suggest . . . that using multiple FPGA dies would work in a straightforward manner, let alone in Petitioner’s proposed combination, so as to have a reasonable expectation of success.” Id. Patent Owner provides little support for this argument. See id. Contradicting Patent Owner, Alexander itself states that using multiple FPGAs in a stack results in a chip with “significantly smaller physical space,” lower “power consumption,” “shorter signal propagation delay,” and “greater resource utilization and versatility” due to the “increased number of logic block neighbors” as “compared with a circuit-board-based 2D FPGA implementation.” Ex. 1009, 253. In other words, Alexander suggests that stacked FPGAs simply implement the same circuitry of well-known single layer FPGAs, albeit with numerous advantages. Patent Owner also refers to sections in Alexander that describe thermal issues. PO Resp. 56. Patent Owner also argues that “Petitioner’s threadbare argument that the combination is based on known methods to yield a predictable result (see Petition at 65) is . . . untethered to the features of the claimed invention.” Id. at 57. Contrary to these arguments, the Petition tethers the claimed stacking of two FPGAs to several reasons to combine the references. As discussed above, Patent Owner itself cites these reasons offered by Petitioner, including “offer[ing] FPGAs to enhance parallel processing image and signal tasks of Zavracky’s microprocessor,” and similarly “perform[ing] ‘arbitrary logic functions,’ . . . as a cue to enhance and expand upon the packet processing task performed by the programmable logic device in Zavracky,” as noted above. See PO Resp. 55 (citing Pet. 19). IPR2020-01570 Patent RE42,035 E 117 As Petitioner also argues, Patent Owner does not dispute that “Zavracky already taught combining an FPGA with a memory and microprocessor.” Reply 27 (citing Ex. 1003, 12:29-39, Fig. 13). Adding another FPGA layer in place of one of the microprocessor layers in Zavracky (Ex. 1003, Figs. 12, 13) therefore would have reduced thermal problems, “because FPGAs were more energy-efficient than microprocessors for the same size die, reducing heat.” Id. at 28 (citing Ex. 1070 ¶¶ 37-41; Ex. 1058; Ex. 1082). Dr. Franzon’s testimony includes an excerpt from DeHon (Ex. 1058) and Scrofano (Ex. 1082), which support Dr. Franzon’s testimony that “FPGAs needed less power to get the same level of computing capability” as a processor. See Ex. 1070 ¶¶ 37-38 (citing Ex. 1058, 43). Similar to Alexander’s teaching that “3D FPGAs have good implications with respect to power consumption” (Ex. 1009, 263), the ’035 patent also evidences that 3-D stacks “overall reduced power requirements” (Ex. 1001, 4:63). Reduced power translates to less heat, as was well-known and as Petitioner shows. See infra note 27. Describing dual layer FPGA stacks, the ’035 patent states as follows: It should be noted that although a single FPGA die 68 has been illustrated, two or more FPGA die 68 may be included in the reconfigurable module 60. Through the use of the through- die area array contacts 70, inter-cell connections currently limited to two dimensions of a single die, may be routed up and down the stack in three dimensions. This is not known to be possible with any other currently available stacking techniques since they all require the stacking contacts to be located on the periphery of the die. In this fashion, the number of FPGA die 68 cells that may be accessed within a specified time period is increased by up to 4 VT/3, where “V” is the propagation velocity of the wafer and “T” is the specified time of propagation. IPR2020-01570 Patent RE42,035 E 118 Ex. 1001, 5:11-24 (emphasis added). Here, the ’035 patent offers no description of any specific connection scheme between the two FPGA dies. It simply describes vias throughout the periphery of each die (instead of just at the periphery thereof) as a new technique (which is not correct), without any mention of heat problems associated with stacking two FPGAs. The ’035 patent’s lack of description and focus on vias throughout the whole die as a solution (providing speed gains) further evidences a reasonable expectation of success and supports Petitioner’s showing. As Petitioner also argues, thermal issues were a routine consideration, with known viable options to address the issues. Reply 28 (citing Ex. 1020, 11; Ex. 1070 ¶¶ 29-41; Ex. 1020; Ex. 1012; Ex. 1009; Ex. 1058; Ex. 1082). Dr. Franzon credibly lists known ways to dissipate heat, including use of low thermal resistance substrates, forced fluid coolants, thermal vias, and thermally conductive adhesives. Ex. 1070 ¶ 32. The record also supports Dr. Franzon’s testimony that “Alexander itself noted that thermal concerns were standard in any multi-chip design.”27 In addition to mitigating heat concerns by eliminating I/O buffers (or “restrict[ing] I/O to one layer and plac[ing] it close to the heat sink,” Ex. 1009, 256 § 5), in the same section, Alexander further supports Dr. Franzon’s testimony, stating that “[a] number of . . . thermal-reduction techniques (i.e., thermal bumps and pillars . . ., thermal gels . . ., etc.) may also be applicable for 3D FPGAs.” Ex. 1009, 255 § 5 (“Thermal Issues”). 27 Testimony from footnote 2 of Dr. Franzon’s declaration follows: “It would have been well known to the POSITA that in a chip, an increase in power usage generally translated to an increase in heat. For example, a processor using more power to perform computations will put off more heat than when the processor is using less power.” IPR2020-01570 Patent RE42,035 E 119 Alexander also states that “[a]s the power-to-area/volume ratio increases, so does the operating temperature unless heat can be effectively dissipated.” Id. As Petitioner also persuasively reasons, Patent Owner’s arguments about heat dissipation concerns here do not undermine Petitioner’s showing of a reasonable expectation of success, because a reasonable expectation of success “does not require a certainty of success.” Reply 28 (quoting Medichem v. Rolabo S.L., 437 F.3d 1157, 1165 (Fed. Cir. 2006)). As found above, Alexander promotes using multiple FPGAs in a module stack, and myriad additional evidence further supports a reasonable expectation of success. See id. (citing Ex. 1002 ¶¶ 44-45 (listing prior art showing FPGA stacks or FPGA stacks with microprocessors and memory), ¶¶ 260-261; Ex. 1009, 1). Finally, none of the challenged claims, including claim 37, specifies the size of the claimed 3-D modules or corresponding amount of computing power. Therefore, the breadth of claim 37 encompasses a 3-D stack operable on a minimal power basis (and without any limit on the area of each die, further dissipating heat as the chip area increases), rendering heat concerns nonexistent or at least well within the bounds of a reasonable expectation of success. See supra note 27; Ex. 1009, 255-256 § 5 (discussed above, e.g., as power per unit area decreases, so does temperature). We adopt and incorporate Petitioner’s showing as to claim 37, as set forth by the Petition and summarized above, as our own. See Pet. 7-20; 63- 66. Based on the foregoing discussion and a review of the full record, including evidence and arguments addressed in sections above that tend to IPR2020-01570 Patent RE42,035 E 120 overlap to a certain extent with issues in the instant section due to the format of the Response, Petitioner shows by a preponderance of evidence that the combined teachings of Zavracky, Chiricescu, Akasaka, and Alexander would have rendered obvious claim 37. H. Exhibit 1070 Patent Owner argues that “[p]aragraphs 5-9, 13-28, 29-41, 44, 45, 59-66, 68, 73, 74, 76, 77, and 94-103 from Dr. Franzon’s [Reply D]eclaration (Ex. 1070) addressing Petitioner’s alleged obviousness grounds are not sufficiently discussed in the Reply” at pages 10, 14, 20, 21, 25, 27, and 28 of the Reply. Sur-reply 25. Patent Owner contends that the noted paragraphs are “not discussed in the Reply, but instead incorporated by citation or a cursorily parenthetical.” Id. Patent Owner further contends that “the Board should not and cannot play archeologist with the record to search for the arguments” and “should not . . . consider[] Dr. Franzon’s arguments.” Id. (citing 37 C.F.R. § 42.6(a)(3) (“Arguments must not be incorporated by reference from one document into another document.”). Patent Owner also cites General Access Solutions, Ltd. v. Sprint Spectrum L.P., 811 F. App’x 654, 658 (Fed. Cir. 2020) as “upholding the Board’s finding of improper incorporation by reference because, inter alia” (Sur-reply 25), “‘playing archaeologist with the record’ is precisely what the rule against incorporation by references was intended to prevent,” (id. (quoting Spring Spectrum, 811 F. App’x at 658, internal citation omitted)). The situation here is different than in Sprint Spectrum, because there, the court noted a problem with identifying a party’s substantive arguments prior to turning to the declaration at issue: “To identify GAS’s substantive arguments, the Board was forced to turn to a declaration by Struhsaker, and IPR2020-01570 Patent RE42,035 E 121 further to delve into a twenty-nine-page claim chart attached as an exhibit.” Id. (emphasis added). Here, Patent Owner does not describe or allege any problem with identifying Petitioner’s substantive arguments. In context, except as discussed below, the cited paragraphs of Dr. Franzon’s Reply Declaration (Ex. 1070) properly support Petitioner’s substantive arguments at the pages of the Reply identified by Patent Owner. Regarding the first citation, page 10 of the Reply cites paragraphs 94- 103 of Dr. Franzon’s Reply Declaration, and discusses how, even if the “functional to accelerate” clauses require “a wide configuration data port,” the combination of Zavracky, Chiricescu, and Akasaka teaches it. See Reply 9-10 (citing Ex. 1070 ¶¶ 94-103). This citation is a misprint or oversight by Petitioner, because Dr. Franzon’s Reply Declaration does not include paragraphs 96-102. Therefore, any issue with respect to those paragraphs is moot. The remaining cited paragraphs of Dr. Franzon’s Reply Declaration on page 10 of the Reply directly relate to what a “wide configuration data port” constitutes. Also, paragraph 95 reproduces some of the same testimony by Dr. Chakrabarty (Patent Owner’s expert in IPR2020-01021) that the Reply discusses and reproduces on page 10 of the Reply. Regarding the second citation, page 14 of the Reply cites two paragraphs with a parenthetical as follows: “Ex. 1070 ¶¶ 73-74 (citing Ex. 1083, an example of common usage of ‘share data’ as ‘transfer data’).” Prior to the citation, the Reply addresses the plain meaning of “share,” tracking the parenthetical. See Reply 14. Notwithstanding that Patent Owner generally implies that citation is one of several examples of “a IPR2020-01570 Patent RE42,035 E 122 cursorily parenthetical” (Sur-reply 25), the parenthetical is clear as to how Dr. Franzon’s cited testimony supports Petitioner’s Reply argument. Regarding the third citation, page 20 of the Reply (citing Ex. 1070 ¶¶ 13-28), Petitioner’s argument merely responds to a summary argument by Patent Owner about four different “TSV interconnection issues.” See PO Resp. 41 (“At the time of the invention, a POSITA was aware of numerous []TSV interconnection issues, such as routing congestion, TSV placement, granularity, hardware description language (‘HDL’) algorithms, which must be considered.” (citing Ex. 2011 ¶ 82; Ex. 2014, 85, 87, 89); Reply 20 (“The supposed ‘TSV interconnection issues’ that [Patent Owner] cursorily identifies were at most normal engineering issues, not problems preventing a combination. Ex. 1070 ¶¶ 13-28 (Dr. Franzon rebutting Dr. Souri’s testimony as to every purported issue with citations to evidence).” Here, Petitioner’s parenthetical generally informs the reader that Dr. Franzon’s testimony responds to Dr. Souri’s “cursor[y]” summary alleging “TSV interconnection issues.” See Reply 20; PO Resp. 41. Paragraphs 13-20 of Dr. Franzon’s Reply Declaration provide background context leading to thrust of paragraphs 21-28, which directly support Petitioner’s Reply argument that TSV issues were normal engineering issues in the context of combining the references. Therefore, we consider cited paragraphs 13-20 only as background information and context. In comparison, providing his testimony about the TSV issues, Dr. Souri’s support for TSV issues is a citation to “Ex. 2014 at 85, 97, 90.” Ex. 2011 ¶ 82. Patent Owner provides the same citation without any explanation of the citation. PO Resp. 41. This amounts to the same type of IPR2020-01570 Patent RE42,035 E 123 incorporation-by-reference of pages of evidence that Patent Owner attributes to Petitioner. Also, the cited three pages of Exhibit 2014 are in the middle of an industry article, and the pages are densely packed two-column pages that facially appear to have at least the same number of words in some of the complained-about citations to multiple paragraphs that Petitioner provides to Dr. Souri’s Reply Declaration. Here, Patent Owner leaves it to the Board to dig into the cited pages of Exhibit 2014 to find the alleged TSV interconnection issues and place it in context to the background information in the whole article. In reaching our decision, we exercised judgment as to all the evidence cited by the parties for its relevance, context, and substance, and weighed it accordingly. Finally, an examination of the other citations identified by Patent Owner in full context, reveals (like the citations addressed above) that Petitioner’s use of and citation to Dr. Souri’s testimony is not improper. In summary, the remaining pages of the Reply identified by Patent Owner include citations with a clear sentence preceding the citation and/or clear parenthetical informing the reader clearly how the cited testimony supports the sentence. See Reply 21 n.7 (clear parenthetical and preceding sentence (citing Ex. 1070 ¶¶ 59-66)), 25 (clear preceding sentence (citing Ex. 1070 ¶¶ 76-77), 27 (no citation), 28 (clear parentheticals and preceding sentences about thermal issues (citing Ex. 1070 ¶¶ 37-41; Ex. 1070 ¶¶ 29-41)).28 28 As noted above, Patent Owner cites to page 27 of the Reply, but page 27 does not have a citation to Exhibit 1070. It appears that Patent Owner intended to refer to the two citations to Exhibit 1070 on page 28 of the Reply. See PO Resp. 25; Reply 28. IPR2020-01570 Patent RE42,035 E 124 III. CONCLUSION The outcome for the challenged claims of this Final Written Decision follows.29 In summary: Claims 35 U.S.C. § References/ Basis Claims Shown Unpatent- able Claims Not shown Unpatent -able 1-30, 33, 36, 38 103(a) Zavracky, Chiricescu, Akasaka 1-30, 33, 36, 38 31, 32, 34 103(a) Zavracky, Chiricescu, Akasaka, Trimberger 31, 32, 34 29 Should Patent Owner wish to pursue amendment of the challenged claims in a reissue or reexamination proceeding subsequent to the issuance of this decision, we draw Patent Owner’s attention to the April 2019 Notice Regarding Options for Amendments by Patent Owner Through Reissue or Reexamination During a Pending AIA Trial Proceeding. See 84 Fed. Reg. 16,654 (Apr. 22, 2019). If Patent Owner chooses to file a reissue application or a request for reexamination of the challenged patent, we remind Patent Owner of its continuing obligation to notify the Board of any such related matters in updated mandatory notices. See 37 C.F.R. § 42.8(a)(3), (b)(2). IPR2020-01570 Patent RE42,035 E 125 Claims 35 U.S.C. § References/ Basis Claims Shown Unpatent- able Claims Not shown Unpatent -able 35 103(a) Zavracky, Chiricescu, Akasaka, Satoh 35 37 103(a) Zavracky, Chiricescu, Akasaka, Alexander 37 Overall Outcome 1-38 IV. ORDER In consideration of the foregoing, it is hereby ORDERED that claims 1-38 the ’035 patent are unpatentable; and FURTHER ORDERED that because this is a Final Written Decision, parties to the proceeding seeking judicial review of the Decision must comply with the notice and service requirements of 37 C.F.R. § 90.2 IPR2020-01570 Patent RE42,035 E 126 PETITIONER: David M. Hoffman Kenneth W. Darby Jr. Jeffrey Shneidman FISH & RICHARDSON P.C. PTABInbound@fr.com IPR42653-0031IP1@fr.com hoffman@fr.com kdarby@fr.com shneidman@fr.com PATENT OWNER: Jonathan S. Caplan James Hannah Jeffrey H. Price KRAMER LEVIN NAFTALIS & FRANKEL LLP jcaplan@kramerlevin.com jhannah@kramerlevin.com jprice@kramerlevin.com