Apple Inc.v.Memory Integrity, LLC, a Delaware limited liability company

Patent Trial and Appeal Board

May 8, 2015

10966161 (P.T.A.B. May. 8, 2015)

Trials@uspto.gov Paper No. 18
571.272.7822 Entered: May 8, 2015

UNITED STATES PATENT AND TRADEMARK OFFICE
____________

BEFORE THE PATENT TRIAL AND APPEAL BOARD
____________

APPLE INC., HTC CORPORATION, HTC AMERICA, INC.,
SAMSUNG ELECTRONICS CO. LTD,
SAMSUNG ELECTRONICS AMERICA, INC., and
AMAZON.COM, INC.,
Petitioner,

v.

MEMORY INTEGRITY, LLC,
Patent Owner.
____________

Case IPR2015-00161
Patent 7,296,121 B2
____________

Before JENNIFER S. BISK, NEIL T. POWELL, and KERRY BEGLEY,
Administrative Patent Judges.

BEGLEY, Administrative Patent Judge.

DECISION
Denying Institution of Inter Partes Review
37 C.F.R. § 42.108

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Apple Inc., HTC Corporation, HTC America, Inc., Samsung
Electronics Co. Ltd., Samsung Electronics America, Inc.,
1
and Amazon.com,
Inc. (collectively, “Petitioner”) filed a Petition requesting inter partes review
of claims 1–3, 8, 9, 11, and 14–25 of U.S. Patent No. 7,296,121 B2 (Ex.
1001, “the ’121 patent”). Memory Integrity, LLC (“Patent Owner”) filed a
Preliminary Response to the Petition. Paper 13 (“Prelim. Resp.”).
Pursuant to 35 U.S.C. § 314(a), an inter partes review may not be
instituted unless “the information presented in the petition . . . and any
response . . . shows that there is a reasonable likelihood that the petitioner
would prevail with respect to at least 1 of the claims challenged in the
petition.” Having considered the Petition and the Preliminary Response, we
determine that there is not a reasonable likelihood that Petitioner would
prevail in establishing that the challenged claims of the ’121 patent are
unpatentable. Therefore, we deny institution of inter partes review.
I. BACKGROUND
A. THE ’121 PATENT
The ’121 patent relates to techniques to reduce memory transaction
traffic and to improve data access and cache coherency in systems with
multiple processors connected using point-to-point links. Ex. 1001, 1:22–
25, 2:39–47. The ’121 patent explains that cache coherency problems can
arise in a system with multiple processors, each with an individual cache
memory, because the system may contain multiple copies of the same data.
Id. at 1:26–38. For example, if the caches of two different processors have a

1
The Petition also lists Samsung Telecommunications America, LLC
(“STA”) as a petitioner. Paper 6 (“Pet.”), 1. After the filing of the Petition,
however, STA merged with and into Samsung Electronics America, Inc.
Paper 12. Thus, STA no longer exists as a separate corporate entity. Id.
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copy of the same data block and both processors “attempt to write new
values into the data block at the same time,” then the two caches may have
different data values and the system may be “unable to determine what value
to write through to system memory.” Id. at 1:37–45.
The ’121 patent discloses a computer system with processing nodes,
each with a cache memory, connected by a point-to-point architecture. Id. at
[57], 2:48–62. The system also includes a “probe filtering unit” that can
receive a probe, “[a] mechanism for eliciting a response from a node to
maintain cache coherency in a system,” from a processing node. Id. at [57],
2:52–65, 5:45–47. The probe filtering unit then can evaluate the probe
based on probe filtering information, specifically “[a]ny criterion that can be
used to reduce the number of clusters or nodes probed,” and can transmit the
probe to selected processing nodes. Id. at [57], 2:52–3:5, 14:50–52; see id.
at 28:29–58, 29:43–46. The probe filtering unit also may be operable to
accumulate responses from the selected processing nodes and to respond to
the node from which the probe originated. Id. at 3:5–8, 28:59–67, 29:46–51.
Figure 18 of the patent is reproduced below.

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Figure 18 is a diagrammatic representation of a multiple processor
system with a probe filtering unit. Id. at 3:61–63, 26:58–27:20, Fig. 18.
Specifically, Figure 18 depicts multiple processor system 1800 with
processing nodes 1802a–d interconnected by point-to-point communication
links 1808a–e. Id. at 26:58–27:1. System 1800 also includes probe filtering
unit 1830 as well as I/O switch 1810, one or more Basic I/O systems
(“BIOS”) 1804, I/O adapters 1816, 1820, and a memory subsystem with
memory banks 1806a–d. Id. at 3:61–63, 26:58–27:20, Fig. 18.
Claims 1, 16, and 25 of the ’121 patent are independent claims.
Claim 1 is illustrative of the claimed subject matter:
1. A computer system comprising a plurality of processing
nodes interconnected by a first point-to-point architecture,
each processing node having a cache memory associated
therewith,
the computer system further comprising a probe filtering unit
which is operable to receive probes corresponding to memory
lines from the processing nodes and to transmit the probes only
to selected ones of the processing nodes with reference to probe
filtering information representative of states associated with
selected ones of the cache memories.
Id. at 30:65–31:7 (line breaks added).
B. ASSERTED PRIOR ART
The Petition relies upon the following prior art references, as well as
the supporting Declaration of Robert Horst, Ph.D. (Ex. 1014):
David Chaiken et al., Directory-Based Cache Coherence in Large-
Scale Multiprocessors, COMPUTER, June 1990, at 49 (Ex. 1004, “Chaiken”);
JOSÉ DUATO ET AL., INTERCONNECTION NETWORKS (1997) (Corrected
Ex. 1007, “Duato”); and
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MICHAEL JOHN SEBASTIAN SMITH, APPLICATION-SPECIFIC INTEGRATED
CIRCUITS (1997) (Ex. 1008, “Smith”).
C. ASSERTED GROUNDS OF UNPATENTABILITY
Petitioner challenges claims 1–3, 8, 9, 11, and 14–25 of the
’121 patent on the following grounds. Pet. 3.
Challenged Claim[s] Basis Reference[s]
1–3, 8, 11, 14–16, 19,
20, 22, and 25
§ 102 Chaiken
9 § 103 Chaiken and Duato
17–24 § 103 Chaiken and Smith

II. ANALYSIS
A. CLAIM INTERPRETATION
We begin our analysis by addressing the meaning of the claims. The
Board interprets claims using the “broadest reasonable construction in light
of the specification of the patent in which [they] appear[].” 37 C.F.R.
§ 42.100(b); see In re Cuozzo Speed Techs., LLC, 778 F.3d 1271, 1279–82
(Fed. Cir. 2015). We presume a claim term carries its “ordinary and
customary meaning,” which is “the meaning that the term would have to a
person of ordinary skill in the art in question” at the time of the invention.
In re Translogic Tech., Inc., 504 F.3d 1249, 1257 (Fed. Cir. 2007) (citation
and quotations omitted). This presumption, however, is rebutted when the
patentee acts as his own lexicographer by giving the term a particular
meaning in the specification with “reasonable clarity, deliberateness, and
precision.” In re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
Petitioner and Patent Owner each proffer proposed constructions of
several claim terms. On this record and for purposes of this decision, we
determine that only the claim terms addressed below require construction.
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1. “probe” (claims 1–3, 8, 11, 14–16, 19, 20, 22, and 25)
Petitioner points out that the ’121 patent defines the term “probe,”
which is recited in challenged claims 1–3, 8, 11, 14–16, 19, 20, 22, and 25,
and argues that the term should be construed as “a mechanism that elicits a
response from a node to maintain cache coherency in a system.” Pet. 7–8.
Patent Owner does not address Petitioner’s assertions.
We note that Petitioner’s proposed construction slightly differs from
the definition of “probe” in the ’121 patent, which uses the language “a
mechanism for eliciting a response,” as opposed to “a mechanism that elicits
a response” in Petitioner’s proposed construction. Id. (emphases added); see
Ex. 1001, 5:45–47. Petitioner has provided no reason for the difference in
wording. Therefore, for purposes of this decision, we adopt as the broadest
reasonable construction of “probe” the express definition of the term in the
’121 patent: “[a] mechanism for eliciting a response from a node to
maintain cache coherency in a system.” Ex. 1001, 5:45–47.
2. “transmit the probes” (claims 1 and 16) and “transmitting the probe”
(claim 25)
Neither party proposes a construction of the terms “transmit the
probes” in independent claim 1 and 16 and “transmitting the probe” in
independent claim 25, beyond the definition of “probe” provided in the
specification of the ’121 patent. See Pet. 7–8; Prelim. Resp. 10–24. Yet
each party relies on an interpretation of these terms in addressing the
asserted grounds in this case. See id. at 27–29; Prelim. Resp. 26. To
determine whether institution is warranted in this case, we address two
aspects of the scope of the terms.
First, we determine that, as a result of an antecedent relationship, the
probe or probes in “transmit the probes” (claims 1 and 16) and “transmitting
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the probe” (claim 25) refers to the probe or probes that the probe filtering
unit receives from processing nodes. Specifically, claims 1 and 16 of the
’121 patent recite a “probe filtering unit” that is “operable to receive probes
corresponding to memory lines from the processing nodes and to transmit
the probes only to selected ones of the processing nodes.” Ex. 1001, 31:1–5,
32:11–14 (emphases added). Because “the probes” uses the definite article
“the,” the term requires antecedent basis. See NTP, Inc. v. Research in
Motion, Ltd., 418 F.3d 1282, 1306 (Fed. Circ. 2005), abrogated on other
grounds by, Zontek Corp. v. United States, 672 F.3d 1309, 1323 (Fed. Cir.
2012). We agree with both parties that in each claim, the antecedent for “the
probes” transmitted by the probe filtering unit is the “probes” received by
the probe filtering unit from the processing nodes. See Prelim. Resp. 26 (“In
all independent claims, probes received by the probe filtering unit provide
the antecedent basis for ‘the probes’ transmitted by the probe filtering
unit.”); cf. Pet. 13–14 (explaining that “[t]he only antecedent” for “the
probes” in claim 8, which depends from claim 1, is “recited in independent
claim 1 . . . . Thus, the term ‘the probes’ refers to probes received by the
probe filtering unit from the processing nodes.”).
Similarly, independent claim 25 recites a method comprising
“transmitting a probe from a first one of the processing nodes only to a
probe filtering unit” and “transmitting the probe from the probe filtering unit
only to the selected ones of the processing nodes.” Ex. 1001, 32:45–57
(emphases added). Like claims 1 and 16, the probe transmitted to the probe
filtering unit from a processing node provides the antecedent for “the probe”
that the probe filtering unit transmits to selected processing nodes.
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Second, we agree with Petitioner that, to fall within the scope of
independent claims 1, 16, and 25, the probes that the probe filtering unit
transmits need not be identical to those it receives. Pet. 14 n.3, 29. Rather,
the transmitted probes can be modified versions of the received probes. This
conclusion is supported by claim 14, which depends from claim 1 and
recites: “The computer system of claim 1 wherein the probe filtering unit is
further operable to modify the probes such that the selected processing nodes
transmit responses to the probe filtering unit.” Ex. 1001, 31:63–32:2
(emphasis added). The written description confirms that the probes
transmitted by the probe filtering unit may contain “modifi[cations]” from
those received by the unit. Id. at 28:50–58; see id. at 10:62–11:3. For
example, the specification explains that the probe filtering unit, after
accepting a probe from a memory controller, sends the probe to selected
nodes. Id. at 28:25–58. “The outgoing probe is the same as the incoming
probe, except that it is modified to identify the [probe filtering unit] as the
target, i.e., the source of the probe, and the command is changed . . . .” Id. at
28:53–56 (emphasis added).
In sum, for purposes of this decision, we conclude that, to fall within
the scope of “transmit the probes” (claims 1 and 16) and “transmitting the
probe” (claim 25), the transmitted probe or probes must be the probe or
probes—or modified versions thereof—received from processing nodes.
3. “probe filtering information” (claims 1, 3, 16, and 25)
Petitioner argues that the ’121 patent expressly defines “probe
filtering information,” as recited in challenged claims 1, 3, 16, and 25.
Pet. 8–9. Patent Owner does not respond to this argument. We agree that
the ’121 patent defines the term “probe filter information.” Ex. 1001,
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14:50–52. On the record before us, we adopt this definition as the broadest
reasonable construction of the claim term “probe filtering information”:
“[a]ny criterion that can be used to reduce the number of clusters or nodes
probed.” Id.
4. “cache coherence controller” (claim 3)
Petitioner also correctly contends that the ’121 patent defines “cache
coherence controller,” as recited in claim 3. Pet. 11–12. Patent Owner does
not address this assertion. For purposes of this decision, we adopt this
express definition as the broadest reasonable construction of “cache
coherence controller”: “[a]ny mechanism or apparatus that can be used to
provide communication between multiple processor clusters while
maintaining cache coherence.” Ex. 1001, 7:2–5.
B. ASSERTED ANTICIPATION GROUND
We turn to the asserted grounds. Petitioner argues that Chaiken
anticipates claims 1–3, 8, 11, 14–16, 19, 20, 22, and 25 of the ’121 patent.
Pet. 20–48.
1. Chaiken
Chaiken discloses directory-based cache coherence protocols for
multiprocessor systems. Ex. 1004, 49–50. In particular, Chaiken discloses a
cache coherence protocol that uses a full-map directory. Id. at 50. The full-
map directory has a directory entry for each block of data. Id. Each
directory entry features: (1) a dirty bit and (2) one bit for each processor in
the multiprocessor system. Id. The bit for each processor “represents the
status of the block in the corresponding processor’s cache (present or
absent).” Id. The dirty bit indicates if a “unique cache has permission to
write the associated block of data.” Id. Therefore, the dirty bit is set only
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when one processor has permission to write into the block of data and only
that processor has its bit set in the directory entry. Id. Figure 1a of Chaiken
is reproduced below.

Figure 1a includes three images illustrating three different states of a full-
map directory entry for a block of data at location X in a multiprocessor
system, which includes processors P1, P2, and P3 with individual caches
(referred to in text as C1, C2, and C3, respectively). See id., Fig. 1a. In the
first state, depicted in the upper left corner of Figure 1a, the block of data at
“location X is missing in all of the caches in the system.” Id. The second
state, shown in the upper right corner of Figure 1a, illustrates the full-map
directory after three caches (C1, C2, and C3) request copies of the block of
data at location X. Id. Three pointers, or “processor bits,” are set in the
directory entry for location X to indicate that these three caches have copies
of the block of data at location X. Id. In both the first and second state, the
dirty bit, shown at the left side of the directory entry, is set to clean (C),
indicating that no processor has permission to write to the block of data at
location X. Id.
The third state, shown at the bottom center of Figure 1a, illustrates the
full-map directory entry after cache C3 requests write permission for the
block of data at location X. Id. In the third state, the dirty bit is set to dirty
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(shaded in Figure 1a) and the directory entry for location X contains only
one pointer to the block of data in cache C3. Id.
The transition from the second state to the third state of Figure 1a,
after “processor P3 issues the write to cache C3,” occurs as follows:
(1) Cache C3 detects that the block containing location X is
valid but that the processor does not have permission to write to
the block, indicated by the block’s write permission bit in the
cache.
(2) Cache C3 issues a write request to the memory module
containing location X and stalls processor P3.
(3) The memory module issues invalidate requests to
caches C1 and C2.
(4) Cache C1 and cache C2 receive the invalidate requests,
set the appropriate bit to indicate that the block containing
location X is invalid, and send acknowledgements back to the
memory module.
(5) The memory module receives the acknowledgements, sets
the dirty bit, clears the pointers to caches C1 and C2, and sends
write permission to cache C3.
(6) Cache C3 receives the write permission message, updates
the state in the cache, and reactivates processor P3.
Id. (emphases added).
2. Discussion
a. Independent Claims 1, 16, and 25
We are not persuaded that Petitioner has proffered sufficient evidence
that Chaiken discloses the probe or probes recited in independent claims 1,
16, and 25. Specifically, we determine that Petitioner has not shown
adequately that Chaiken discloses a “probe filtering unit . . . operable to
receive probes . . . and to transmit the probes”—as recited in independent
claims 1 and 16—or a method comprising “transmitting a probe . . . to a
probe filtering unit” and “transmitting the probe from the probe filtering
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unit”—as recited in independent claim 25. Ex. 1001, 31:1–5, 32:11–14,
32:45–57 (emphases added).
Petitioner asserts that the “write request” and “invalidate requests”
disclosed in Chaiken, or some combination thereof, corresponds to the probe
or probes recited in independent claims 1, 16, and 25. See Pet. 27–30, 38–
39, 42–47. We agree with Patent Owner that the Petition is not clear
regarding what Petitioner asserts corresponds to the recited probe or probes.
Prelim. Resp. 27–29. Yet each of the possibilities suggested in the Petition
is deficient, for the reasons explained below.
First, Petitioner’s argument that Chaiken’s “write request” discloses
the recited probe or probes, which the probe filtering unit receives and
transmits, lacks merit. See Pet. 28–29 (“Processor P3’s write request elicits
responses . . . to maintain cache coherency in the multiprocessor system,
and, thus, is a probe.”); id. at 44 (“Chaiken describes that a processor P3
with associated cache C3 requests permission to write . . . . This request is a
probe . . . .”); Ex. 1014 ¶ B-11 (“This write request issued by cache C3 to the
memory module is a ‘probe’ . . . .”). Chaiken’s memory module—which
Petitioner argues corresponds to the recited “probe filtering unit”—receives
“a write request” from cache C3 but then “issues invalidate requests” to
caches C1 and C2. Ex. 1004, 50. In other words, in Chaiken, the memory
module transmits invalidate requests, not write requests. Therefore, Chaiken
does not disclose that its memory module is “operable . . . to transmit”
(claims 1 and 16) or “transmit[s]” a write request (claim 25). Accordingly,
Chaiken’s write request does not correspond to the probe or probes recited in
claims 1, 16, and 25.
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Second, Petitioner’s argument that Chaiken’s “invalidate requests”
disclose the recited probe or probes fails for similar reasons. Pet. 46 (“These
invalidate requests are also probes . . . .”); Ex. 1014 ¶ B-12 (same).
Specifically, because Chaiken’s memory module receives “a write
request”—rather than “invalidate requests”—from cache C3, Ex. 1004, 50,
Chaiken does not disclose that its memory module is “operable to receive”
invalidate requests (claims 1 and 16). Nor does it disclose that an invalidate
request is “transmitt[ed]” to its memory module (claim 25). Therefore,
Chaiken’s invalidate requests do not correspond to the probe or probes
recited in claims 1, 16, and 25.
Third, Petitioner’s arguments that a combination of the “write
request” and “invalidate requests” disclosed in Chaiken corresponds to the
recited probe or probes are deficient. The Petition proffers three different
arguments that fall under this category: (1) Chaiken’s invalidate requests are
a “form of” the write request (Pet. 27); (2) Chaiken’s invalidate requests are
“simply modifications” of the write request (Id. at 28–30; see id. at 46–47);
and (3) Chaiken’s invalidate requests and its write request are the same,
specifically, “in the context of a multiprocessor system that maintains cache
coherency using a write invalidation cache coherency protocol, like that
described in Chaiken, a write request is more accurately understood to be a
‘write and invalidate’ request” (Id. at 28 n.4, 46 n.7). For each of these
positions, the Petition cites only the declaration testimony of Dr. Horst. See
id. at 27–30, 38–39, 45–47.
In the cited declaration testimony, Dr. Horst merely restates these
statements and conclusions from the Petition, without any supporting
citations or discussion of the knowledge and understanding of a person of
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ordinary skill in the art. Ex. 1014 ¶¶ B-12, B-15. We do not credit this
conclusory and unsupported testimony regarding a key factual issue:
whether the “write request” and “invalidate requests” disclosed in Chaiken
are the same, or modified versions of one another, such that Chaiken
discloses the probes received by and transmitted from the probe filtering unit
as recited in the independent claims of the ’121 patent. 37 C.F.R. § 42.65(a)
(“Expert testimony that does not disclose the underlying facts or data on
which the opinion is based is entitled to little or no weight.”); see Rohm &
Haas Co. v. Brotech Corp., 127 F.3d 1089, 1092 (Fed. Cir. 1997) (“Nothing
in the [federal] rules [of evidence] or in our jurisprudence requires the fact
finder to credit the unsupported assertions of an expert witness.”); Ashland
Oil, Inc. v. Delta Resins & Refractories, Inc., 776 F.2d 281, 294 (Fed. Cir.
1985) (“Lack of factual support for expert opinion going to factual
determinations . . . may render the testimony of little probative value in a
validity determination.”); see also In re Am. Acad. of Sci. Tech Ctr., 367
F.3d 1359, 1368 (Fed. Cir. 2004) (explaining that “the Board has broad
discretion” to weigh declarations offered in the course of prosecution and “to
conclude that the lack of factual corroboration warrants discounting the
opinions expressed in the declarations”).
We are not persuaded that Chaiken itself supports Petitioner’s position
that the disclosed write request and invalidate requests are the same or
modified versions of one another. Rather, Chaiken uses different terms for
the requests and explains that they are “issue[d]” by distinct parts of the
multiprocessor system: “Cache C3 issues a write request to the memory
module,” whereas “[t]he memory module issues invalidate requests to
caches C1 and C2.” Ex. 1004, 50. Further, as Patent Owner points out,
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“there is no teaching in Chaiken that requests are modified. Nor is there any
disclosure in Chaiken of the structure of write request[s] . . . as compared to
the structure of . . . invalidat[e requests] . . . from which one could conclude
that one is a modified version of the other.” Prelim. Resp. 28. Nor does
Chaiken use the terminology “write and invalidate.” Id.
The Petition does not cite any other evidence, such as the specification
of the ’121 patent or another prior art reference, to show that one of ordinary
skill in the art would understand Chaiken’s write request and invalidate
requests to be the same or modified versions of one another.
Accordingly, we determine that Petitioner has not proffered sufficient
evidence that Chaiken discloses a “probe filtering unit . . . operable to
receive probes . . . and to transmit the probes”—as recited in independent
claims 1 and 16—and a method comprising “transmitting a probe . . . to a
probe filtering unit” and “transmitting the probe from the probe filtering
unit”—as recited in independent claim 25. Ex. 1001, 31:1–5, 32:11–14,
32:45–57.
b. Dependent Claims 2, 3, 8, 11, 14, 15, 19, 20, and 22
For the same reasons, we also are not persuaded that Chaiken
anticipates claims 2, 3, 8, 11, 14, 15, 19, 20, and 22, given their dependency
from either independent claim 1 or 16. In addition, for the reasons explained
above regarding the deficiencies in Petitioner’s argument that Chaiken’s
invalidate requests are modified versions of its write request, there is
insufficient evidence on the record before us that Chaiken discloses the
additional limitation of dependent claim 14: “the probe filtering unit is
further operable to modify the probes such that the selected processing nodes
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transmit responses to the probes to the probe filtering unit.” Id. at 31:63–
32:2; see Pet. 35–36.
c. Conclusion
For the reasons stated above, we determine the Petition does not show
a reasonable likelihood that Petitioner would prevail in showing that
Chaiken anticipates claims 1–3, 8, 11, 14–16, 19, 20, 22, and 25.
C. ASSERTED OBVIOUSNESS GROUNDS
In addition to the asserted ground of anticipation by Chaiken, the
Petition asserts two obviousness grounds that rely on Chaiken. Specifically,
the Petition challenges claim 9—which depends from independent claim 1—
as obvious over Chaiken and Duato, and claims 17–24—which depend from
independent claim 16—as obvious over Chaiken and Smith. Pet. 48–54.
Each of these asserted obviousness grounds relies on the asserted
anticipation ground for the independent claims, and discusses the additional
reference (Duato or Smith) only to address the additional limitations of the
relevant dependent claims. See id. Therefore, the asserted grounds rely
exclusively on Chaiken—not Duato or Smith—as teaching or suggesting the
limitations of independent claims 1 and 16. See id. For the reasons
explained above in our analysis of the asserted ground of anticipation by
Chaiken, Petitioner has not proffered sufficient evidence that Chaiken
teaches or suggests “a probe filtering unit . . . operable to receive probes . . .
and to transmit the probes,” as recited in claims 1 and 16.
Accordingly, we determine that the Petition does not establish a
reasonable likelihood that Petitioner would prevail in showing that claim 9
would have been obvious over Chaiken and Duato and that claims 17–24
would have been obvious over Chaiken and Smith.
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III. ORDER
For the reasons given, it is:
ORDERED that pursuant to 35 U.S.C. § 314(a), the Petition is denied.

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PETITIONER:
W. Karl Renner
Roberto Devoto
FISH & RICHARDSON P.C.
axf@fr.com
IPR39521-0007IP2@fr.com

PATENT OWNER:
Jonathan D. Baker
Bryan Atkinson
FARNEY DANIELS PC
jbaker@farneydaniels.com
batkinson@farneydaniels.com
MemoryIntegrityIPR@farneydaniels.com