Analog Devices, Inc.

Patent Trials and Appeals Board

Jul 23, 2021

2020000403 (P.T.A.B. Jul. 23, 2021)

UNITED STATES PATENT AND TRADEMARK OFFICE
UNITED STATES DEPARTMENT OF COMMERCE
United States Patent and Trademark Office
Address: COMMISSIONER FOR PATENTS
P.O. Box 1450
Alexandria, Virginia 22313-1450
www.uspto.gov
APPLICATION NO. FILING DATE FIRST NAMED INVENTOR ATTORNEY DOCKET NO. CONFIRMATION NO.
14/735,104 06/09/2015 Bikiran Goswami G0766.70088US03 7105
140980 7590 07/23/2021
Analog Devices Inc.
c/o Wolf Greenfield & Sacks, P.C.
600 ATLANTIC AVENUE
BOSTON, MA 02210-2206
EXAMINER
MURPHY, RHONDA L
ART UNIT PAPER NUMBER
2462
NOTIFICATION DATE DELIVERY MODE
07/23/2021 ELECTRONIC
Please find below and/or attached an Office communication concerning this application or proceeding.
The time period for reply, if any, is set in the attached communication.
Notice of the Office communication was sent electronically on above-indicated "Notification Date" to the
following e-mail address(es):
G0766_eOfficeAction@WolfGreenfield.com
Patents_eOfficeAction@WolfGreenfield.com
PTOL-90A (Rev. 04/07)
UNITED STATES PATENT AND TRADEMARK OFFICE
BEFORE THE PATENT TRIAL AND APPEAL BOARD
Ex parte BIKIRAN GOSWAMI and BAOXING CHEN
Appeal 2020-000403
Application 14/735,104
Technology Center 2400
Before JOHN A. JEFFERY, JUSTIN BUSCH, and
JENNIFER L. MCKEOWN, Administrative Patent Judges.
BUSCH, Administrative Patent Judge.
DECISION ON APPEAL
STATEMENT OF THE CASE
Pursuant to 35 U.S.C. § 134(a), Appellant1 appeals from the
Examiner’s decision to reject claims 1, 2, 7, 10, 13–18, 22–24, and 27–37.
We have jurisdiction under 35 U.S.C. § 6(b).
We AFFIRM IN PART.
CLAIMED SUBJECT MATTER
Appellant’s invention generally relates to circuits and systems
providing efficient communication across an isolation barrier. Spec. ¶ 4.

1 We use the term Appellant to refer to “applicant” as defined in 37 C.F.R.
§ 1.42(a). Appellant identifies the real party in interest as Analog Devices,
Inc. Appeal Br. 3.
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More specifically, the claimed subject matter relates to circuits and methods
on one side of an isolation barrier both for receiving, framing, and encoding
input from multiple channels to generate and drive a data symbol onto an
isolator that bridges the isolation barrier and for decoding and deframing a
data symbol received via the isolator to generate a plurality of output data
channels. Spec. ¶¶ 49–52, Fig. 4. Claim 1, reproduced below, is illustrative
of the claimed subject matter:
1. A communication circuit for communicating data across an
isolation barrier, comprising:
an input circuit configured to receive a plurality of input
data channels;
a framing circuit coupled to the input circuit and
configured to frame an input data packet from the plurality of
input data channels, the input data packet comprising a plurality
of bits;
an encoding circuit configured to encode the plurality of
bits of the framed input data packet as a first data symbol;
a driver circuit configured to drive the first data symbol
onto an isolator bridging the isolation barrier;
a receive circuit configured to receive a second data
symbol from the isolator;
a decoding circuit configured to decode a plurality of bits
of an output data packet based on the second data symbol; and
a deframing circuit configured to deframe the output data
packet into output data of a plurality of output data channels,
wherein the receive circuit and the deframing circuit are on a
same side of the isolation barrier as the driver circuit.
REFERENCES
Name Reference Date
Reingand US 2003/0058499 A1 Mar. 27, 2003
Sasaki US 2005/0077905 A1 Apr. 14, 2005
Dupuis US 7,515,672 B2 Apr. 7, 2009
Sundar US 2014/0307759 A1 Oct. 16, 2014

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REJECTIONS
Claims 1, 13–17, 22, 23, and 27–37 stand rejected under 35 U.S.C.
§ 103 as obvious over Sundar and Dupuis. Final Act. 3–7.
Claims 2, 18, and 24 stand rejected under 35 U.S.C. § 103 as obvious
over Sundar, Dupuis, and Reingand. Final Act. 7–8.
Claims 7 and 10 stand rejected under 35 U.S.C. § 103 as obvious over
Sundar, Dupuis, Reingand, and Sasaki. Final Act. 8–9.
ANALYSIS
Appellant presents various arguments asserting the patentability of the
pending claims. We address each of these arguments below, generally in the
order the arguments are presented in the Appeal Brief. For clarity and
conciseness, we group some arguments Appellant presents under separate
headings due to the similarity of the arguments and analysis.
APPELLANT’S ARGUMENT THAT THE LIMITATIONS RECITED IN CLAIMS 17 AND
23 WERE NOT ADDRESSED IN THE OFFICE ACTION
Appellant argues the Examiner rejected independent claims 1, 17, and
23 based on only the limitations recited in claim 1 and, therefore, the
Examiner made no findings regarding limitations in claims 17 and 23 that
are different than the limitations recited in claim 1. Appeal Br. 9; Reply
Br. 3. Specifically, Appellant asserts “[t]he rejection does not explicitly
address the limitations of method claim 17,” and “[t]he rejection fails to
make any mention at all of the required ‘means for encoding the plurality of
bits of the framed input data packet as a first data symbol’ of claim 23.”
Appeal Br. 9; see Reply Br. 3.
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Claim 17
We initially note that the only difference between the preambles in
claims 1 and 17 is that claim 1 recites a “communication circuit for
communicating data across an isolation barrier” whereas claim 17 recites a
“method for communicating data across an isolation barrier.” See Appeal
Br. 18–19 (emphases added). The only other differences between claims 1
and 17 are that each step in method claim 17 recites an affirmative action
performed by an element of a communication circuit, whereas claim 1
recites the circuit elements being configured to perform those same actions.
Because the Examiner finds the prior art teaches every circuit element
configured to perform the same actions that make up the limitations recited
in independent method claim 17, we are not persuaded the Examiner erred in
grouping the claims 1 and 17 for the purpose of identifying where the prior
art teaches each limitation in the two claims.
Claim 23
Independent claims 1 and 23 are identical except that claim 1 recites
“an encoding circuit configured to encode the plurality of bits” whereas
claim 23 recites a “means for encoding the plurality of bits.” Thus, other
than the encoding means, every recited circuit element and the respective
function the element is configured to perform are properly grouped with the
same element and corresponding function recited in claim 1. However,
Appellant is correct that the Examiner’s rejection did not address the “means
for encoding,” recited in claim 23.
In order for a prior art element to satisfy a limitation that invokes
35 U.S.C. § 112(f), which is then construed as a means-plus-function
limitation, the prior art element must teach or suggest the disclosed structure
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or its equivalent. In re Donaldson Co., 16 F.3d 1189, 1195 (Fed. Cir. 1994)
(en banc). Two structures may be “equivalent” for purposes of section
112(f) if they perform the identical function, in substantially the same way,
with substantially the same result. Kemco Sales, Inc. v. Control Papers Co.,
208 F.3d 1352, 1364 (Fed. Cir. 2000). However, a claim may use this
claiming format only if the specification “discloses specific structure(s)
corresponding to that means.” Kemco, 208 F.3d at 1360. The statute
specifically states that an element claimed as a means plus function without
reciting “structure, material, or acts in support thereof . . . shall be construed
to cover the corresponding structure, material, or acts described in the
specification and equivalents thereof.” 35 U.S.C. § 112(f) (emphasis added).
The disclosure of structure under 35 U.S.C. § 112(f) serves the “purpose of
limiting the scope of the claim to the particular structure disclosed, together
with equivalents.” EON Corp. IP Holdings LLC v. AT & T Mobility LLC,
785 F.3d 616, 623 (Fed. Cir. 2015) (quoting Aristocrat Techs. Austl. Pty Ltd.
v. Int'l Game Tech., 521 F.3d 1328, 1336 (Fed. Cir. 2008)).
The Examiner initially did not construe the “means for encoding the
plurality of bits of the framed input data packet as a first data symbol.” See
Final Act. 3–5. In the Answer, however, the Examiner finds the “means for
encoding” “is represented by the ‘encoding circuit’ described in claim 1,”
and “[t]he structural language in claim 1 is supported by the [S]pecification
in paragraph 50 and illustrated in Figure 4.” Ans. 3. In the Summary of
Claimed Subject Matter in the Appeal Brief Appellant also identifies
paragraph 50 and element 130 in Figure 4, plus paragraph 30 as the
disclosures allegedly supporting the “means for encoding.” Appeal Br. 6.
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“Construing a means-plus-function claim term is a two-step process”
by first identifying the claimed function, then determining “what structure, if
any, disclosed in the specification corresponds to the claimed function.”
Williamson v. Citrix Online, LLC, 792 F.3d. 1339, 1351 (Fed. Cir. 2015) (en
banc) (citing Noah Sys., Inc. v. Intuit Inc., 675 F.3d 1302, 1311 (Fed.
Cir. 2012); see also MANUAL OF PATENT EXAMINING PROCEDURE (MPEP)
¶ 2181 (9th ed. rev. 10.2019 June 2020) (explaining that the broadest
reasonable interpretation of a claim term that invokes 35 U.S.C § 112(f) “is
the structure, material or act described in the specification as performing the
entire claimed function and equivalents to the disclosed structure, material or
act”). Here, the claimed function is “encoding the plurality of bits of the
framed input data packet as a first data symbol.” Next, we identify structure
in the Specification corresponding to this claimed function. The
Specification discloses that the transmit circuit may include “an encode logic
circuit 130,” which “may encode bits of the framed packet received from the
framing circuit 76 . . . and output the encoded bits as a differential driver
input signal.” Spec. ¶ 50. Figure 4, reproduced below depicts “Encode
Logic Circuit 130” without any detail regarding what the elements that
constitute this circuit:

Spec., Fig. 4 (“depicting embodiments of a transmit circuit, an isolator, and a
receive circuit of the communication system”). Spec. ¶ 9.
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Paragraph 50 discloses “encode logic circuit 130,” which is depicted
in Figure 4, and describes the function of that circuit. Spec. ¶ 50, Fig. 4; see
also Spec. ¶ 37 (merely disclosing, at a high level, that the transmit circuit
may encode bits of a packet). Thus, the only structure disclosed in the
Specification corresponding to the recited “means for encoding the plurality
of bits of the framed input data packet as a first data symbol” is the “encode
logic circuit 130.” “It is important to determine whether one of skill in the
art would understand the specification itself to disclose the structure, not
simply whether that person would be capable of implementing that
structure.” Med. Instrumentation & Diagnostics Corp. v. Elekta AB, 344
F.3d 1205, 1212 (Fed. Cir. 2003) (citing Atmel Corp. v. Info. Storage
Devices, Inc., 198 F.3d 1374, 1382 (Fed. Cir. 1999) (“Fulfillment of the
§ 112, ¶ 6 trade-off cannot be satisfied when there is a total omission of
structure. There must be structure in the specification”)). Our reviewing
court held that a claimed circuit, combined with a “description of the
operation of the circuit,” was sufficient structure to avoid invoking
35 U.S.C. § 112(f). See Mass. Inst. of Tech. v. Abacus Software, 432 F.3d
1344, 1354 (Fed. Cir. 2006).2 When evaluating a means plus function
limitation, we similarly analyze the Specification to determine whether it
discloses sufficiently definite structure corresponding to the claimed
function. Thus, even though the Specification describes and depicts
“Encode Logic Circuit 130” without details regarding the particular

2 We note that this decision by the Federal Circuit was before Williamson
eliminated the “strong” presumption that a claim does not invoke 35 U.S.C.
§ 112(f) if the claim does not use the word “means.” Nevertheless,
Massachusetts Institute of Technology has not been overruled.
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components of the circuit necessary to encode the plurality of bits, we
conclude that encode logic circuit 130, which encodes bits of a packet,
represents sufficiently definite structure for performing the corresponding
function recited in claim 23.
Having concluded that encode logic circuit 130 is the corresponding
structure for claim 23’s recited means for encoding, we disagree that the
rejection does not address the means limitation recited in claim 23.
Although the Examiner’s initial findings did not expressly identify the
“means for encoding,” the Examiner sufficiently explained why the findings
apply to the means recited in claim 23. Ans. 3 (“The ‘means for'’ recited in
claim 23 is represented by the ‘encoding circuit’ described in claim 1. The
structural language in claim 1 is supported by the specification in paragraph
50 and illustrated in Figure 4.”). Thus, because the Examiner finds Sundar
teaches both the structure (i.e., “encode logic circuit 130” or its equivalent3)
and the function (“encoding the plurality of bits of the framed input data
packet as a first data symbol”), the rejection is not deficient. See Final
Act. 3–4.

3 To the extent the “encoding circuit” and “means for encoding” are
supported, definite, and enabled, the lack of detail regarding what elements
the encoding circuit comprises suggests that, at the time of Appellant’s
invention, a person of ordinary skill in the art would have known how to
make an encoding circuit configured to perform the recited encoding
function. We also note that, in this particular situation (i.e., given that the
structure supporting claim 23’s recited means is a generic encoding circuit,
which is the same structure recited in claim 1), the Examiner may wish to
consider, at the appropriate time, whether claim 23 is a substantial duplicate
of claim 1 and whether to enter a corresponding objection. See MPEP
§ 7.05.06.
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For these reasons, we disagree that the rejection did not address the
limitations recited in claims 17 and 23.
APPELLANT’S ARGUMENTS THAT THE OFFICE ACTION FAILS TO ARTICULATE
HOW SUNDAR IS MODIFIED IN VIEW OF DUPUIS AND REINGAND
Appellant argues the rejection of claims 1, 2, 17, 18, 23, and 24 is
improper because the Examiner does not explain how Dupuis and Reingand
would be combined with Sundar based on the cited teachings and rationale
to arrive at the claimed invention. Appeal Br. 9–11; Reply Br. 4–5. More
specifically, Appellant argues Sundar and Dupuis are “complicated systems
with many components,” and the rejection includes no explanation regarding
the particular way in which Dupuis’s and Reingand’s cited teachings would
be incorporated into Sundar’s teachings. Appeal Br. 9–11; Reply Br. 4–5.
Appellant argues this deficiency places Appellant “at a disadvantage in
evaluating whether such a modification would have been practical, carried a
reasonable expectation of success, changed the principle of operation of a
reference, or been of a type that the references teach away from, as some
examples.” Appeal Br. 10.
We are not persuaded by this argument. The Examiner’s rejection
relies on similar circuits in Sundar and Dupuis, both of which are used to
transmit data across an isolation barrier. See, e.g., Sundar, Figs. 3, 4;
Dupuis, Figs. 5, 7, 8. For example, Sundar describes Figure 3 as “a high
level block diagram of an isolation system” and Figure 4 as “additional
details of an isolation system.” Sundar ¶¶ 13, 14. Similarly, Dupuis
describes Figure 7 as “a block diagram illustrating a bidirectional isolation
system,” Figure 8 as “a block diagram of a clock recovery and data
synchronization circuit,” and Figure 5 as “a block diagram showing the
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components of [an] exemplary clock recovery circuit.” Dupuis 5:32–41.
Furthermore, the Examiner relies on Sundar to teach or suggest the majority
of the limitations of the isolation circuit recited in claims 1, 17, and 23, and
the Examiner relies on Dupuis as explicitly teaching the isolation barrier and
transmitting and receiving circuits on the same side of the isolation barrier–
i.e., bidirectional communication across the isolation barrier. See Final
Act. 3–5. With respect to claims 2, 18, and 24, the Examiner relies on
Reingand merely for the general concept that an encoding circuit can encode
bits in an input data packet as a selected amplitude, frequency, and/or phase.
Final Act. 7–8 (citing Reingand ¶ 18).4
With respect to independent claims 1, 17, and 23, the rejection, on its
face, sufficiently conveys that the proposed combination involves modifying
Sundar to include transmitting and a receiving circuits on both sides of the
isolation barrier. Given the similarity of the circuits cited in Sundar and
Dupuis and the limited purpose for which the Examiner relies on Dupuis, we
disagree with Appellant that it is unclear how Dupuis’s teachings would be
incorporated into Sundar’s system. Similarly, with respect to claims 2, 18,
and 24, the Examiner’s reliance on Reingand merely to teach the general
concept that various ways of encoding information were known sufficiently
conveys that the Examiner’s proposed combination merely requires
modifying the encoding technique explicitly disclosed in Sundar with any

4 As noted above, Appellant’s Specification provides no details regarding the
circuitry required for the “encoding circuit” or “means for encoding.” As
also noted, to the extent these limitations are enabled, this lack of disclosure
indicates that such encoding circuits and functions were well-known to a
person of ordinary skill in the art at the time of Appellant’s invention such
that the Specification need not disclose the details.
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other known encoding technique, such as those taught in Reingand. See
Sundar ¶ 33 (“While Manchester encoding may be used in certain
embodiments, various other encoding approaches may be utilized with
embodiments described herein.”). Because the arguments addressed above
are Appellant’s only arguments with respect to independent claims 1, 17,
and 23, we sustain the rejection of claims 1, 17, and 23 as obvious over
Sundar and Dupuis.
APPELLANT’S ARGUMENT THAT A PERSON OF ORDINARY SKILL IN THE ART
WOULD NOT HAVE MADE MODIFIED SUNDAR WITH REINGAND AS PROPOSED
Appellant argues the rejection of claims 2, 18, and 24 is improper
because a person of ordinary skill in the art would not have modified Sundar
to incorporate Reingand’s teachings. Appeal Br. 11–12. More specifically,
Appellant argues that Sundar’s encoder “operates on the principle of
Manchester encoding” and, therefore, modifying Sundar’s encoder “to use a
different encoding principle based on Reingand” would have changed
Sundar’s principle of operation. Appeal Br. 12.
Sundar does disclose using Manchester encoding. However, Sundar
explicitly states that other encoding may be used. Specifically, Sundar
discloses that “[w]hile Manchester encoding may be used in certain
embodiments, various other encoding approaches may be utilized with
embodiments described herein.” Sundar ¶ 33. Accordingly, we are not
persuaded that using an encoding other than Manchester encoding would
change Sundar’s principle of operation. Because the arguments addressed
above are Appellant’s only arguments with respect to dependent claims 2,
18, and 24, we sustain the rejection of claims 2, 18, and 24 as obvious over
Sundar, Dupuis, and Reingand.
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APPELLANT’S ARGUMENT THAT THE PROPOSED COMBINATION FAILS TO
TEACH THE LIMITATIONS RECITED IN CLAIM 13
Claim 13, which depends directly from claim 1, recites that the
communication circuit further comprises “a phase locked loop circuit
configured to detect a frequency of the second data symbol.” Appeal Br. 19.
The Examiner finds that Sundar teaches a phase-locked loop circuit as part
of the clock recovery circuit 315, which is part of the circuit that receives an
incoming signal. Final Act. 5 (citing Sundar ¶ 29); Ans. 7; see Sundar ¶ 29
(“The secondary side 303 decodes the received packet . . . deserializer 311
includes clock recovery 315 . . . [and i]n an embodiment a phase-locked loop
may be utilized as part of a clock and data recovery circuit”). The Examiner
also finds Dupuis teaches a phase locked loop circuit. Ans. 7 (citing Dupuis
11:21–23); see Dupuis 11:21–23 (“One section of the clock recovery circuit
may be a phase locked loop (‘PLL’) circuit, consisting of phase/frequency
detector 531.”). The Examiner further explains that the bidirectional
communication circuit resulting from the proposed combination of Sundar
and Dupuis “enables the phase lock loop to be located on either side of the
isolation barrier.” Ans. 7.
Appellant argues the rejection of claim 13 should be reversed. Appeal
Br. 12–13; Reply Br. 6. Specifically, Appellant argues the phase locked
loop circuit that the Examiner cites to in Sundar’s decoding circuit is on the
wrong side of the isolation barrier. Appeal Br. 13. Appellant asserts there is
no evidence in the record to support the finding that a person of ordinary
skill in the art would have included “identical or duplicative components on
both sides of an isolation barrier” merely because the “system exhibits
bidirectional communication.” Reply Br. 6. Appellant further contends
Dupuis itself, which the Examiner relies on as teaching a bidirectional
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communication circuit does not disclose identical components on both sides
of the isolation barrier. Reply Br. 6.
In Figure 7, reproduced below, Dupuis’s bidirectional communication
circuit includes clock recovery circuit 707 only on the right side of the
isolation barrier:

Figure 7 of Dupuis illustrates “a bidirectional isolation system.” Dupuis
5:38–39. Appellant is correct that Dupuis does not include identical
components on both sides of the isolation barrier.
However, we are not persuaded by Appellant’s argument because
claim 13 does not require identical components on both sides of the isolation
barrier. Claim 13 recites that the communication circuit includes a phase
locked loop circuit that detects the frequency of the received second data
symbol. Appeal Br. 19. Claim 13 depends from claim 1, which recites that
the “receive circuit [is] configured to receive [the] second data symbol” and
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that the receive circuit is “on a same side of the isolation barrier as the driver
circuit.” Appeal Br. 18. In other words, the claim merely requires that the
phase locked loop circuit is on the same side of the isolation barrier as a
driver circuit.
As can be seen in Dupuis’s Figure 7, the right side of the circuit
includes clock recovery circuit 707. Dupuis discloses that “[t]he clock
recovery circuit recovers a clock signal from the digital data driven across
the isolation barrier and provides synchronized clock signal 730” and “[t]he
recovered clock operates as the time base for decoder 708.” Dupuis
15:14–18. Dupuis discloses that the “master oscillator” may be on either
side of the circuit and the clock recovery circuit is on the other side in order
to recover a clock signal so that the two sides are synchronized for purposes
of transmitting and receiving signals across the isolation barrier. Dupuis
7:6–17, 7:44–57.
The Examiner correctly finds that both Sundar and Dupuis disclose
inputting a received data signal or symbol into clock recovery circuits that
may be implemented using phase locked loop circuitry. Sundar ¶ 29
(describing the circuitry for receiving a signal across the isolation barrier as
including clock recovery circuitry which may use phase-locked loop
circuitry); Dupuis 11:19–37 (“A preferred embodiment for a clock recovery
circuit 216 for use in this invention is detailed in FIG. 5 and described 20
below. One section of the clock recovery circuit may be a phase locked loop
(‘PLL’) circuit”). Moreover, the Examiner’s proposed combination results
in a driver circuit for driving a data symbol across the isolation barrier on
both sides of the isolation barrier. The proposed combination teaches a
phase locked loop circuit used to detect a frequency of a received symbol on
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the same side of the isolation barrier as a driver circuit configured to drive a
symbol to be transmitted across the isolation barrier. Accordingly, we
sustain the rejection of claim 13 as obvious over Sundar and Dupuis.
APPELLANT’S ARGUMENT THAT THE PROPOSED COMBINATION FAILS TO
TEACH THE ADDITIONAL LIMITATIONS RECITED IN CLAIM 14
Claim 14 depends directly from claim 1 and recites that the
communication circuit further comprises “comprising a mixer circuit and a
delay circuit configured to detect a phase of the second data symbol.”
Appeal Br. 19. The Examiner finds Sundar teaches this limitation in
paragraphs 33, 35, and 36. Final Act. 5. In the Answer, the Examiner also
cites Sundar’s paragraphs 29 and 38 and elements 717 and 721 in Figure 7.
Ans. 8. More specifically, the Examiner finds: paragraph 29 discloses using
a phase-locked loop circuit as part of a clock and data recovery circuit;
paragraphs 35 and 36 disclose “the delay”; paragraph 38 provides additional
details describing “clock recovery logic 717 that recovers a clock, e.g., based
on transitions in the frame” and that “packet decoder and edge position
recovery logic 721 recreate the data on the input channels and supplies the
data to output 723 based on the edge position recovery data”; and that the
bidirectional communication circuit of the proposed combination allows for
the elements in which phase detection occurs to be on either side of the
isolation barrier. Ans. 8.
Appellant argues the combination of Sundar and Dupuis fails to teach
or suggest a mixer that detects a phase of a received second data symbol.
Appeal Br. 14; Reply Br. 7. More specifically, Appellant argues that cited
Sundar neither describes nor depicts a mixer and that the Examiner never
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“identifies what [within the cited portions of Sundar] allegedly represents a
mixer satisfying the requirements of claim 14.” Appeal Br. 14; Reply Br. 7.
The Examiner’s findings regarding Sundar’s cited teachings appear to
be accurate. However, we agree with Appellant that these citations and the
Examiner’s explanation fail to account for the specific structure recited in
claim 14 such that the rejection does not establish a prima facie case of
obviousness. In particular, claim 14 requires “a mixer circuit and a delay
circuit configured to detect a phase of the second data symbol.” Appeal
Br. 19. Although Sundar teaches inputting a received signal into a phase-
locked loop circuit that is part of a clock recovery circuit, the Examiner has
not pointed to elements that teach or suggest a “mixer circuit and a delay”
circuit that perform the recited functions. Nor, to the extent a person of
ordinary skill in the art would have understood Sundar or Dupuis’s phase
lock loop circuits to suggest these recited elements, has the Examiner made
that finding on the record, let alone sufficiently explain, or provide evidence
in support of, such a finding. Accordingly, on this record, we cannot sustain
the rejection of claim 14 as obvious over Sundar and Dupuis.
APPELLANT’S ARGUMENT THAT THE PROPOSED COMBINATION FAILS TO
TEACH THE ADDITIONAL LIMITATIONS RECITED IN CLAIMS 28 AND 29
Claim 28 depends directly from claim 1 and recites that “the framing
circuit is configured to dynamically adjust a number of bits included in the
input data packet.” Appeal Br. 21. The Examiner finds Sundar teaches this
limitation in paragraph 36. Final Act. 6. In the Answer, the Examiner also
cites Sundar’s claims 8 and 14 and explains that “[t]he function of a framer
is to adjust the number of bits to form the data packet.” Ans. 9.
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Appellant argues the rejection of claim 28 is improper because
nothing in Sundar teaches a framing circuit that dynamically adjusts the
number of bits included in a data packet. Appeal Br. 15. Appellant
contends that the Sundar’s paragraph 36 relates to mitigating pulse width
distortion “by sending packets continuously and using edge position
recovery.” Appeal Br. 15 (citing Sundar ¶ 36). Appellant explains that
Sundar’s process to mitigate pulse width distortion adds to a packet bits that
identify an elapsed time since an input transition, wherein the accuracy of
this timing information depends on the number of bits used. Appeal Br. 15
(citing Sundar ¶ 36). Appellant argues that although the accuracy of the
information may depend on the number of bits, these disclosures do not
teach or suggest dynamically adjusting the number of bits included in the
packet. Appeal Br. 15. Appellant further argues the Examiner’s finding that
a framer’s function is to place bits in a packet does not teach the recited
limitation of a circuit (e.g., the framer) configured to dynamically adjust the
number of bits included. Reply Br. 7.
Once again, the Examiner’s findings regarding Sundar’s cited
teachings are accurate, but the rejection lacks a findings that Sundar teaches
or suggests the particular recited feature—i.e., dynamically adjusting a
number of bits included in a packet. Therefore, the rejection does not
establish a prima facie case of obviousness. Although Sundar teaches a
framer configured to place bits into a data packet, we see nothing in Sundar
suggesting that the number of bits included in the input data packet are
dynamically adjusted by the framer. As with the mixer circuit recited in
claim 14, even to the extent a person of ordinary skill in the art would have
understood Sundar or Dupuis’s framing circuits to teach or suggest
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dynamically adjusting the number of bits included in the input data packet,
the Examiner has not made that finding on the record, let alone sufficiently
explained, or provided evidence in support of, such a finding.
Claim 29 directly depends from, and incorporates the limitations of,
claim 28. Therefore, on this record, we cannot sustain the rejection of
claims 28 and 29 as obvious over Sundar and Dupuis.
THE REMAINING CLAIMS NOT ARGUED SEPARATELY
Appellant does not argue the rejections of claims 15, 16, 22, 27, and
30–37 as obvious over Sundar and Dupuis and claims 7 and 10 as obvious
over Sundar, Dupuis, Reingand, and Sasaki separately with particularity.
Accordingly, we also sustain the rejections of these claims for the reasons
explained above.
DECISION SUMMARY
Claims
Rejected
35 U.S.C. § References Affirmed Reversed
1, 13–17, 22,
23, 27–37
103 Sundar, Dupuis 1, 13, 15–17, 22,
23, 27, 30–37
14, 28, 29
2, 18, 24 103 Sundar, Dupuis,
Reingand
2, 18, 24
7, 10 103 Sundar, Dupuis,
Reingand, Sasaki
7, 10
Overall
Outcome
1, 2, 7, 10, 13,
15–18, 22–24,
27, 30–37
14, 28, 29
RESPONSE
No time period for taking any subsequent action in connection with
this appeal may be extended. 37 C.F.R. § 1.136(a)(1)(iv).
AFFIRMED IN PART